@ -86,6 +86,35 @@ _start_e500:
li r1 ,M S R _ D E
mtmsr r1
# ifdef C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0
mfspr r3 ,S P R N _ S V R
rlwinm r3 ,r3 ,0 ,0 x f f
li r4 ,C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0 _ S V R _ R E V
cmpw r3 ,r4
beq 1 f
# ifdef C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0 _ S V R _ R E V 2
li r4 ,C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0 _ S V R _ R E V 2
cmpw r3 ,r4
beq 1 f
# endif
/* Not a supported revision affected by erratum */
li r27 ,0
b 2 f
1 : li r27 ,1 / * R e m e m b e r f o r l a t e r t h a t w e h a v e t h e e r r a t u m * /
/* Erratum says set bits 55:60 to 001001 */
msync
isync
mfspr r3 ,9 7 6
li r4 ,0 x48
rlwimi r3 ,r4 ,0 ,0 x1 f8
mtspr 9 7 6 ,r3
isync
2 :
# endif
# if d e f i n e d ( C O N F I G _ S E C U R E _ B O O T ) & & d e f i n e d ( C O N F I G _ E 5 0 0 M C )
/ * ISBC u s e s L 2 a s s t a c k .
* Disable L 2 c a c h e h e r e s o t h a t u - b o o t c a n e n a b l e i t l a t e r
@ -440,6 +469,14 @@ nexti: mflr r1 /* R1 = our PC */
mfspr r2 , M A S 2
andc r2 , r2 , r3
or r2 , r2 , r1
# ifdef C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0
cmpwi r27 ,0
beq 1 f
andi. r15 , r2 , M A S 2 _ I | M A S 2 _ G / * s a v e t h e o l d I / G f o r l a t e r * /
rlwinm r2 , r2 , 0 , ~ M A S 2 _ I
ori r2 , r2 , M A S 2 _ G
1 :
# endif
mtspr M A S 2 , r2 / * S e t t h e E P N t o o u r P C b a s e a d d r e s s * /
mfspr r2 , M A S 3
@ -719,6 +756,253 @@ delete_temp_tlbs:
tlbwe
# endif / * #i f ( C O N F I G _ S Y S _ C C S R B A R _ D E F A U L T ! = C O N F I G _ S Y S _ C C S R B A R _ P H Y S ) * /
# ifdef C O N F I G _ S Y S _ F S L _ E R R A T U M _ A 0 0 4 5 1 0
# define D C S R _ L A W B A R H 0 ( C O N F I G _ S Y S _ C C S R B A R + 0 x10 0 0 )
# define L A W _ S I Z E _ 1 M 0 x13
# define D C S R B A R _ L A W A R ( L A W _ E N | ( 0 x1 d < < 2 0 ) | L A W _ S I Z E _ 1 M )
cmpwi r27 ,0
beq 9 f
/ *
* Create a T L B e n t r y f o r C C S R
*
* We' r e e x e c u t i n g o u t o f T L B 1 e n t r y i n r14 , a n d t h a t ' s t h e o n l y
* TLB e n t r y t h a t e x i s t s . T o a l l o c a t e s o m e T L B e n t r i e s f o r o u r
* own u s e , f l i p a b i t h i g h e n o u g h t h a t w e w o n ' t f l i p i t a g a i n
* via i n c r e m e n t i n g .
* /
xori r8 , r14 , 3 2
lis r0 , M A S 0 _ T L B S E L ( 1 ) @h
rlwimi r0 , r8 , 1 6 , M A S 0 _ E S E L _ M S K
lis r1 , F S L _ B O O K E _ M A S 1 ( 1 , 1 , 0 , 0 , B O O K E _ P A G E S Z _ 1 6 M ) @h
ori r1 , r1 , F S L _ B O O K E _ M A S 1 ( 1 , 1 , 0 , 0 , B O O K E _ P A G E S Z _ 1 6 M ) @l
lis r7 , C O N F I G _ S Y S _ C C S R B A R @h
ori r7 , r7 , C O N F I G _ S Y S _ C C S R B A R @l
ori r2 , r7 , M A S 2 _ I | M A S 2 _ G
lis r3 , F S L _ B O O K E _ M A S 3 ( C O N F I G _ S Y S _ C C S R B A R _ P H Y S _ L O W , 0 , ( M A S 3 _ S W | M A S 3 _ S R ) ) @h
ori r3 , r3 , F S L _ B O O K E _ M A S 3 ( C O N F I G _ S Y S _ C C S R B A R _ P H Y S _ L O W , 0 , ( M A S 3 _ S W | M A S 3 _ S R ) ) @l
lis r4 , C O N F I G _ S Y S _ C C S R B A R _ P H Y S _ H I G H @h
ori r4 , r4 , C O N F I G _ S Y S _ C C S R B A R _ P H Y S _ H I G H @l
mtspr M A S 0 , r0
mtspr M A S 1 , r1
mtspr M A S 2 , r2
mtspr M A S 3 , r3
mtspr M A S 7 , r4
isync
tlbwe
isync
msync
/* Map DCSR temporarily to physical address zero */
li r0 , 0
lis r3 , D C S R B A R _ L A W A R @h
ori r3 , r3 , D C S R B A R _ L A W A R @l
stw r0 , 0 x c00 ( r7 ) / * L A W B A R H 0 * /
stw r0 , 0 x c04 ( r7 ) / * L A W B A R L 0 * /
sync
stw r3 , 0 x c08 ( r7 ) / * L A W A R 0 * /
/* Read back from LAWAR to ensure the update is complete. */
lwz r3 , 0 x c08 ( r7 ) / * L A W A R 0 * /
isync
/* Create a TLB entry for DCSR at zero */
addi r9 , r8 , 1
lis r0 , M A S 0 _ T L B S E L ( 1 ) @h
rlwimi r0 , r9 , 1 6 , M A S 0 _ E S E L _ M S K
lis r1 , F S L _ B O O K E _ M A S 1 ( 1 , 1 , 0 , 0 , B O O K E _ P A G E S Z _ 1 M ) @h
ori r1 , r1 , F S L _ B O O K E _ M A S 1 ( 1 , 1 , 0 , 0 , B O O K E _ P A G E S Z _ 1 M ) @l
li r6 , 0 / * D C S R e f f e c t i v e a d d r e s s * /
ori r2 , r6 , M A S 2 _ I | M A S 2 _ G
li r3 , M A S 3 _ S W | M A S 3 _ S R
li r4 , 0
mtspr M A S 0 , r0
mtspr M A S 1 , r1
mtspr M A S 2 , r2
mtspr M A S 3 , r3
mtspr M A S 7 , r4
isync
tlbwe
isync
msync
/* enable the timebase */
# define C T B E N R 0 x e 2 0 8 4
li r3 , 1
addis r4 , r7 , C T B E N R @ha
stw r3 , C T B E N R @l(r4)
lwz r3 , C T B E N R @l(r4)
twi 0 ,r3 ,0
isync
.macro erratum_set_ccsr offset v a l u e
addis r3 , r7 , \ o f f s e t @ha
lis r4 , \ v a l u e @h
addi r3 , r3 , \ o f f s e t @l
ori r4 , r4 , \ v a l u e @l
bl e r r a t u m _ s e t _ v a l u e
.endm
.macro erratum_set_dcsr offset v a l u e
addis r3 , r6 , \ o f f s e t @ha
lis r4 , \ v a l u e @h
addi r3 , r3 , \ o f f s e t @l
ori r4 , r4 , \ v a l u e @l
bl e r r a t u m _ s e t _ v a l u e
.endm
erratum_ s e t _ d c s r 0 x b0 e 0 8 0 x e 0 2 0 1 8 0 0
erratum_ s e t _ d c s r 0 x b0 e 1 8 0 x e 0 2 0 1 8 0 0
erratum_ s e t _ d c s r 0 x b0 e 3 8 0 x e 0 4 0 0 0 0 0
erratum_ s e t _ d c s r 0 x b00 0 8 0 x00 9 0 0 0 0 0
erratum_ s e t _ d c s r 0 x b0 e 4 0 0 x e 0 0 a00 0 0
erratum_ s e t _ c c s r 0 x18 6 0 0 C O N F I G _ S Y S _ F S L _ C O R E N E T _ S N O O P V E C _ C O R E O N L Y
erratum_ s e t _ c c s r 0 x10 f00 0 x41 5 e 5 0 0 0
erratum_ s e t _ c c s r 0 x11 f00 0 x41 5 e 5 0 0 0
/* Make temp mapping uncacheable again, if it was initially */
bl 2 f
2 : mflr r3
tlbsx 0 , r3
mfspr r4 , M A S 2
rlwimi r4 , r15 , 0 , M A S 2 _ I
rlwimi r4 , r15 , 0 , M A S 2 _ G
mtspr M A S 2 , r4
isync
tlbwe
isync
msync
/* Clear the cache */
lis r3 ,( L 1 C S R 1 _ I C F I | L 1 C S R 1 _ I C L F R ) @h
ori r3 ,r3 ,( L 1 C S R 1 _ I C F I | L 1 C S R 1 _ I C L F R ) @l
sync
isync
mtspr S P R N _ L 1 C S R 1 ,r3
isync
2 : sync
mfspr r4 ,S P R N _ L 1 C S R 1
and. r4 ,r4 ,r3
bne 2 b
lis r3 ,( L 1 C S R 1 _ C P E | L 1 C S R 1 _ I C E ) @h
ori r3 ,r3 ,( L 1 C S R 1 _ C P E | L 1 C S R 1 _ I C E ) @l
sync
isync
mtspr S P R N _ L 1 C S R 1 ,r3
isync
2 : sync
mfspr r4 ,S P R N _ L 1 C S R 1
and. r4 ,r4 ,r3
beq 2 b
/* Remove temporary mappings */
lis r0 , M A S 0 _ T L B S E L ( 1 ) @h
rlwimi r0 , r9 , 1 6 , M A S 0 _ E S E L _ M S K
li r3 , 0
mtspr M A S 0 , r0
mtspr M A S 1 , r3
isync
tlbwe
isync
msync
li r3 , 0
stw r3 , 0 x c08 ( r7 ) / * L A W A R 0 * /
lwz r3 , 0 x c08 ( r7 )
isync
lis r0 , M A S 0 _ T L B S E L ( 1 ) @h
rlwimi r0 , r8 , 1 6 , M A S 0 _ E S E L _ M S K
li r3 , 0
mtspr M A S 0 , r0
mtspr M A S 1 , r3
isync
tlbwe
isync
msync
b 9 f
/* r3 = addr, r4 = value, clobbers r5, r11, r12 */
erratum_set_value :
/* Lock two cache lines into I-Cache */
sync
mfspr r11 , S P R N _ L 1 C S R 1
rlwinm r11 , r11 , 0 , ~ L 1 C S R 1 _ I C U L
sync
isync
mtspr S P R N _ L 1 C S R 1 , r11
isync
mflr r12
bl 5 f
5 : mflr r5
addi r5 , r5 , 2 f - 5 b
icbtls 0 , 0 , r5
addi r5 , r5 , 6 4
sync
mfspr r11 , S P R N _ L 1 C S R 1
3 : andi. r11 , r11 , L 1 C S R 1 _ I C U L
bne 3 b
icbtls 0 , 0 , r5
addi r5 , r5 , 6 4
sync
mfspr r11 , S P R N _ L 1 C S R 1
3 : andi. r11 , r11 , L 1 C S R 1 _ I C U L
bne 3 b
b 2 f
.align 6
/* Inside a locked cacheline, wait a while, write, then wait a while */
2 : sync
mfspr r5 , S P R N _ T B R L
addis r11 , r5 , 0 x10 0 0 0 @h /* wait 65536 timebase ticks */
4 : mfspr r5 , S P R N _ T B R L
subf. r5 , r5 , r11
bgt 4 b
stw r4 , 0 ( r3 )
mfspr r5 , S P R N _ T B R L
addis r11 , r5 , 0 x10 0 0 0 @h /* wait 65536 timebase ticks */
4 : mfspr r5 , S P R N _ T B R L
subf. r5 , r5 , r11
bgt 4 b
sync
/ *
* Fill o u t t h e r e s t o f t h i s c a c h e l i n e a n d t h e n e x t w i t h n o p s ,
* to e n s u r e t h a t n o t h i n g o u t s i d e t h e l o c k e d a r e a w i l l b e
* fetched d u e t o a b r a n c h .
* /
.rept 19
nop
.endr
sync
mfspr r11 , S P R N _ L 1 C S R 1
rlwinm r11 , r11 , 0 , ~ L 1 C S R 1 _ I C U L
sync
isync
mtspr S P R N _ L 1 C S R 1 , r11
isync
mtlr r12
blr
9 :
# endif
create_init_ram_area :
lis r6 ,F S L _ B O O K E _ M A S 0 ( 1 , 1 5 , 0 ) @h
ori r6 ,r6 ,F S L _ B O O K E _ M A S 0 ( 1 , 1 5 , 0 ) @l