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@ -14,7 +14,6 @@ |
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#define PLL_DIV_1024 1024 |
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#define PLL_DIV_65535 65535 |
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#define PLL_DIV_65536 65536 |
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/* *
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* This structure is to store the src bit, div bit and prediv bit |
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* positions of the peripheral clocks of the src and div registers |
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@ -423,8 +422,8 @@ static unsigned long exynos5_get_periph_rate(int peripheral) |
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case PERIPH_ID_I2C6: |
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case PERIPH_ID_I2C7: |
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src = EXYNOS_SRC_MPLL; |
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div = readl(&clk->div_top0); |
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sub_div = readl(&clk->div_top1); |
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div = readl(&clk->div_top1); |
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sub_div = readl(&clk->div_top0); |
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break; |
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default: |
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debug("%s: invalid peripheral %d", __func__, peripheral); |
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@ -1028,6 +1027,40 @@ static unsigned long exynos5420_get_lcd_clk(void) |
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return pclk; |
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} |
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static unsigned long exynos5800_get_lcd_clk(void) |
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{ |
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struct exynos5420_clock *clk = |
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(struct exynos5420_clock *)samsung_get_base_clock(); |
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unsigned long sclk; |
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unsigned int sel; |
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unsigned int ratio; |
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/*
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* CLK_SRC_DISP10 |
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* CLKMUX_FIMD1 [6:4] |
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*/ |
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sel = (readl(&clk->src_disp10) >> 4) & 0x7; |
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if (sel) { |
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/*
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* Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into |
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* PLLs. The first element is a placeholder to bypass the |
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* default settig. |
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*/ |
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const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, |
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RPLL}; |
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sclk = get_pll_clk(reg_map[sel]); |
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} else |
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sclk = CONFIG_SYS_CLK_FREQ; |
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/*
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* CLK_DIV_DISP10 |
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* FIMD1_RATIO [3:0] |
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*/ |
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ratio = readl(&clk->div_disp10) & 0xf; |
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return sclk / (ratio + 1); |
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} |
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void exynos4_set_lcd_clk(void) |
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{ |
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struct exynos4_clock *clk = |
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@ -1159,6 +1192,28 @@ void exynos5420_set_lcd_clk(void) |
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writel(cfg, &clk->div_disp10); |
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} |
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void exynos5800_set_lcd_clk(void) |
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{ |
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struct exynos5420_clock *clk = |
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(struct exynos5420_clock *)samsung_get_base_clock(); |
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unsigned int cfg; |
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/*
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* Use RPLL for pixel clock |
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* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] |
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* ================== |
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* 111: SCLK_RPLL |
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*/ |
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cfg = readl(&clk->src_disp10) | (0x7 << 4); |
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writel(cfg, &clk->src_disp10); |
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/*
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* CLK_DIV_DISP10 |
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* FIMD1_RATIO [3:0] |
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*/ |
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clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); |
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} |
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void exynos4_set_mipi_clk(void) |
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{ |
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struct exynos4_clock *clk = |
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@ -1646,8 +1701,10 @@ unsigned long get_lcd_clk(void) |
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if (cpu_is_exynos4()) |
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return exynos4_get_lcd_clk(); |
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else { |
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if (proid_is_exynos5420() || proid_is_exynos5800()) |
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if (proid_is_exynos5420()) |
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return exynos5420_get_lcd_clk(); |
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else if (proid_is_exynos5800()) |
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return exynos5800_get_lcd_clk(); |
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else |
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return exynos5_get_lcd_clk(); |
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} |
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@ -1660,8 +1717,10 @@ void set_lcd_clk(void) |
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else { |
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if (proid_is_exynos5250()) |
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exynos5_set_lcd_clk(); |
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else if (proid_is_exynos5420() || proid_is_exynos5800()) |
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else if (proid_is_exynos5420()) |
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exynos5420_set_lcd_clk(); |
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else |
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exynos5800_set_lcd_clk(); |
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} |
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} |
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Tom Rini
9 years ago