As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>master
Stefan Roese
10 years ago
committed by
Tom Rini
parent
dc116bd6c4
commit
345b77baca
@ -1,88 +0,0 @@ |
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
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nandobj := $(OBJTREE)/nand_spl/
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LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
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LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
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$(LDFLAGS_FINAL)
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asflags-y += -DCONFIG_NAND_SPL
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ccflags-y += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o cache.o
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COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
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OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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targets += $(__OBJS)
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all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
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$(nandobj)System.map
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds |
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map -o $@
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$(nandobj)System.map: $(nandobj)u-boot-spl |
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@$(NM) $< | \
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grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
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sort > $@
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$(nandobj)u-boot.lds: $(LDSCRIPT) |
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$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
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# create symbolic links for common files
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# from cpu directory
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$(obj)/cache.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
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$(obj)/gpio.c: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@
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$(obj)/ndfc.c: |
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@rm -f $@
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ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
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$(obj)/resetvec.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
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$(obj)/start.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
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# from board directory
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$(obj)/memory.c: |
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@rm -f $@
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ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@
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$(obj)/pll.c: |
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@rm -f $@
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ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@
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# from nand_spl directory
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$(obj)/nand_boot.c: |
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@rm -f $@
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ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
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# from drivers/mtd/nand directory
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$(obj)/nand_ecc.c: |
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@rm -f $@
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ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
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@ -1,31 +0,0 @@ |
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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# AMCC 405EZ Reference Platform (Acadia) board
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#
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#
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# CONFIG_SYS_TEXT_BASE for SPL:
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#
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# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
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# in the last 4kBytes of memory space in cache.
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# We will copy this SPL into internal SRAM in start.S. So we set
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# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
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#
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CONFIG_SYS_TEXT_BASE = 0xf8004000
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# PAD_TO used to generate a 16kByte binary needed for the combined image
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# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
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PAD_TO = 0xf8008000
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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@ -1,48 +0,0 @@ |
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/* |
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(powerpc:common) |
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SECTIONS |
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{ |
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.resetvec 0xf8004ffc : |
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{ |
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KEEP(*(.resetvec)) |
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} = 0xffff |
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.text : |
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{ |
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start.o (.text) |
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nand_boot.o (.text) |
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ndfc.o (.text) |
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*(.text) |
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*(.fixup) |
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} |
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_etext = .; |
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.data : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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*(.data*) |
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*(.sdata*) |
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__got2_start = .; |
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*(.got2) |
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__got2_end = .; |
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} |
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_edata = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.sbss) |
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*(.bss) |
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. = ALIGN(4); |
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} |
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__bss_end = . ; |
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} |
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@ -1,70 +0,0 @@ |
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
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nandobj := $(OBJTREE)/nand_spl/
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LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
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LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
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$(LDFLAGS_FINAL)
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asflags-y += -DCONFIG_NAND_SPL
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ccflags-y += -DCONFIG_NAND_SPL
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SOBJS = start.o init.o resetvec.o
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COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
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OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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targets += $(__OBJS)
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all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin |
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds |
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map -o $@
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$(nandobj)u-boot.lds: $(LDSCRIPT) |
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$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
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# create symbolic links for common files
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# from cpu directory
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$(obj)/ndfc.c: |
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@rm -f $@
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ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
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$(obj)/resetvec.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
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$(obj)/start.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
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# from board directory
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$(obj)/init.S: |
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@rm -f $@
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ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@
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# from nand_spl directory
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$(obj)/nand_boot.c: |
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@rm -f $@
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ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
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# from drivers/mtd/nand directory
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$(obj)/nand_ecc.c: |
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@rm -f $@
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ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
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@ -1,33 +0,0 @@ |
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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# AMCC 440EP Reference Platform (Bamboo) board
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#
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#
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# CONFIG_SYS_TEXT_BASE for SPL:
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#
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# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
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# in the last 4kBytes of memory space in cache.
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# We will copy this SPL into instruction-cache in start.S. So we set
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# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
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#
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CONFIG_SYS_TEXT_BASE = 0x00800000
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# PAD_TO used to generate a 16kByte binary needed for the combined image
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# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
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PAD_TO = 0x00804000
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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@ -1,76 +0,0 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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static void wait_init_complete(void) |
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{ |
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u32 val; |
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do { |
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mfsdram(SDRAM0_MCSTS, val); |
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} while (!(val & 0x80000000)); |
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} |
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/*
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* phys_size_t initdram(int board_type) |
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* |
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* As the name already indicates, this function is called very early |
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* from start.S and configures the SDRAM with fixed values. This is needed, |
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* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has |
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* not enough free space to implement the complete I2C SPD DDR autodetection |
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* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM |
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* when booting from NAND flash. |
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* |
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* Note: |
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* As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed |
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* DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM |
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* modules are still plugged in. So it is recommended to remove the DIMM |
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* modules while using the NAND booting code with the fixed SDRAM setup! |
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*/ |
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phys_size_t initdram(int board_type) |
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{ |
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/*
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* Soft-reset SDRAM controller. |
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*/ |
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mtsdr(SDR0_SRST, SDR0_SRST_DMC); |
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mtsdr(SDR0_SRST, 0x00000000); |
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/*
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* Disable memory controller. |
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*/ |
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mtsdram(SDRAM0_CFG0, 0x00000000); |
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/*
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* Setup some default |
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*/ |
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mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ |
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mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
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mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ |
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mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ |
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mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ |
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB |
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*/ |
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mtsdram(SDRAM0_B0CR, 0x00082001); |
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mtsdram(SDRAM0_TR0, 0x41094012); |
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mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ |
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mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ |
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mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/ |
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/*
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* Enable the controller, then wait for DCEN to complete |
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*/ |
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mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/ |
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wait_init_complete(); |
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return CONFIG_SYS_MBYTES_SDRAM << 20; |
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} |
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@ -1,50 +0,0 @@ |
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/* |
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(powerpc:common) |
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SECTIONS |
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{ |
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.resetvec 0x00800FFC : |
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{ |
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KEEP(*(.resetvec)) |
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} = 0xffff |
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.text : |
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{ |
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start.o (.text) |
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init.o (.text) |
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nand_boot.o (.text) |
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sdram.o (.text) |
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ndfc.o (.text) |
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|
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*(.text) |
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*(.fixup) |
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} |
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_etext = .; |
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.data : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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*(.data*) |
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*(.sdata*) |
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__got2_start = .; |
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*(.got2) |
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__got2_end = .; |
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} |
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_edata = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.sbss) |
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*(.bss) |
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. = ALIGN(4); |
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} |
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__bss_end = . ; |
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} |
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@ -1,75 +0,0 @@ |
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#
|
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# (C) Copyright 2008
|
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
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nandobj := $(OBJTREE)/nand_spl/
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LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
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LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
|
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$(LDFLAGS_FINAL)
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asflags-y += -DCONFIG_NAND_SPL
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ccflags-y += -DCONFIG_NAND_SPL
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SOBJS := start.o
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SOBJS += init.o
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SOBJS += resetvec.o
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COBJS := ddr2_fixed.o
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COBJS += nand_boot.o
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COBJS += nand_ecc.o
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COBJS += ndfc.o
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OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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targets += $(__OBJS)
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all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin |
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|
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
|
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|
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
|
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|
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds |
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
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-Map $(nandobj)u-boot-spl.map -o $@
|
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|
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$(nandobj)u-boot.lds: $(LDSCRIPT) |
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$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
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|
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# create symbolic links for common files
|
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|
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# from cpu directory
|
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$(obj)/ndfc.c: |
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@rm -f $@
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ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
|
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|
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$(obj)/resetvec.S: |
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@rm -f $@
|
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
|
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|
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$(obj)/start.S: |
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@rm -f $@
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ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
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|
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# from board directory
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$(obj)/init.S: |
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@rm -f $@
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ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@
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|
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# from nand_spl directory
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$(obj)/nand_boot.c: |
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@rm -f $@
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ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
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# from drivers/mtd/nand directory
|
||||
$(obj)/nand_ecc.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
|
||||
@ -1,33 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
#
|
||||
# AMCC 460EX Reference Platform (Canyonlands) board
|
||||
#
|
||||
|
||||
#
|
||||
# CONFIG_SYS_TEXT_BASE for SPL:
|
||||
#
|
||||
# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into internal SRAM in start.S. So we set
|
||||
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0xE3003000
|
||||
|
||||
# PAD_TO used to generate a 128kByte binary needed for the combined image
|
||||
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
|
||||
PAD_TO = 0xE3023000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif |
||||
|
||||
ifeq ($(dbcr),1) |
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif |
||||
@ -1,130 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2008-2009 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/ppc4xx.h> |
||||
#include <asm/io.h> |
||||
#include <asm/processor.h> |
||||
|
||||
/*
|
||||
* This code can configure those two Crucial SODIMM's: |
||||
* |
||||
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) |
||||
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) |
||||
* |
||||
*/ |
||||
|
||||
#define TEST_ADDR 0x10000000 |
||||
#define TEST_MAGIC 0x11223344 |
||||
|
||||
static void wait_init_complete(void) |
||||
{ |
||||
u32 val; |
||||
|
||||
do { |
||||
mfsdram(SDRAM_MCSTAT, val); |
||||
} while (!(val & 0x80000000)); |
||||
} |
||||
|
||||
static void ddr_start(void) |
||||
{ |
||||
mtsdram(SDRAM_MCOPT2, 0x28000000); |
||||
wait_init_complete(); |
||||
} |
||||
|
||||
static void ddr_init_common(void) |
||||
{ |
||||
/*
|
||||
* Reset the DDR-SDRAM controller. |
||||
*/ |
||||
mtsdr(SDR0_SRST, SDR0_SRST0_DMC); |
||||
mtsdr(SDR0_SRST, 0x00000000); |
||||
|
||||
/*
|
||||
* These values are cloned from a running NOR booting |
||||
* Canyonlands with SPD-DDR2 detection and calibration |
||||
* enabled. This will only work for the same memory |
||||
* configuration as used here: |
||||
* |
||||
*/ |
||||
mtsdram(SDRAM_MCOPT2, 0x00000000); |
||||
mtsdram(SDRAM_MODT0, 0x01000000); |
||||
mtsdram(SDRAM_WRDTR, 0x82000823); |
||||
mtsdram(SDRAM_CLKTR, 0x40000000); |
||||
mtsdram(SDRAM_MB0CF, 0x00000201); |
||||
mtsdram(SDRAM_RTR, 0x06180000); |
||||
mtsdram(SDRAM_SDTR1, 0x80201000); |
||||
mtsdram(SDRAM_SDTR2, 0x42103243); |
||||
mtsdram(SDRAM_SDTR3, 0x0A0D0D16); |
||||
mtsdram(SDRAM_MMODE, 0x00000632); |
||||
mtsdram(SDRAM_MEMODE, 0x00000040); |
||||
mtsdram(SDRAM_INITPLR0, 0xB5380000); |
||||
mtsdram(SDRAM_INITPLR1, 0x82100400); |
||||
mtsdram(SDRAM_INITPLR2, 0x80820000); |
||||
mtsdram(SDRAM_INITPLR3, 0x80830000); |
||||
mtsdram(SDRAM_INITPLR4, 0x80810040); |
||||
mtsdram(SDRAM_INITPLR5, 0x80800532); |
||||
mtsdram(SDRAM_INITPLR6, 0x82100400); |
||||
mtsdram(SDRAM_INITPLR7, 0x8A080000); |
||||
mtsdram(SDRAM_INITPLR8, 0x8A080000); |
||||
mtsdram(SDRAM_INITPLR9, 0x8A080000); |
||||
mtsdram(SDRAM_INITPLR10, 0x8A080000); |
||||
mtsdram(SDRAM_INITPLR11, 0x80000432); |
||||
mtsdram(SDRAM_INITPLR12, 0x808103C0); |
||||
mtsdram(SDRAM_INITPLR13, 0x80810040); |
||||
mtsdram(SDRAM_RDCC, 0x40000000); |
||||
mtsdram(SDRAM_RQDC, 0x80000038); |
||||
mtsdram(SDRAM_RFDC, 0x00000257); |
||||
|
||||
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
/*
|
||||
* First try init for this module: |
||||
* |
||||
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank) |
||||
*/ |
||||
|
||||
ddr_init_common(); |
||||
|
||||
/*
|
||||
* Crucial CT6464AC667.8FB - 512MB SO-DIMM |
||||
*/ |
||||
mtdcr(SDRAM_R0BAS, 0x0000F800); |
||||
mtdcr(SDRAM_R1BAS, 0x0400F800); |
||||
mtsdram(SDRAM_MCOPT1, 0x05122000); |
||||
mtsdram(SDRAM_CODT, 0x02800021); |
||||
mtsdram(SDRAM_MB1CF, 0x00000201); |
||||
|
||||
ddr_start(); |
||||
|
||||
/*
|
||||
* Now test if the dual-ranked module is really installed |
||||
* by checking an address in the upper 256MByte region |
||||
*/ |
||||
out_be32((void *)TEST_ADDR, TEST_MAGIC); |
||||
if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) { |
||||
/*
|
||||
* The test failed, so we assume that the single |
||||
* ranked module is installed: |
||||
* |
||||
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank) |
||||
*/ |
||||
|
||||
ddr_init_common(); |
||||
|
||||
mtdcr(SDRAM_R0BAS, 0x0000F000); |
||||
mtsdram(SDRAM_MCOPT1, 0x05322000); |
||||
mtsdram(SDRAM_CODT, 0x00800021); |
||||
|
||||
ddr_start(); |
||||
} |
||||
|
||||
return CONFIG_SYS_MBYTES_SDRAM << 20; |
||||
} |
||||
@ -1,50 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2008 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc:common) |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xE3003FFC : |
||||
{ |
||||
KEEP(*(.resetvec)) |
||||
} = 0xffff |
||||
|
||||
.text : |
||||
{ |
||||
start.o (.text) |
||||
init.o (.text) |
||||
nand_boot.o (.text) |
||||
ddr2_fixed.o (.text) |
||||
ndfc.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
} |
||||
_etext = .; |
||||
|
||||
.data : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
*(.data*) |
||||
*(.sdata*) |
||||
__got2_start = .; |
||||
*(.got2) |
||||
__got2_end = .; |
||||
} |
||||
|
||||
_edata = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
|
||||
__bss_end = . ; |
||||
} |
||||
@ -1,77 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
|
||||
$(LDFLAGS_FINAL)
|
||||
asflags-y += -DCONFIG_NAND_SPL
|
||||
ccflags-y += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o resetvec.o cache.o
|
||||
COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
|
||||
|
||||
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(nandobj)board/$(BOARDDIR)
|
||||
|
||||
targets += $(__OBJS)
|
||||
|
||||
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin |
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds |
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
||||
-Map $(nandobj)u-boot-spl.map -o $@
|
||||
|
||||
$(nandobj)u-boot.lds: $(LDSCRIPT) |
||||
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@
|
||||
|
||||
$(obj)/cache.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@
|
||||
|
||||
$(obj)/ecc.h: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@
|
||||
|
||||
$(obj)/ndfc.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
|
||||
|
||||
$(obj)/resetvec.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
|
||||
|
||||
$(obj)/start.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)/nand_boot.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
|
||||
|
||||
# from drivers/nand directory
|
||||
$(obj)/nand_ecc.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
|
||||
@ -1,32 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
#
|
||||
# AMCC 405EX Reference Platform (Kilauea) board
|
||||
#
|
||||
|
||||
#
|
||||
# CONFIG_SYS_TEXT_BASE for SPL:
|
||||
#
|
||||
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into SDRAM since we can't access the NAND
|
||||
# controller at CS0 while running from this location. So we set
|
||||
# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0x00800000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
|
||||
PAD_TO = 0x00804000
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif |
||||
|
||||
ifeq ($(dbcr),1) |
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif |
||||
@ -1,48 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc:common) |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0x00800FFC : |
||||
{ |
||||
KEEP(*(.resetvec)) |
||||
} = 0xffff |
||||
|
||||
.text : |
||||
{ |
||||
start.o (.text) |
||||
nand_boot.o (.text) |
||||
ndfc.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
} |
||||
_etext = .; |
||||
|
||||
.data : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
*(.data*) |
||||
*(.sdata*) |
||||
__got2_start = .; |
||||
*(.got2) |
||||
__got2_end = .; |
||||
} |
||||
|
||||
_edata = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
|
||||
__bss_end = . ; |
||||
} |
||||
@ -1,80 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2006-2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
|
||||
$(LDFLAGS_FINAL)
|
||||
asflags-y += -DCONFIG_NAND_SPL
|
||||
ccflags-y += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
|
||||
OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(nandobj)board/$(BOARDDIR)
|
||||
|
||||
targets += $(__OBJS)
|
||||
|
||||
all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin |
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
||||
$(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds |
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
||||
-Map $(nandobj)u-boot-spl.map -o $@
|
||||
|
||||
$(nandobj)u-boot.lds: $(LDSCRIPT) |
||||
$(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)/denali_data_eye.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@
|
||||
|
||||
$(obj)/ndfc.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@
|
||||
|
||||
$(obj)/resetvec.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@
|
||||
|
||||
$(obj)/start.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@
|
||||
|
||||
# from board directory
|
||||
$(obj)/init.S: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@
|
||||
|
||||
$(obj)/sdram.c: |
||||
@rm -f $@
|
||||
@rm -f $(obj)/sdram.h
|
||||
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@
|
||||
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)/nand_boot.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
|
||||
|
||||
# from drivers/mtd/nand directory
|
||||
$(obj)/nand_ecc.c: |
||||
@rm -f $@
|
||||
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@
|
||||
@ -1,33 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
#
|
||||
# AMCC 440EPx Reference Platform (Sequoia) board
|
||||
#
|
||||
|
||||
#
|
||||
# CONFIG_SYS_TEXT_BASE for SPL:
|
||||
#
|
||||
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into internal SRAM in start.S. So we set
|
||||
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0xE0013000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
|
||||
PAD_TO = 0xE0017000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif |
||||
|
||||
ifeq ($(dbcr),1) |
||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
||||
endif |
||||
@ -1,50 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2006-2010 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc:common) |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xE0013FFC : |
||||
{ |
||||
KEEP(*(.resetvec)) |
||||
} = 0xffff |
||||
|
||||
.text : |
||||
{ |
||||
start.o (.text) |
||||
init.o (.text) |
||||
nand_boot.o (.text) |
||||
sdram.o (.text) |
||||
ndfc.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
} |
||||
_etext = .; |
||||
|
||||
.data : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
*(.data*) |
||||
*(.sdata*) |
||||
__got2_start = .; |
||||
*(.got2) |
||||
__got2_end = .; |
||||
} |
||||
|
||||
_edata = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) |
||||
*(.bss) |
||||
. = ALIGN(4); |
||||
} |
||||
|
||||
__bss_end = . ; |
||||
} |
||||
Loading…
Reference in new issue