1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>master
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/* |
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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|
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#define __ASSEMBLY__ |
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#include <config.h> |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of spi, sd, eimnor, nand, sata: |
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* spinor: flash_offset: 0x0400 |
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* nand: flash_offset: 0x0400 |
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* sata: flash_offset: 0x0400 |
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* sd/mmc: flash_offset: 0x0400 |
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* eimnor: flash_offset: 0x1000 |
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*/ |
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BOOT_FROM sd |
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|
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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DATA 4 0x020e0798 0x000C0000 |
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DATA 4 0x020e0758 0x00000000 |
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DATA 4 0x020e0588 0x00000030 |
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DATA 4 0x020e0594 0x00000030 |
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DATA 4 0x020e056c 0x00000030 |
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DATA 4 0x020e0578 0x00000030 |
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DATA 4 0x020e074c 0x00000030 |
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DATA 4 0x020e057c 0x00000030 |
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DATA 4 0x020e058c 0x00000000 |
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DATA 4 0x020e059c 0x00000030 |
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DATA 4 0x020e05a0 0x00000030 |
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DATA 4 0x020e078c 0x00000030 |
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DATA 4 0x020e0750 0x00020000 |
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DATA 4 0x020e05a8 0x00000030 |
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DATA 4 0x020e05b0 0x00000030 |
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DATA 4 0x020e0524 0x00000030 |
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DATA 4 0x020e051c 0x00000030 |
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DATA 4 0x020e0518 0x00000030 |
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DATA 4 0x020e050c 0x00000030 |
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DATA 4 0x020e05b8 0x00000030 |
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DATA 4 0x020e05c0 0x00000030 |
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DATA 4 0x020e0774 0x00020000 |
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DATA 4 0x020e0784 0x00000030 |
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DATA 4 0x020e0788 0x00000030 |
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DATA 4 0x020e0794 0x00000030 |
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DATA 4 0x020e079c 0x00000030 |
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DATA 4 0x020e07a0 0x00000030 |
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DATA 4 0x020e07a4 0x00000030 |
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DATA 4 0x020e07a8 0x00000030 |
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DATA 4 0x020e0748 0x00000030 |
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DATA 4 0x020e05ac 0x00000030 |
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DATA 4 0x020e05b4 0x00000030 |
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DATA 4 0x020e0528 0x00000030 |
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DATA 4 0x020e0520 0x00000030 |
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DATA 4 0x020e0514 0x00000030 |
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DATA 4 0x020e0510 0x00000030 |
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DATA 4 0x020e05bc 0x00000030 |
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DATA 4 0x020e05c4 0x00000030 |
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DATA 4 0x021b0800 0xa1390003 |
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DATA 4 0x021b080c 0x001b001e |
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DATA 4 0x021b0810 0x002e0029 |
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DATA 4 0x021b480c 0x001b002a |
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DATA 4 0x021b4810 0x0019002c |
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DATA 4 0x021b083c 0x43240334 |
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DATA 4 0x021b0840 0x0324031a |
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DATA 4 0x021b483c 0x43340344 |
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DATA 4 0x021b4840 0x03280276 |
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DATA 4 0x021b0848 0x44383A3E |
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DATA 4 0x021b4848 0x3C3C3846 |
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DATA 4 0x021b0850 0x2e303230 |
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DATA 4 0x021b4850 0x38283E34 |
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DATA 4 0x021b081c 0x33333333 |
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DATA 4 0x021b0820 0x33333333 |
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DATA 4 0x021b0824 0x33333333 |
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DATA 4 0x021b0828 0x33333333 |
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DATA 4 0x021b481c 0x33333333 |
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DATA 4 0x021b4820 0x33333333 |
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DATA 4 0x021b4824 0x33333333 |
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DATA 4 0x021b4828 0x33333333 |
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DATA 4 0x021b08c0 0x24912492 |
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DATA 4 0x021b48c0 0x24912492 |
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DATA 4 0x021b08b8 0x00000800 |
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DATA 4 0x021b48b8 0x00000800 |
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DATA 4 0x021b0004 0x00020036 |
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DATA 4 0x021b0008 0x09444040 |
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DATA 4 0x021b000c 0x898E7955 |
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DATA 4 0x021b0010 0xFF328F64 |
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DATA 4 0x021b0014 0x01FF00DB |
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DATA 4 0x021b0018 0x00001740 |
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DATA 4 0x021b001c 0x00008000 |
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DATA 4 0x021b002c 0x000026d2 |
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DATA 4 0x021b0030 0x008E1023 |
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DATA 4 0x021b0040 0x00000047 |
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DATA 4 0x021b0400 0x14420000 |
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DATA 4 0x021b0000 0x841A0000 |
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DATA 4 0x00bb0008 0x00000004 |
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DATA 4 0x00bb000c 0x2891E41A |
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DATA 4 0x00bb0038 0x00000564 |
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DATA 4 0x00bb0014 0x00000040 |
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DATA 4 0x00bb0028 0x00000020 |
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DATA 4 0x00bb002c 0x00000020 |
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DATA 4 0x021b001c 0x04088032 |
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DATA 4 0x021b001c 0x00008033 |
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DATA 4 0x021b001c 0x00048031 |
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DATA 4 0x021b001c 0x09408030 |
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DATA 4 0x021b001c 0x04008040 |
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DATA 4 0x021b0020 0x00005800 |
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DATA 4 0x021b0818 0x00011117 |
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DATA 4 0x021b4818 0x00011117 |
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DATA 4 0x021b0004 0x00025576 |
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DATA 4 0x021b0404 0x00011006 |
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DATA 4 0x021b001c 0x00000000 |
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/* set the default clock gate to save power */ |
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DATA 4, 0x020c4068, 0x00C03F3F |
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DATA 4, 0x020c406c, 0x0030FC03 |
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DATA 4, 0x020c4070, 0x0FFFC000 |
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DATA 4, 0x020c4074, 0x3FF00000 |
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DATA 4, 0x020c4078, 0xFFFFF300 |
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DATA 4, 0x020c407c, 0x0F0000F3 |
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DATA 4, 0x020c4080, 0x00000FFF |
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/* enable AXI cache for VDOA/VPU/IPU */ |
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DATA 4, 0x020e0010, 0xF00000CF |
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/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ |
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DATA 4, 0x020e0018, 0x77177717 |
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DATA 4, 0x020e001c, 0x77177717 |
@ -0,0 +1,4 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_MX6QSABREAUTO=y |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6qp.cfg,MX6Q" |
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CONFIG_SPI_FLASH=y |
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