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@ -1,5 +1,5 @@ |
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/* |
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* Cache-handling routined for MIPS 4K CPUs |
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* Cache-handling routined for MIPS CPUs |
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* |
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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* |
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@ -32,10 +32,14 @@ |
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#define RA t8 |
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/* 16KB is the maximum size of instruction and data caches on |
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* MIPS 4K. |
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*/ |
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#define MIPS_MAX_CACHE_SIZE 0x4000 |
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/* |
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* 16kB is the maximum size of instruction and data caches on MIPS 4K, |
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* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. |
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* |
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* Note that the above size is the maximum size of primary cache. U-Boot |
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* doesn't have L2 cache support for now. |
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*/ |
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#define MIPS_MAX_CACHE_SIZE 0x10000 |
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#define INDEX_BASE KSEG0 |
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