This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>master
parent
e5aa8a9b15
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374e78efb0
@ -0,0 +1,628 @@ |
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/dts-v1/; |
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|
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#include <dt-bindings/gpio/x86-gpio.h> |
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/include/ "skeleton.dtsi" |
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/include/ "keyboard.dtsi" |
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/include/ "serial.dtsi" |
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/include/ "rtc.dtsi" |
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/include/ "tsc_timer.dtsi" |
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/ { |
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model = "Google Samus"; |
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compatible = "google,samus", "intel,broadwell"; |
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aliases { |
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spi0 = &spi; |
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usb0 = &usb_0; |
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usb1 = &usb_1; |
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}; |
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config { |
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silent_console = <0>; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "intel,core-i3-gen5"; |
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reg = <0>; |
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intel,apic-id = <0>; |
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intel,slow-ramp = <3>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "intel,core-i3-gen5"; |
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reg = <1>; |
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intel,apic-id = <1>; |
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}; |
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "intel,core-i3-gen5"; |
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reg = <2>; |
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intel,apic-id = <2>; |
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}; |
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "intel,core-i3-gen5"; |
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reg = <3>; |
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intel,apic-id = <3>; |
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}; |
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}; |
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chosen { |
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stdout-path = "/serial"; |
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}; |
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keyboard { |
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intel,duplicate-por; |
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}; |
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pch_pinctrl { |
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compatible = "intel,x86-broadwell-pinctrl"; |
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u-boot,dm-pre-reloc; |
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reg = <0 0>; |
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/* Put this first: it is the default */ |
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gpio_unused: gpio-unused { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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owner = <OWNER_GPIO>; |
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sense-disable; |
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}; |
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gpio_acpi_sci: acpi-sci { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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invert; |
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route = <ROUTE_SCI>; |
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}; |
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gpio_acpi_smi: acpi-smi { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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invert; |
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route = <ROUTE_SMI>; |
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}; |
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gpio_input: gpio-input { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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owner = <OWNER_GPIO>; |
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}; |
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gpio_input_invert: gpio-input-invert { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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owner = <OWNER_GPIO>; |
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invert; |
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}; |
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gpio_native: gpio-native { |
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}; |
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gpio_out_high: gpio-out-high { |
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mode-gpio; |
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direction = <PIN_OUTPUT>; |
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output-value = <1>; |
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owner = <OWNER_GPIO>; |
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sense-disable; |
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}; |
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gpio_out_low: gpio-out-low { |
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mode-gpio; |
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direction = <PIN_OUTPUT>; |
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output-value = <0>; |
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owner = <OWNER_GPIO>; |
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sense-disable; |
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}; |
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gpio_pirq: gpio-pirq { |
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mode-gpio; |
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direction = <PIN_INPUT>; |
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owner = <OWNER_GPIO>; |
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pirq-apic = <PIRQ_APIC_ROUTE>; |
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}; |
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soc_gpio@0 { |
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config = |
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<0 &gpio_unused 0>, /* unused */ |
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<1 &gpio_unused 0>, /* unused */ |
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<2 &gpio_unused 0>, /* unused */ |
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<3 &gpio_unused 0>, /* unused */ |
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<4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */ |
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<5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */ |
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<6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */ |
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<7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */ |
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<8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */ |
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<9 &gpio_input_invert 0>, /* trackpad_int_l (wake) */ |
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<10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */ |
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<11 &gpio_unused 0>, /* unused */ |
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<12 &gpio_unused 0>, /* unused */ |
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<13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */ |
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<14 &gpio_pirq 4>, /* touch_int_l (pirqm) */ |
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<15 &gpio_unused 0>, /* unused (strap) */ |
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<16 &gpio_input 0>, /* pch_wp */ |
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<17 &gpio_unused 0>, /* unused */ |
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<18 &gpio_unused 0>, /* unused */ |
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<19 &gpio_unused 0>, /* unused */ |
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<20 &gpio_native 0>, /* pcie_wlan_clkreq_l */ |
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<21 &gpio_out_high 0>, /* pp3300_ssd_en */ |
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<22 &gpio_unused 0>, /* unused */ |
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<23 &gpio_out_low 0>, /* pp3300_autobahn_en */ |
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<24 &gpio_unused 0>, /* unused */ |
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<25 &gpio_input 0>, /* ec_in_rw */ |
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<26 &gpio_unused 0>, /* unused */ |
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<27 &gpio_acpi_sci 0>, /* pch_wake_l */ |
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<28 &gpio_unused 0>, /* unused */ |
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<29 &gpio_unused 0>, /* unused */ |
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<30 &gpio_native 0>, /* native: pch_suswarn_l */ |
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<31 &gpio_native 0>, /* native: acok_buf */ |
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<32 &gpio_native 0>, /* native: lpc_clkrun_l */ |
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<33 &gpio_native 0>, /* native: ssd_devslp */ |
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<34 &gpio_acpi_smi 0>, /* ec_smi_l */ |
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<35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */ |
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<36 &gpio_acpi_sci 0>, /* ec_sci_l */ |
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<37 &gpio_unused 0>, /* unused */ |
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<38 &gpio_unused 0>, /* unused */ |
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<39 &gpio_unused 0>, /* unused */ |
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<40 &gpio_native 0>, /* native: pch_usb1_oc_l */ |
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<41 &gpio_native 0>, /* native: pch_usb2_oc_l */ |
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<42 &gpio_unused 0>, /* wlan_disable_l */ |
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<43 &gpio_out_high 0>, /* pp1800_codec_en */ |
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<44 &gpio_unused 0>, /* unused */ |
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<45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */ |
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<46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */ |
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<47 &gpio_out_low 0>, /* ssd_reset_l */ |
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<48 &gpio_unused 0>, /* unused */ |
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<49 &gpio_unused 0>, /* unused */ |
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<50 &gpio_unused 0>, /* unused */ |
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<51 &gpio_unused 0>, /* unused */ |
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<52 &gpio_input 0>, /* sim_det */ |
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<53 &gpio_unused 0>, /* unused */ |
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<54 &gpio_unused 0>, /* unused */ |
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<55 &gpio_unused 0>, /* unused */ |
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<56 &gpio_unused 0>, /* unused */ |
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<57 &gpio_out_high 0>, /* codec_reset_l */ |
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<58 &gpio_unused 0>, /* unused */ |
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<59 &gpio_out_high 0>, /* lte_disable_l */ |
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<60 &gpio_unused 0>, /* unused */ |
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<61 &gpio_native 0>, /* native: pch_sus_stat */ |
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<62 &gpio_native 0>, /* native: pch_susclk */ |
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<63 &gpio_native 0>, /* native: pch_slp_s5_l */ |
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<64 &gpio_unused 0>, /* unused */ |
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<65 &gpio_input 0>, /* ram_id3 */ |
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<66 &gpio_input 0>, /* ram_id3_old (strap) */ |
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<67 &gpio_input 0>, /* ram_id0 */ |
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<68 &gpio_input 0>, /* ram_id1 */ |
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<69 &gpio_input 0>, /* ram_id2 */ |
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<70 &gpio_unused 0>, /* unused */ |
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<71 &gpio_native 0>, /* native: modphy_en */ |
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<72 &gpio_unused 0>, /* unused */ |
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<73 &gpio_unused 0>, /* unused */ |
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<74 &gpio_unused 0>, /* unused */ |
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<75 &gpio_unused 0>, /* unused */ |
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<76 &gpio_unused 0>, /* unused */ |
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<77 &gpio_unused 0>, /* unused */ |
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<78 &gpio_unused 0>, /* unused */ |
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<79 &gpio_unused 0>, /* unused */ |
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<80 &gpio_unused 0>, /* unused */ |
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<81 &gpio_unused 0>, /* unused */ |
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<82 &gpio_native 0>, /* native: ec_rcin_l */ |
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<83 &gpio_native 0>, /* gspi0_cs */ |
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<84 &gpio_native 0>, /* gspi0_clk */ |
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<85 &gpio_native 0>, /* gspi0_miso */ |
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<86 &gpio_native 0>, /* gspi0_mosi (strap) */ |
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<87 &gpio_unused 0>, /* unused */ |
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<88 &gpio_unused 0>, /* unused */ |
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<89 &gpio_out_high 0>, /* pp3300_sd_en */ |
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<90 &gpio_unused 0>, /* unused */ |
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<91 &gpio_unused 0>, /* unused */ |
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<92 &gpio_unused 0>, /* unused */ |
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<93 &gpio_unused 0>, /* unused */ |
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<94 &gpio_unused 0>; /* unused */ |
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}; |
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}; |
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pci { |
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compatible = "pci-x86"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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u-boot,dm-pre-reloc; |
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ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 |
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0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 |
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0x01000000 0x0 0x1000 0x1000 0 0xefff>; |
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northbridge@0,0 { |
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reg = <0x00000000 0 0 0 0>; |
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compatible = "intel,broadwell-northbridge"; |
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board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>, |
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<&gpio_c 3 0>, <&gpio_c 1 0>; |
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u-boot,dm-pre-reloc; |
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spd { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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samsung_4 { |
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reg = <6>; |
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data = [91 20 f1 03 04 11 05 0b |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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10 04 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 11 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 80 ce 01 |
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00 00 55 00 00 00 00 00 |
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4b 34 45 38 45 33 30 34 |
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45 44 2d 45 47 43 45 20 |
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20 20 00 00 80 ce 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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hynix-h9ccnnnbltmlar-ntm-lpddr3-32 { |
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/* |
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* banks 8, ranks 2, rows 14, |
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* columns 10, density 4096 mb, x32 |
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*/ |
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reg = <8>; |
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data = [91 20 f1 03 04 11 05 0b |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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10 04 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 01 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 80 ad 00 |
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00 00 55 00 00 00 00 00 |
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48 39 43 43 4e 4e 4e 42 |
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4c 54 4d 4c 41 52 2d 4e |
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54 4d 00 00 80 ad 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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samsung_8 { |
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reg = <10>; |
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data = [91 20 f1 03 04 12 05 0a |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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10 04 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 11 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 80 ce 01 |
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00 00 55 00 00 00 00 00 |
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4b 34 45 36 45 33 30 34 |
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45 44 2d 45 47 43 45 20 |
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20 20 00 00 80 ce 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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hynix-h9ccnnnbltmlar-ntm-lpddr3-16 { |
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/* |
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* banks 8, ranks 2, rows 14, |
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* columns 11, density 4096 mb, x16 |
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*/ |
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reg = <12>; |
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data = [91 20 f1 03 04 12 05 0a |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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10 04 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 01 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 80 ad 00 |
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00 00 55 00 00 00 00 00 |
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48 39 43 43 4e 4e 4e 42 |
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4c 54 4d 4c 41 52 2d 4e |
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54 4d 00 00 80 ad 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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hynix-h9ccnnncltmlar-lpddr3 { |
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/* |
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* banks 8, ranks 2, rows 15, |
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* columns 11, density 8192 mb, x16 |
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*/ |
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reg = <13>; |
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data = [91 20 f1 03 05 1a 05 0a |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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90 06 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 01 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 80 ad 00 |
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00 00 55 00 00 00 00 00 |
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48 39 43 43 4e 4e 4e 43 |
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4c 54 4d 4c 41 52 00 00 |
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00 00 00 00 80 ad 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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elpida-edfb232a1ma { |
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/* |
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* banks 8, ranks 2, rows 15, |
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* columns 11, density 8192 mb, x16 |
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*/ |
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reg = <15>; |
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data = [91 20 f1 03 05 1a 05 0a |
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03 11 01 08 0a 00 50 01 |
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78 78 90 50 90 11 50 e0 |
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90 06 3c 3c 01 90 00 00 |
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00 80 00 00 00 00 00 a8 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 0f 01 02 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 02 fe 00 |
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00 00 00 00 00 00 00 00 |
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45 44 46 42 32 33 32 41 |
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31 4d 41 2d 47 44 2d 46 |
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00 00 00 00 02 fe 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00 |
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00 00 00 00 00 00 00 00]; |
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}; |
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}; |
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}; |
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|
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gma@2,0 { |
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reg = <0x00001000 0 0 0 0>; |
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compatible = "intel,broadwell-igd"; |
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intel,dp-hotplug = <6 6 6>; |
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intel,port-select = <1>; /* eDP */ |
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intel,power-cycle-delay = <6>; |
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intel,power-up-delay = <2000>; |
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intel,power-down-delay = <500>; |
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intel,power-backlight-on-delay = <2000>; |
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intel,power-backlight-off-delay = <2000>; |
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intel,cpu-backlight = <0x00000200>; |
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intel,pch-backlight = <0x04000200>; |
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intel,pre-graphics-delay = <200>; |
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}; |
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|
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me@16,0 { |
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reg = <0x0000b000 0 0 0 0>; |
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compatible = "intel,me"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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usb_1: usb@14,0 { |
||||
reg = <0x0000a000 0 0 0 0>; |
||||
compatible = "xhci-pci"; |
||||
}; |
||||
|
||||
usb_0: usb@1d,0 { |
||||
status = "disabled"; |
||||
reg = <0x0000e800 0 0 0 0>; |
||||
compatible = "ehci-pci"; |
||||
}; |
||||
|
||||
pch@1f,0 { |
||||
reg = <0x0000f800 0 0 0 0>; |
||||
compatible = "intel,broadwell-pch"; |
||||
u-boot,dm-pre-reloc; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b |
||||
0x80 0x80 0x80 0x80>; |
||||
intel,gpi-routing = <0 0 0 0 0 0 0 2 |
||||
1 0 0 0 0 0 0 0>; |
||||
/* Enable EC SMI source */ |
||||
intel,alt-gp-smi-enable = <0x0040>; |
||||
|
||||
/* EC-SCI is GPIO36 */ |
||||
intel,gpe0-en = <0 0x10 0 0>; |
||||
|
||||
power-enable-gpio = <&gpio_a 23 0>; |
||||
|
||||
spi: spi { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "intel,ich9-spi"; |
||||
spi-flash@0 { |
||||
#size-cells = <1>; |
||||
#address-cells = <1>; |
||||
reg = <0>; |
||||
compatible = "winbond,w25q64", |
||||
"spi-flash"; |
||||
memory-map = <0xff800000 0x00800000>; |
||||
rw-mrc-cache { |
||||
label = "rw-mrc-cache"; |
||||
reg = <0x003e0000 0x00010000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
gpio_a: gpioa { |
||||
compatible = "intel,broadwell-gpio"; |
||||
u-boot,dm-pre-reloc; |
||||
#gpio-cells = <2>; |
||||
gpio-controller; |
||||
reg = <0 0>; |
||||
bank-name = "A"; |
||||
}; |
||||
|
||||
gpio_b: gpiob { |
||||
compatible = "intel,broadwell-gpio"; |
||||
u-boot,dm-pre-reloc; |
||||
#gpio-cells = <2>; |
||||
gpio-controller; |
||||
reg = <1 0>; |
||||
bank-name = "B"; |
||||
}; |
||||
|
||||
gpio_c: gpioc { |
||||
compatible = "intel,broadwell-gpio"; |
||||
u-boot,dm-pre-reloc; |
||||
#gpio-cells = <2>; |
||||
gpio-controller; |
||||
reg = <2 0>; |
||||
bank-name = "C"; |
||||
}; |
||||
|
||||
lpc { |
||||
compatible = "intel,broadwell-lpc"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
u-boot,dm-pre-reloc; |
||||
intel,gen-dec = <0x800 0xfc 0x900 0xfc>; |
||||
cros-ec@200 { |
||||
compatible = "google,cros-ec-lpc"; |
||||
reg = <0x204 1 0x200 1 0x880 0x80>; |
||||
|
||||
/* |
||||
* Describes the flash memory within |
||||
* the EC |
||||
*/ |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
flash@8000000 { |
||||
reg = <0x08000000 0x20000>; |
||||
erase-value = <0xff>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
sata@1f,2 { |
||||
compatible = "intel,wildcatpoint-ahci"; |
||||
reg = <0x0000fa00 0 0 0 0>; |
||||
u-boot,dm-pre-reloc; |
||||
intel,sata-mode = "ahci"; |
||||
intel,sata-port-map = <1>; |
||||
intel,sata-port0-gen3-tx = <0x72>; |
||||
reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>; |
||||
}; |
||||
|
||||
smbus: smbus@1f,3 { |
||||
compatible = "intel,ich-i2c"; |
||||
reg = <0x0000fb00 0 0 0 0>; |
||||
u-boot,dm-pre-reloc; |
||||
}; |
||||
}; |
||||
|
||||
tpm { |
||||
reg = <0xfed40000 0x5000>; |
||||
compatible = "infineon,slb9635lpc"; |
||||
}; |
||||
|
||||
microcode { |
||||
update@0 { |
||||
#include "microcode/mc0306d4_00000018.dtsi" |
||||
}; |
||||
}; |
||||
|
||||
}; |
@ -0,0 +1,40 @@ |
||||
if TARGET_CHROMEBOOK_SAMUS |
||||
|
||||
config SYS_BOARD |
||||
default "chromebook_samus" |
||||
|
||||
config SYS_VENDOR |
||||
default "google" |
||||
|
||||
config SYS_SOC |
||||
default "broadwell" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "chromebook_samus" |
||||
|
||||
config SYS_TEXT_BASE |
||||
default 0xffe00000 |
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy |
||||
def_bool y |
||||
select X86_RESET_VECTOR |
||||
select INTEL_BROADWELL |
||||
select HAVE_INTEL_ME |
||||
select BOARD_ROMSIZE_KB_8192 |
||||
|
||||
config PCIE_ECAM_BASE |
||||
default 0xf0000000 |
||||
|
||||
config EARLY_POST_CROS_EC |
||||
bool "Enable early post to Chrome OS EC" |
||||
default y |
||||
|
||||
config SYS_CAR_ADDR |
||||
hex |
||||
default 0xff7c0000 |
||||
|
||||
config SYS_CAR_SIZE |
||||
hex |
||||
default 0x40000 |
||||
|
||||
endif |
@ -0,0 +1,6 @@ |
||||
CHROMEBOOK SAMUS BOARD |
||||
M: Simon Glass <sjg@chromium.org> |
||||
S: Maintained |
||||
F: board/google/chromebook_samus/ |
||||
F: include/configs/chromebook_samus.h |
||||
F: configs/chromebook_samus_defconfig |
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (c) 2016 Google, Inc
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += samus.o
|
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/cpu.h> |
||||
|
||||
int arch_early_init_r(void) |
||||
{ |
||||
return cpu_run_reference_code(); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
return 0; |
||||
} |
@ -0,0 +1,51 @@ |
||||
CONFIG_X86=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x1800 |
||||
CONFIG_VENDOR_GOOGLE=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" |
||||
CONFIG_TARGET_CHROMEBOOK_SAMUS=y |
||||
CONFIG_ENABLE_MRC_CACHE=y |
||||
CONFIG_HAVE_MRC=y |
||||
CONFIG_HAVE_REFCODE=y |
||||
CONFIG_SMP=y |
||||
CONFIG_HAVE_VGA_BIOS=y |
||||
CONFIG_CMD_CPU=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_NFS is not set |
||||
CONFIG_BOOTSTAGE=y |
||||
CONFIG_BOOTSTAGE_REPORT=y |
||||
CONFIG_CMD_BOOTSTAGE=y |
||||
CONFIG_CMD_TPM=y |
||||
CONFIG_CMD_TPM_TEST=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_CPU=y |
||||
CONFIG_INTEL_BROADWELL_GPIO=y |
||||
CONFIG_CMD_CROS_EC=y |
||||
CONFIG_CROS_EC=y |
||||
CONFIG_CROS_EC_LPC=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_GIGADEVICE=y |
||||
CONFIG_SPI_FLASH_MACRONIX=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_DM_RTC=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_DEBUG_UART_BASE=0x3f8 |
||||
CONFIG_DEBUG_UART_CLOCK=1843200 |
||||
CONFIG_DEBUG_UART_BOARD_INIT=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_ICH_SPI=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_TPM_TIS_LPC=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_DM_VIDEO=y |
||||
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
||||
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y |
||||
CONFIG_VIDEO_BROADWELL_IGD=y |
||||
CONFIG_USE_PRIVATE_LIBGCC=y |
||||
CONFIG_TPM=y |
@ -0,0 +1,29 @@ |
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors. |
||||
* (C) Copyright 2008 |
||||
* Graeme Russ, graeme.russ@gmail.com. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <configs/x86-common.h> |
||||
#include <configs/x86-chromebook.h> |
||||
|
||||
#undef CONFIG_CFB_CONSOLE |
||||
|
||||
#undef CONFIG_STD_DEVICES_SETTINGS |
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ |
||||
"stdout=vidconsole,serial\0" \
|
||||
"stderr=vidconsole,serial\0" |
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000 |
||||
#define CONFIG_ENV_OFFSET 0x003f8000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue