sunxi: usb: Move setup of host controller clocks to the host controller drivers

The sunxi "usbc" code is mostly about phy setup, but currently also sets up
the host controller clocks, which is something which really belongs in the
host controller drivers, so move it there.

This is a preparation patch for moving the sunxi ehci code to the driver
model and for adding ohci support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

arch/arm/cpu/armv7/sunxi/usbc.c

@@ -11,12 +11,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/usbc.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <common.h>
 #include <errno.h>
 #ifdef CONFIG_AXP152_POWER
 #include <axp152.h>
@@ -44,25 +44,21 @@
 static struct sunxi_usbc_hcd {
 	struct usb_hcd *hcd;
 	int usb_rst_mask;
-	int ahb_clk_mask;
 	int gpio_vbus;
 	int gpio_vbus_det;
 	int id;
 } sunxi_usbc_hcd[] = {
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
-		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB0,
 		.id = 0,
 	},
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
-		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
 		.id = 1,
 	},
 #if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
-		.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
 		.id = 2,
 	}
 #endif
@@ -227,10 +223,6 @@ void sunxi_usbc_enable(int index)
 		setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
 
 	setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
-	setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
-#endif
 
 	sunxi_usb_phy_init(sunxi_usbc);
 
@@ -248,10 +240,6 @@ void sunxi_usbc_disable(int index)
 	if (sunxi_usbc->id != 0)
 		sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
 
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-	clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
-#endif
-	clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
 	clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
 
 	/* disable common PHY only once, for the last enabled hcd */

drivers/usb/host/ehci-sunxi.c

@@ -9,19 +9,29 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <asm/arch/usbc.h>
 #include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/usbc.h>
+#include <asm/io.h>
 #include "ehci.h"
 
 int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 		struct ehci_hcor **hcor)
 {
-	int err;
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int ahb_gate_offset, err;
 
 	err = sunxi_usbc_request_resources(index + 1);
 	if (err)
 		return err;
 
+	ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
+				  AHB_GATE_OFFSET_USB_EHCI0;
+	setbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
+#endif
+
 	sunxi_usbc_enable(index + 1);
 	sunxi_usbc_vbus_enable(index + 1);
 
@@ -39,8 +49,18 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
 
 int ehci_hcd_stop(int index)
 {
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	int ahb_gate_offset;
+
 	sunxi_usbc_vbus_disable(index + 1);
 	sunxi_usbc_disable(index + 1);
 
+	ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
+				  AHB_GATE_OFFSET_USB_EHCI0;
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
+#endif
+	clrbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
+
 	return sunxi_usbc_free_resources(index + 1);
 }

drivers/usb/musb-new/sunxi.c

@@ -22,6 +22,7 @@
  */
 #include <common.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/usbc.h>
 #include <asm-generic/gpio.h>
@@ -219,11 +220,24 @@ static void sunxi_musb_enable(struct musb *musb)
 
 static void sunxi_musb_disable(struct musb *musb)
 {
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
 	pr_debug("%s():\n", __func__);
 
 	/* Put the controller back in a pristane state for "usb reset" */
 	if (musb->is_active) {
 		sunxi_usbc_disable(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+		clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+		clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
+		mdelay(10);
+
+		setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+		setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
 		sunxi_usbc_enable(0);
 		musb->is_active = 0;
 	}
@@ -231,6 +245,7 @@ static void sunxi_musb_disable(struct musb *musb)
 
 static int sunxi_musb_init(struct musb *musb)
 {
+	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	int err;
 
 	pr_debug("%s():\n", __func__);
@@ -249,6 +264,11 @@ static int sunxi_musb_init(struct musb *musb)
 	}
 
 	musb->isr = sunxi_musb_interrupt;
+
+	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
 	sunxi_usbc_enable(0);
 
 	USBC_ConfigFIFO_Base();