Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules 3. Setting up the right voltage on voltage rails This work draws upon previous work done for x-loader by: Santosh Shilimkar <santosh.shilimkar@ti.com> Rajendra Nayak <rnayak@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
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/*
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* |
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* Clock initialization for OMAP4 |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* |
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* Based on previous work by: |
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* Santosh Shilimkar <santosh.shilimkar@ti.com> |
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* Rajendra Nayak <rnayak@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/omap_common.h> |
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#include <asm/arch/clocks.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/utils.h> |
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#ifndef CONFIG_SPL_BUILD |
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/*
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* printing to console doesn't work unless |
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* this code is executed from SPL |
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*/ |
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#define printf(fmt, args...) |
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#define puts(s) |
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#endif |
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#define abs(x) (((x) < 0) ? ((x)*-1) : (x)) |
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struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; |
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static const u32 sys_clk_array[8] = { |
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12000000, /* 12 MHz */ |
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13000000, /* 13 MHz */ |
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16800000, /* 16.8 MHz */ |
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19200000, /* 19.2 MHz */ |
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26000000, /* 26 MHz */ |
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27000000, /* 27 MHz */ |
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38400000, /* 38.4 MHz */ |
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}; |
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/*
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* The M & N values in the following tables are created using the |
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* following tool: |
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* tools/omap/clocks_get_m_n.c |
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* Please use this tool for creating the table for any new frequency. |
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*/ |
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/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */ |
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static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = { |
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{66, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{792, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{330, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{165, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{396, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{88, 2, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{165, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ |
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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { |
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{50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { |
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{200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { |
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{127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params |
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core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { |
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{200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ |
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{800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ |
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{619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ |
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{125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ |
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{400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ |
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{800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ |
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{125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { |
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{64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ |
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{768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ |
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{320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ |
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{40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ |
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{384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ |
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{256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ |
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{20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ |
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}; |
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static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { |
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{931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ |
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{931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ |
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{665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ |
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{727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ |
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{931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ |
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{931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ |
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{412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ |
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}; |
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/* ABE M & N values with sys_clk as source */ |
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static const struct dpll_params |
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
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{49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ |
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{68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ |
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{35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ |
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{29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ |
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{64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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/* ABE M & N values with 32K clock as source */ |
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static const struct dpll_params abe_dpll_params_32k_196608khz = { |
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750, 0, 1, 1, -1, -1, -1, -1 |
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}; |
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
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{80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ |
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{960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ |
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{400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
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{50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
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{480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ |
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{320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ |
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{25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
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}; |
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static inline u32 __get_sys_clk_index(void) |
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{ |
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u32 ind; |
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/*
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* For ES1 the ROM code calibration of sys clock is not reliable |
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* due to hw issue. So, use hard-coded value. If this value is not |
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* correct for any board over-ride this function in board file |
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* From ES2.0 onwards you will get this information from |
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* CM_SYS_CLKSEL |
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*/ |
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if (omap_revision() == OMAP4430_ES1_0) |
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ind = OMAP_SYS_CLK_IND_38_4_MHZ; |
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else { |
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/* SYS_CLKSEL - 1 to match the dpll param array indices */ |
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ind = (readl(&prcm->cm_sys_clksel) & |
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CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; |
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} |
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return ind; |
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} |
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u32 get_sys_clk_index(void) |
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__attribute__ ((weak, alias("__get_sys_clk_index"))); |
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u32 get_sys_clk_freq(void) |
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{ |
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u8 index = get_sys_clk_index(); |
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return sys_clk_array[index]; |
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} |
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static inline void do_bypass_dpll(u32 *const base) |
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{ |
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struct dpll_regs *dpll_regs = (struct dpll_regs *)base; |
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
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CM_CLKMODE_DPLL_DPLL_EN_MASK, |
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DPLL_EN_FAST_RELOCK_BYPASS << |
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CM_CLKMODE_DPLL_EN_SHIFT); |
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} |
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static inline void wait_for_bypass(u32 *const base) |
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{ |
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, |
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LDELAY)) { |
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printf("Bypassing DPLL failed %p\n", base); |
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} |
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} |
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static inline void do_lock_dpll(u32 *const base) |
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{ |
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
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clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, |
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CM_CLKMODE_DPLL_DPLL_EN_MASK, |
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); |
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} |
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static inline void wait_for_lock(u32 *const base) |
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{ |
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, |
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&dpll_regs->cm_idlest_dpll, LDELAY)) { |
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printf("DPLL locking failed for %p\n", base); |
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hang(); |
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} |
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} |
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static void do_setup_dpll(u32 *const base, const struct dpll_params *params, |
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u8 lock) |
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{ |
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u32 temp; |
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struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; |
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bypass_dpll(base); |
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/* Set M & N */ |
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temp = readl(&dpll_regs->cm_clksel_dpll); |
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temp &= ~CM_CLKSEL_DPLL_M_MASK; |
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; |
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temp &= ~CM_CLKSEL_DPLL_N_MASK; |
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; |
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writel(temp, &dpll_regs->cm_clksel_dpll); |
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/* Lock */ |
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if (lock) |
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do_lock_dpll(base); |
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/* Setup post-dividers */ |
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if (params->m2 >= 0) |
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writel(params->m2, &dpll_regs->cm_div_m2_dpll); |
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if (params->m3 >= 0) |
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writel(params->m3, &dpll_regs->cm_div_m3_dpll); |
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if (params->m4 >= 0) |
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writel(params->m4, &dpll_regs->cm_div_m4_dpll); |
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if (params->m5 >= 0) |
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writel(params->m5, &dpll_regs->cm_div_m5_dpll); |
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if (params->m6 >= 0) |
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writel(params->m6, &dpll_regs->cm_div_m6_dpll); |
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if (params->m7 >= 0) |
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writel(params->m7, &dpll_regs->cm_div_m7_dpll); |
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/* Wait till the DPLL locks */ |
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if (lock) |
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wait_for_lock(base); |
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} |
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const struct dpll_params *get_core_dpll_params(void) |
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{ |
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u32 sysclk_ind = get_sys_clk_index(); |
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switch (omap_revision()) { |
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case OMAP4430_ES1_0: |
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return &core_dpll_params_es1_1524mhz[sysclk_ind]; |
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case OMAP4430_ES2_0: |
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case OMAP4430_SILICON_ID_INVALID: |
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/* safest */ |
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return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; |
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default: |
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return &core_dpll_params_1600mhz[sysclk_ind]; |
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} |
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} |
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u32 omap4_ddr_clk(void) |
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{ |
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u32 ddr_clk, sys_clk_khz; |
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const struct dpll_params *core_dpll_params; |
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sys_clk_khz = get_sys_clk_freq() / 1000; |
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core_dpll_params = get_core_dpll_params(); |
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debug("sys_clk %d\n ", sys_clk_khz * 1000); |
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/* Find Core DPLL locked frequency first */ |
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ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / |
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(core_dpll_params->n + 1); |
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/*
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* DDR frequency is PHY_ROOT_CLK/2 |
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* PHY_ROOT_CLK = Fdpll/2/M2 |
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*/ |
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ddr_clk = ddr_clk / 4 / core_dpll_params->m2; |
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ddr_clk *= 1000; /* convert to Hz */ |
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debug("ddr_clk %d\n ", ddr_clk); |
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return ddr_clk; |
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} |
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static void setup_dplls(void) |
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{ |
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u32 sysclk_ind, temp; |
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const struct dpll_params *params; |
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debug("setup_dplls\n"); |
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sysclk_ind = get_sys_clk_index(); |
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/* CORE dpll */ |
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params = get_core_dpll_params(); /* default - safest */ |
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/*
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* Do not lock the core DPLL now. Just set it up. |
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* Core DPLL will be locked after setting up EMIF |
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* using the FREQ_UPDATE method(freq_update_core()) |
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*/ |
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do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK); |
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/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ |
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temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | |
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(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | |
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(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); |
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writel(temp, &prcm->cm_clksel_core); |
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debug("Core DPLL configured\n"); |
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/* lock PER dpll */ |
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do_setup_dpll(&prcm->cm_clkmode_dpll_per, |
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&per_dpll_params_1536mhz[sysclk_ind], DPLL_LOCK); |
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debug("PER DPLL locked\n"); |
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/* MPU dpll */ |
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if (omap_revision() == OMAP4430_ES1_0) |
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params = &mpu_dpll_params_1200mhz[sysclk_ind]; |
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else |
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params = &mpu_dpll_params_1584mhz[sysclk_ind]; |
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do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK); |
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debug("MPU DPLL locked\n"); |
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} |
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static void setup_non_essential_dplls(void) |
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{ |
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u32 sys_clk_khz, abe_ref_clk; |
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u32 sysclk_ind, sd_div, num, den; |
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const struct dpll_params *params; |
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sysclk_ind = get_sys_clk_index(); |
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sys_clk_khz = get_sys_clk_freq() / 1000; |
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/* IVA */ |
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clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, |
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CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); |
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do_setup_dpll(&prcm->cm_clkmode_dpll_iva, |
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&iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); |
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/*
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* USB: |
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* USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction |
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* DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) |
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* - where CLKINP is sys_clk in MHz |
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* Use CLKINP in KHz and adjust the denominator accordingly so |
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* that we have enough accuracy and at the same time no overflow |
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*/ |
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params = &usb_dpll_params_1920mhz[sysclk_ind]; |
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num = params->m * sys_clk_khz; |
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den = (params->n + 1) * 250 * 1000; |
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num += den - 1; |
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sd_div = num / den; |
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clrsetbits_le32(&prcm->cm_clksel_dpll_usb, |
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CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, |
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sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); |
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/* Now setup the dpll with the regular function */ |
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do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); |
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#ifdef CONFIG_SYS_OMAP4_ABE_SYSCK |
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params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; |
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; |
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#else |
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params = &abe_dpll_params_32k_196608khz; |
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; |
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/*
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* We need to enable some additional options to achieve |
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* 196.608MHz from 32768 Hz |
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*/ |
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setbits_le32(&prcm->cm_clkmode_dpll_abe, |
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CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| |
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CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| |
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CM_CLKMODE_DPLL_LPMODE_EN_MASK| |
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CM_CLKMODE_DPLL_REGM4XEN_MASK); |
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/* Spend 4 REFCLK cycles at each stage */ |
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clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, |
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CM_CLKMODE_DPLL_RAMP_RATE_MASK, |
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1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); |
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#endif |
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/* Select the right reference clk */ |
||||
clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, |
||||
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, |
||||
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); |
||||
/* Lock the dpll */ |
||||
do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); |
||||
} |
||||
|
||||
static void do_scale_vcore(u32 vcore_reg, u32 volt_mv) |
||||
{ |
||||
u32 temp, offset_code; |
||||
u32 step = 12660; /* 12.66 mV represented in uV */ |
||||
u32 offset = volt_mv; |
||||
|
||||
/* convert to uV for better accuracy in the calculations */ |
||||
offset *= 1000; |
||||
|
||||
if (omap_revision() == OMAP4430_ES1_0) |
||||
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; |
||||
else |
||||
offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; |
||||
|
||||
offset_code = (offset + step - 1) / step; |
||||
/* The code starts at 1 not 0 */ |
||||
offset_code++; |
||||
|
||||
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, |
||||
offset_code); |
||||
|
||||
temp = SMPS_I2C_SLAVE_ADDR | |
||||
(vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) | |
||||
(offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) | |
||||
PRM_VC_VAL_BYPASS_VALID_BIT; |
||||
writel(temp, &prcm->prm_vc_val_bypass); |
||||
if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0, |
||||
&prcm->prm_vc_val_bypass, LDELAY)) { |
||||
printf("Scaling voltage failed for 0x%x\n", vcore_reg); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
||||
* We set the maximum voltages allowed here because Smart-Reflex is not |
||||
* enabled in bootloader. Voltage initialization in the kernel will set |
||||
* these to the nominal values after enabling Smart-Reflex |
||||
*/ |
||||
static void scale_vcores(void) |
||||
{ |
||||
u32 volt, sys_clk_khz, cycles_hi, cycles_low, temp; |
||||
|
||||
sys_clk_khz = get_sys_clk_freq() / 1000; |
||||
|
||||
/*
|
||||
* Setup the dedicated I2C controller for Voltage Control |
||||
* I2C clk - high period 40% low period 60% |
||||
*/ |
||||
cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; |
||||
cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10; |
||||
/* values to be set in register - less by 5 & 7 respectively */ |
||||
cycles_hi -= 5; |
||||
cycles_low -= 7; |
||||
temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | |
||||
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); |
||||
writel(temp, &prcm->prm_vc_cfg_i2c_clk); |
||||
|
||||
/* Disable high speed mode and all advanced features */ |
||||
writel(0x0, &prcm->prm_vc_cfg_i2c_mode); |
||||
|
||||
/*
|
||||
* VCORE 1 - 4430 : supplies vdd_mpu |
||||
* Setting a high voltage for Nitro mode as smart reflex is not enabled. |
||||
* We use the maximum possible value in the AVS range because the next |
||||
* higher voltage in the discrete range (code >= 0b111010) is way too |
||||
* high |
||||
*/ |
||||
volt = 1417; |
||||
do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
||||
|
||||
/* VCORE 2 - supplies vdd_iva */ |
||||
volt = 1200; |
||||
do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
||||
|
||||
/* VCORE 3 - supplies vdd_core */ |
||||
volt = 1200; |
||||
do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); |
||||
} |
||||
|
||||
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) |
||||
{ |
||||
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, |
||||
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); |
||||
debug("Enable clock domain - 0x%08x\n", clkctrl_reg); |
||||
} |
||||
|
||||
static inline void wait_for_clk_enable(u32 *clkctrl_addr) |
||||
{ |
||||
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; |
||||
u32 bound = LDELAY; |
||||
|
||||
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || |
||||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { |
||||
|
||||
clkctrl = readl(clkctrl_addr); |
||||
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> |
||||
MODULE_CLKCTRL_IDLEST_SHIFT; |
||||
if (--bound == 0) { |
||||
printf("Clock enable failed for 0x%p idlest 0x%x\n", |
||||
clkctrl_addr, clkctrl); |
||||
return; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, |
||||
u32 wait_for_enable) |
||||
{ |
||||
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, |
||||
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); |
||||
debug("Enable clock module - 0x%08x\n", clkctrl_addr); |
||||
if (wait_for_enable) |
||||
wait_for_clk_enable(clkctrl_addr); |
||||
} |
||||
|
||||
/*
|
||||
* Enable essential clock domains, modules and |
||||
* do some additional special settings needed |
||||
*/ |
||||
static void enable_basic_clocks(void) |
||||
{ |
||||
u32 i, max = 100, wait_for_enable = 1; |
||||
u32 *const clk_domains_essential[] = { |
||||
&prcm->cm_l4per_clkstctrl, |
||||
&prcm->cm_l3init_clkstctrl, |
||||
&prcm->cm_memif_clkstctrl, |
||||
&prcm->cm_l4cfg_clkstctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_hw_auto_essential[] = { |
||||
&prcm->cm_wkup_gpio1_clkctrl, |
||||
&prcm->cm_l4per_gpio2_clkctrl, |
||||
&prcm->cm_l4per_gpio3_clkctrl, |
||||
&prcm->cm_l4per_gpio4_clkctrl, |
||||
&prcm->cm_l4per_gpio5_clkctrl, |
||||
&prcm->cm_l4per_gpio6_clkctrl, |
||||
&prcm->cm_memif_emif_1_clkctrl, |
||||
&prcm->cm_memif_emif_2_clkctrl, |
||||
&prcm->cm_l3init_hsusbotg_clkctrl, |
||||
&prcm->cm_l3init_usbphy_clkctrl, |
||||
&prcm->cm_l4cfg_l4_cfg_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_explicit_en_essential[] = { |
||||
&prcm->cm_l4per_gptimer2_clkctrl, |
||||
&prcm->cm_l3init_hsmmc1_clkctrl, |
||||
&prcm->cm_l3init_hsmmc2_clkctrl, |
||||
&prcm->cm_l4per_mcspi1_clkctrl, |
||||
&prcm->cm_wkup_gptimer1_clkctrl, |
||||
&prcm->cm_l4per_i2c1_clkctrl, |
||||
&prcm->cm_l4per_i2c2_clkctrl, |
||||
&prcm->cm_l4per_i2c3_clkctrl, |
||||
&prcm->cm_l4per_i2c4_clkctrl, |
||||
&prcm->cm_wkup_wdtimer2_clkctrl, |
||||
&prcm->cm_l4per_uart3_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
/* Enable optional additional functional clock for GPIO4 */ |
||||
setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, |
||||
GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
/* Enable 96 MHz clock for MMC1 & MMC2 */ |
||||
setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, |
||||
HSMMC_CLKCTRL_CLKSEL_MASK); |
||||
setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, |
||||
HSMMC_CLKCTRL_CLKSEL_MASK); |
||||
|
||||
/* Select 32KHz clock as the source of GPTIMER1 */ |
||||
setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, |
||||
GPTIMER1_CLKCTRL_CLKSEL_MASK); |
||||
|
||||
/* Enable optional 48M functional clock for USB PHY */ |
||||
setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, |
||||
USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); |
||||
|
||||
/* Put the clock domains in SW_WKUP mode */ |
||||
for (i = 0; (i < max) && clk_domains_essential[i]; i++) { |
||||
enable_clock_domain(clk_domains_essential[i], |
||||
CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
||||
} |
||||
|
||||
/* Clock modules that need to be put in HW_AUTO */ |
||||
for (i = 0; (i < max) && clk_modules_hw_auto_essential[i]; i++) { |
||||
enable_clock_module(clk_modules_hw_auto_essential[i], |
||||
MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
||||
wait_for_enable); |
||||
}; |
||||
|
||||
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
||||
for (i = 0; (i < max) && clk_modules_explicit_en_essential[i]; i++) { |
||||
enable_clock_module(clk_modules_explicit_en_essential[i], |
||||
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
||||
wait_for_enable); |
||||
}; |
||||
|
||||
/* Put the clock domains in HW_AUTO mode now */ |
||||
for (i = 0; (i < max) && clk_domains_essential[i]; i++) { |
||||
enable_clock_domain(clk_domains_essential[i], |
||||
CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Enable non-essential clock domains, modules and |
||||
* do some additional special settings needed |
||||
*/ |
||||
static void enable_non_essential_clocks(void) |
||||
{ |
||||
u32 i, max = 100, wait_for_enable = 0; |
||||
u32 *const clk_domains_non_essential[] = { |
||||
&prcm->cm_mpu_m3_clkstctrl, |
||||
&prcm->cm_ivahd_clkstctrl, |
||||
&prcm->cm_dsp_clkstctrl, |
||||
&prcm->cm_dss_clkstctrl, |
||||
&prcm->cm_sgx_clkstctrl, |
||||
&prcm->cm1_abe_clkstctrl, |
||||
&prcm->cm_c2c_clkstctrl, |
||||
&prcm->cm_cam_clkstctrl, |
||||
&prcm->cm_dss_clkstctrl, |
||||
&prcm->cm_sdma_clkstctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_hw_auto_non_essential[] = { |
||||
&prcm->cm_mpu_m3_mpu_m3_clkctrl, |
||||
&prcm->cm_ivahd_ivahd_clkctrl, |
||||
&prcm->cm_ivahd_sl2_clkctrl, |
||||
&prcm->cm_dsp_dsp_clkctrl, |
||||
&prcm->cm_l3_2_gpmc_clkctrl, |
||||
&prcm->cm_l3instr_l3_3_clkctrl, |
||||
&prcm->cm_l3instr_l3_instr_clkctrl, |
||||
&prcm->cm_l3instr_intrconn_wp1_clkctrl, |
||||
&prcm->cm_l3init_hsi_clkctrl, |
||||
&prcm->cm_l3init_hsusbtll_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
u32 *const clk_modules_explicit_en_non_essential[] = { |
||||
&prcm->cm1_abe_aess_clkctrl, |
||||
&prcm->cm1_abe_pdm_clkctrl, |
||||
&prcm->cm1_abe_dmic_clkctrl, |
||||
&prcm->cm1_abe_mcasp_clkctrl, |
||||
&prcm->cm1_abe_mcbsp1_clkctrl, |
||||
&prcm->cm1_abe_mcbsp2_clkctrl, |
||||
&prcm->cm1_abe_mcbsp3_clkctrl, |
||||
&prcm->cm1_abe_slimbus_clkctrl, |
||||
&prcm->cm1_abe_timer5_clkctrl, |
||||
&prcm->cm1_abe_timer6_clkctrl, |
||||
&prcm->cm1_abe_timer7_clkctrl, |
||||
&prcm->cm1_abe_timer8_clkctrl, |
||||
&prcm->cm1_abe_wdt3_clkctrl, |
||||
&prcm->cm_l4per_gptimer9_clkctrl, |
||||
&prcm->cm_l4per_gptimer10_clkctrl, |
||||
&prcm->cm_l4per_gptimer11_clkctrl, |
||||
&prcm->cm_l4per_gptimer3_clkctrl, |
||||
&prcm->cm_l4per_gptimer4_clkctrl, |
||||
&prcm->cm_l4per_hdq1w_clkctrl, |
||||
&prcm->cm_l4per_mcbsp4_clkctrl, |
||||
&prcm->cm_l4per_mcspi2_clkctrl, |
||||
&prcm->cm_l4per_mcspi3_clkctrl, |
||||
&prcm->cm_l4per_mcspi4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd3_clkctrl, |
||||
&prcm->cm_l4per_mmcsd4_clkctrl, |
||||
&prcm->cm_l4per_mmcsd5_clkctrl, |
||||
&prcm->cm_l4per_uart1_clkctrl, |
||||
&prcm->cm_l4per_uart2_clkctrl, |
||||
&prcm->cm_l4per_uart4_clkctrl, |
||||
&prcm->cm_wkup_keyboard_clkctrl, |
||||
&prcm->cm_wkup_wdtimer2_clkctrl, |
||||
&prcm->cm_cam_iss_clkctrl, |
||||
&prcm->cm_cam_fdif_clkctrl, |
||||
&prcm->cm_dss_dss_clkctrl, |
||||
&prcm->cm_sgx_sgx_clkctrl, |
||||
&prcm->cm_l3init_hsusbhost_clkctrl, |
||||
&prcm->cm_l3init_fsusb_clkctrl, |
||||
0 |
||||
}; |
||||
|
||||
/* Enable optional functional clock for ISS */ |
||||
setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
/* Enable all optional functional clocks of DSS */ |
||||
setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); |
||||
|
||||
|
||||
/* Put the clock domains in SW_WKUP mode */ |
||||
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { |
||||
enable_clock_domain(clk_domains_non_essential[i], |
||||
CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
||||
} |
||||
|
||||
/* Clock modules that need to be put in HW_AUTO */ |
||||
for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { |
||||
enable_clock_module(clk_modules_hw_auto_non_essential[i], |
||||
MODULE_CLKCTRL_MODULEMODE_HW_AUTO, |
||||
wait_for_enable); |
||||
}; |
||||
|
||||
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */ |
||||
for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; |
||||
i++) { |
||||
enable_clock_module(clk_modules_explicit_en_non_essential[i], |
||||
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, |
||||
wait_for_enable); |
||||
}; |
||||
|
||||
/* Put the clock domains in HW_AUTO mode now */ |
||||
for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { |
||||
enable_clock_domain(clk_domains_non_essential[i], |
||||
CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
||||
} |
||||
|
||||
/* Put camera module in no sleep mode */ |
||||
clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, |
||||
CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << |
||||
MODULE_CLKCTRL_MODULEMODE_SHIFT); |
||||
} |
||||
|
||||
|
||||
void freq_update_core(void) |
||||
{ |
||||
u32 freq_config1 = 0; |
||||
const struct dpll_params *core_dpll_params; |
||||
|
||||
core_dpll_params = get_core_dpll_params(); |
||||
/* Put EMIF clock domain in sw wakeup mode */ |
||||
enable_clock_domain(&prcm->cm_memif_clkstctrl, |
||||
CD_CLKCTRL_CLKTRCTRL_SW_WKUP); |
||||
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); |
||||
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); |
||||
|
||||
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | |
||||
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; |
||||
|
||||
freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & |
||||
SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; |
||||
|
||||
freq_config1 |= (core_dpll_params->m2 << |
||||
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & |
||||
SHADOW_FREQ_CONFIG1_M2_DIV_MASK; |
||||
|
||||
writel(freq_config1, &prcm->cm_shadow_freq_config1); |
||||
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, |
||||
&prcm->cm_shadow_freq_config1, LDELAY)) { |
||||
puts("FREQ UPDATE procedure failed!!"); |
||||
hang(); |
||||
} |
||||
|
||||
/* Put EMIF clock domain back in hw auto mode */ |
||||
enable_clock_domain(&prcm->cm_memif_clkstctrl, |
||||
CD_CLKCTRL_CLKTRCTRL_HW_AUTO); |
||||
wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); |
||||
wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); |
||||
} |
||||
|
||||
void bypass_dpll(u32 *const base) |
||||
{ |
||||
do_bypass_dpll(base); |
||||
wait_for_bypass(base); |
||||
} |
||||
|
||||
void lock_dpll(u32 *const base) |
||||
{ |
||||
do_lock_dpll(base); |
||||
wait_for_lock(base); |
||||
} |
||||
|
||||
void prcm_init(void) |
||||
{ |
||||
switch (omap4_hw_init_context()) { |
||||
case OMAP_INIT_CONTEXT_SPL: |
||||
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
||||
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
||||
scale_vcores(); |
||||
setup_dplls(); |
||||
enable_basic_clocks(); |
||||
setup_non_essential_dplls(); |
||||
enable_non_essential_clocks(); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
@ -0,0 +1,664 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Aneesh V <aneesh@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef _CLOCKS_OMAP4_H_ |
||||
#define _CLOCKS_OMAP4_H_ |
||||
#include <common.h> |
||||
|
||||
/*
|
||||
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per |
||||
* loop, allow for a minimum of 2 ms wait (in reality the wait will be |
||||
* much more than that) |
||||
*/ |
||||
#define LDELAY 1000000 |
||||
|
||||
#define CM_CLKMODE_DPLL_CORE (OMAP44XX_L4_CORE_BASE + 0x4120) |
||||
#define CM_CLKMODE_DPLL_PER (OMAP44XX_L4_CORE_BASE + 0x8140) |
||||
#define CM_CLKMODE_DPLL_MPU (OMAP44XX_L4_CORE_BASE + 0x4160) |
||||
#define CM_CLKSEL_CORE (OMAP44XX_L4_CORE_BASE + 0x4100) |
||||
|
||||
struct omap4_prcm_regs { |
||||
/* cm1.ckgen */ |
||||
u32 cm_clksel_core; |
||||
u32 pad001[1]; |
||||
u32 cm_clksel_abe; |
||||
u32 pad002[1]; |
||||
u32 cm_dll_ctrl; |
||||
u32 pad003[3]; |
||||
u32 cm_clkmode_dpll_core; |
||||
u32 cm_idlest_dpll_core; |
||||
u32 cm_autoidle_dpll_core; |
||||
u32 cm_clksel_dpll_core; |
||||
u32 cm_div_m2_dpll_core; |
||||
u32 cm_div_m3_dpll_core; |
||||
u32 cm_div_m4_dpll_core; |
||||
u32 cm_div_m5_dpll_core; |
||||
u32 cm_div_m6_dpll_core; |
||||
u32 cm_div_m7_dpll_core; |
||||
u32 cm_ssc_deltamstep_dpll_core; |
||||
u32 cm_ssc_modfreqdiv_dpll_core; |
||||
u32 cm_emu_override_dpll_core; |
||||
u32 pad004[3]; |
||||
u32 cm_clkmode_dpll_mpu; |
||||
u32 cm_idlest_dpll_mpu; |
||||
u32 cm_autoidle_dpll_mpu; |
||||
u32 cm_clksel_dpll_mpu; |
||||
u32 cm_div_m2_dpll_mpu; |
||||
u32 pad005[5]; |
||||
u32 cm_ssc_deltamstep_dpll_mpu; |
||||
u32 cm_ssc_modfreqdiv_dpll_mpu; |
||||
u32 pad006[3]; |
||||
u32 cm_bypclk_dpll_mpu; |
||||
u32 cm_clkmode_dpll_iva; |
||||
u32 cm_idlest_dpll_iva; |
||||
u32 cm_autoidle_dpll_iva; |
||||
u32 cm_clksel_dpll_iva; |
||||
u32 pad007[2]; |
||||
u32 cm_div_m4_dpll_iva; |
||||
u32 cm_div_m5_dpll_iva; |
||||
u32 pad008[2]; |
||||
u32 cm_ssc_deltamstep_dpll_iva; |
||||
u32 cm_ssc_modfreqdiv_dpll_iva; |
||||
u32 pad009[3]; |
||||
u32 cm_bypclk_dpll_iva; |
||||
u32 cm_clkmode_dpll_abe; |
||||
u32 cm_idlest_dpll_abe; |
||||
u32 cm_autoidle_dpll_abe; |
||||
u32 cm_clksel_dpll_abe; |
||||
u32 cm_div_m2_dpll_abe; |
||||
u32 cm_div_m3_dpll_abe; |
||||
u32 pad010[4]; |
||||
u32 cm_ssc_deltamstep_dpll_abe; |
||||
u32 cm_ssc_modfreqdiv_dpll_abe; |
||||
u32 pad011[4]; |
||||
u32 cm_clkmode_dpll_ddrphy; |
||||
u32 cm_idlest_dpll_ddrphy; |
||||
u32 cm_autoidle_dpll_ddrphy; |
||||
u32 cm_clksel_dpll_ddrphy; |
||||
u32 cm_div_m2_dpll_ddrphy; |
||||
u32 pad012[1]; |
||||
u32 cm_div_m4_dpll_ddrphy; |
||||
u32 cm_div_m5_dpll_ddrphy; |
||||
u32 cm_div_m6_dpll_ddrphy; |
||||
u32 pad013[1]; |
||||
u32 cm_ssc_deltamstep_dpll_ddrphy; |
||||
u32 pad014[5]; |
||||
u32 cm_shadow_freq_config1; |
||||
|
||||
/* cm1.dsp */ |
||||
u32 pad015[103]; |
||||
u32 cm_dsp_clkstctrl; |
||||
u32 pad016[7]; |
||||
u32 cm_dsp_dsp_clkctrl; |
||||
|
||||
/* cm1.abe */ |
||||
u32 pad017[55]; |
||||
u32 cm1_abe_clkstctrl; |
||||
u32 pad018[7]; |
||||
u32 cm1_abe_l4abe_clkctrl; |
||||
u32 pad019[1]; |
||||
u32 cm1_abe_aess_clkctrl; |
||||
u32 pad020[1]; |
||||
u32 cm1_abe_pdm_clkctrl; |
||||
u32 pad021[1]; |
||||
u32 cm1_abe_dmic_clkctrl; |
||||
u32 pad022[1]; |
||||
u32 cm1_abe_mcasp_clkctrl; |
||||
u32 pad023[1]; |
||||
u32 cm1_abe_mcbsp1_clkctrl; |
||||
u32 pad024[1]; |
||||
u32 cm1_abe_mcbsp2_clkctrl; |
||||
u32 pad025[1]; |
||||
u32 cm1_abe_mcbsp3_clkctrl; |
||||
u32 pad026[1]; |
||||
u32 cm1_abe_slimbus_clkctrl; |
||||
u32 pad027[1]; |
||||
u32 cm1_abe_timer5_clkctrl; |
||||
u32 pad028[1]; |
||||
u32 cm1_abe_timer6_clkctrl; |
||||
u32 pad029[1]; |
||||
u32 cm1_abe_timer7_clkctrl; |
||||
u32 pad030[1]; |
||||
u32 cm1_abe_timer8_clkctrl; |
||||
u32 pad031[1]; |
||||
u32 cm1_abe_wdt3_clkctrl; |
||||
|
||||
/* cm2.ckgen */ |
||||
u32 pad032[3805]; |
||||
u32 cm_clksel_mpu_m3_iss_root; |
||||
u32 cm_clksel_usb_60mhz; |
||||
u32 cm_scale_fclk; |
||||
u32 pad033[1]; |
||||
u32 cm_core_dvfs_perf1; |
||||
u32 cm_core_dvfs_perf2; |
||||
u32 cm_core_dvfs_perf3; |
||||
u32 cm_core_dvfs_perf4; |
||||
u32 pad034[1]; |
||||
u32 cm_core_dvfs_current; |
||||
u32 cm_iva_dvfs_perf_tesla; |
||||
u32 cm_iva_dvfs_perf_ivahd; |
||||
u32 cm_iva_dvfs_perf_abe; |
||||
u32 pad035[1]; |
||||
u32 cm_iva_dvfs_current; |
||||
u32 pad036[1]; |
||||
u32 cm_clkmode_dpll_per; |
||||
u32 cm_idlest_dpll_per; |
||||
u32 cm_autoidle_dpll_per; |
||||
u32 cm_clksel_dpll_per; |
||||
u32 cm_div_m2_dpll_per; |
||||
u32 cm_div_m3_dpll_per; |
||||
u32 cm_div_m4_dpll_per; |
||||
u32 cm_div_m5_dpll_per; |
||||
u32 cm_div_m6_dpll_per; |
||||
u32 cm_div_m7_dpll_per; |
||||
u32 cm_ssc_deltamstep_dpll_per; |
||||
u32 cm_ssc_modfreqdiv_dpll_per; |
||||
u32 cm_emu_override_dpll_per; |
||||
u32 pad037[3]; |
||||
u32 cm_clkmode_dpll_usb; |
||||
u32 cm_idlest_dpll_usb; |
||||
u32 cm_autoidle_dpll_usb; |
||||
u32 cm_clksel_dpll_usb; |
||||
u32 cm_div_m2_dpll_usb; |
||||
u32 pad038[5]; |
||||
u32 cm_ssc_deltamstep_dpll_usb; |
||||
u32 cm_ssc_modfreqdiv_dpll_usb; |
||||
u32 pad039[1]; |
||||
u32 cm_clkdcoldo_dpll_usb; |
||||
u32 pad040[2]; |
||||
u32 cm_clkmode_dpll_unipro; |
||||
u32 cm_idlest_dpll_unipro; |
||||
u32 cm_autoidle_dpll_unipro; |
||||
u32 cm_clksel_dpll_unipro; |
||||
u32 cm_div_m2_dpll_unipro; |
||||
u32 pad041[5]; |
||||
u32 cm_ssc_deltamstep_dpll_unipro; |
||||
u32 cm_ssc_modfreqdiv_dpll_unipro; |
||||
|
||||
/* cm2.core */ |
||||
u32 pad0411[324]; |
||||
u32 cm_l3_1_clkstctrl; |
||||
u32 pad042[1]; |
||||
u32 cm_l3_1_dynamicdep; |
||||
u32 pad043[5]; |
||||
u32 cm_l3_1_l3_1_clkctrl; |
||||
u32 pad044[55]; |
||||
u32 cm_l3_2_clkstctrl; |
||||
u32 pad045[1]; |
||||
u32 cm_l3_2_dynamicdep; |
||||
u32 pad046[5]; |
||||
u32 cm_l3_2_l3_2_clkctrl; |
||||
u32 pad047[1]; |
||||
u32 cm_l3_2_gpmc_clkctrl; |
||||
u32 pad048[1]; |
||||
u32 cm_l3_2_ocmc_ram_clkctrl; |
||||
u32 pad049[51]; |
||||
u32 cm_mpu_m3_clkstctrl; |
||||
u32 cm_mpu_m3_staticdep; |
||||
u32 cm_mpu_m3_dynamicdep; |
||||
u32 pad050[5]; |
||||
u32 cm_mpu_m3_mpu_m3_clkctrl; |
||||
u32 pad051[55]; |
||||
u32 cm_sdma_clkstctrl; |
||||
u32 cm_sdma_staticdep; |
||||
u32 cm_sdma_dynamicdep; |
||||
u32 pad052[5]; |
||||
u32 cm_sdma_sdma_clkctrl; |
||||
u32 pad053[55]; |
||||
u32 cm_memif_clkstctrl; |
||||
u32 pad054[7]; |
||||
u32 cm_memif_dmm_clkctrl; |
||||
u32 pad055[1]; |
||||
u32 cm_memif_emif_fw_clkctrl; |
||||
u32 pad056[1]; |
||||
u32 cm_memif_emif_1_clkctrl; |
||||
u32 pad057[1]; |
||||
u32 cm_memif_emif_2_clkctrl; |
||||
u32 pad058[1]; |
||||
u32 cm_memif_dll_clkctrl; |
||||
u32 pad059[3]; |
||||
u32 cm_memif_emif_h1_clkctrl; |
||||
u32 pad060[1]; |
||||
u32 cm_memif_emif_h2_clkctrl; |
||||
u32 pad061[1]; |
||||
u32 cm_memif_dll_h_clkctrl; |
||||
u32 pad062[39]; |
||||
u32 cm_c2c_clkstctrl; |
||||
u32 cm_c2c_staticdep; |
||||
u32 cm_c2c_dynamicdep; |
||||
u32 pad063[5]; |
||||
u32 cm_c2c_sad2d_clkctrl; |
||||
u32 pad064[1]; |
||||
u32 cm_c2c_modem_icr_clkctrl; |
||||
u32 pad065[1]; |
||||
u32 cm_c2c_sad2d_fw_clkctrl; |
||||
u32 pad066[51]; |
||||
u32 cm_l4cfg_clkstctrl; |
||||
u32 pad067[1]; |
||||
u32 cm_l4cfg_dynamicdep; |
||||
u32 pad068[5]; |
||||
u32 cm_l4cfg_l4_cfg_clkctrl; |
||||
u32 pad069[1]; |
||||
u32 cm_l4cfg_hw_sem_clkctrl; |
||||
u32 pad070[1]; |
||||
u32 cm_l4cfg_mailbox_clkctrl; |
||||
u32 pad071[1]; |
||||
u32 cm_l4cfg_sar_rom_clkctrl; |
||||
u32 pad072[49]; |
||||
u32 cm_l3instr_clkstctrl; |
||||
u32 pad073[7]; |
||||
u32 cm_l3instr_l3_3_clkctrl; |
||||
u32 pad074[1]; |
||||
u32 cm_l3instr_l3_instr_clkctrl; |
||||
u32 pad075[5]; |
||||
u32 cm_l3instr_intrconn_wp1_clkctrl; |
||||
|
||||
|
||||
/* cm2.ivahd */ |
||||
u32 pad076[47]; |
||||
u32 cm_ivahd_clkstctrl; |
||||
u32 pad077[7]; |
||||
u32 cm_ivahd_ivahd_clkctrl; |
||||
u32 pad078[1]; |
||||
u32 cm_ivahd_sl2_clkctrl; |
||||
|
||||
/* cm2.cam */ |
||||
u32 pad079[53]; |
||||
u32 cm_cam_clkstctrl; |
||||
u32 pad080[7]; |
||||
u32 cm_cam_iss_clkctrl; |
||||
u32 pad081[1]; |
||||
u32 cm_cam_fdif_clkctrl; |
||||
|
||||
/* cm2.dss */ |
||||
u32 pad082[53]; |
||||
u32 cm_dss_clkstctrl; |
||||
u32 pad083[7]; |
||||
u32 cm_dss_dss_clkctrl; |
||||
|
||||
/* cm2.sgx */ |
||||
u32 pad084[55]; |
||||
u32 cm_sgx_clkstctrl; |
||||
u32 pad085[7]; |
||||
u32 cm_sgx_sgx_clkctrl; |
||||
|
||||
/* cm2.l3init */ |
||||
u32 pad086[55]; |
||||
u32 cm_l3init_clkstctrl; |
||||
|
||||
/* cm2.l3init */ |
||||
u32 pad087[9]; |
||||
u32 cm_l3init_hsmmc1_clkctrl; |
||||
u32 pad088[1]; |
||||
u32 cm_l3init_hsmmc2_clkctrl; |
||||
u32 pad089[1]; |
||||
u32 cm_l3init_hsi_clkctrl; |
||||
u32 pad090[7]; |
||||
u32 cm_l3init_hsusbhost_clkctrl; |
||||
u32 pad091[1]; |
||||
u32 cm_l3init_hsusbotg_clkctrl; |
||||
u32 pad092[1]; |
||||
u32 cm_l3init_hsusbtll_clkctrl; |
||||
u32 pad093[3]; |
||||
u32 cm_l3init_p1500_clkctrl; |
||||
u32 pad094[21]; |
||||
u32 cm_l3init_fsusb_clkctrl; |
||||
u32 pad095[3]; |
||||
u32 cm_l3init_usbphy_clkctrl; |
||||
|
||||
/* cm2.l4per */ |
||||
u32 pad096[7]; |
||||
u32 cm_l4per_clkstctrl; |
||||
u32 pad097[1]; |
||||
u32 cm_l4per_dynamicdep; |
||||
u32 pad098[5]; |
||||
u32 cm_l4per_adc_clkctrl; |
||||
u32 pad100[1]; |
||||
u32 cm_l4per_gptimer10_clkctrl; |
||||
u32 pad101[1]; |
||||
u32 cm_l4per_gptimer11_clkctrl; |
||||
u32 pad102[1]; |
||||
u32 cm_l4per_gptimer2_clkctrl; |
||||
u32 pad103[1]; |
||||
u32 cm_l4per_gptimer3_clkctrl; |
||||
u32 pad104[1]; |
||||
u32 cm_l4per_gptimer4_clkctrl; |
||||
u32 pad105[1]; |
||||
u32 cm_l4per_gptimer9_clkctrl; |
||||
u32 pad106[1]; |
||||
u32 cm_l4per_elm_clkctrl; |
||||
u32 pad107[1]; |
||||
u32 cm_l4per_gpio2_clkctrl; |
||||
u32 pad108[1]; |
||||
u32 cm_l4per_gpio3_clkctrl; |
||||
u32 pad109[1]; |
||||
u32 cm_l4per_gpio4_clkctrl; |
||||
u32 pad110[1]; |
||||
u32 cm_l4per_gpio5_clkctrl; |
||||
u32 pad111[1]; |
||||
u32 cm_l4per_gpio6_clkctrl; |
||||
u32 pad112[1]; |
||||
u32 cm_l4per_hdq1w_clkctrl; |
||||
u32 pad113[1]; |
||||
u32 cm_l4per_hecc1_clkctrl; |
||||
u32 pad114[1]; |
||||
u32 cm_l4per_hecc2_clkctrl; |
||||
u32 pad115[1]; |
||||
u32 cm_l4per_i2c1_clkctrl; |
||||
u32 pad116[1]; |
||||
u32 cm_l4per_i2c2_clkctrl; |
||||
u32 pad117[1]; |
||||
u32 cm_l4per_i2c3_clkctrl; |
||||
u32 pad118[1]; |
||||
u32 cm_l4per_i2c4_clkctrl; |
||||
u32 pad119[1]; |
||||
u32 cm_l4per_l4per_clkctrl; |
||||
u32 pad1191[3]; |
||||
u32 cm_l4per_mcasp2_clkctrl; |
||||
u32 pad120[1]; |
||||
u32 cm_l4per_mcasp3_clkctrl; |
||||
u32 pad121[1]; |
||||
u32 cm_l4per_mcbsp4_clkctrl; |
||||
u32 pad122[1]; |
||||
u32 cm_l4per_mgate_clkctrl; |
||||
u32 pad123[1]; |
||||
u32 cm_l4per_mcspi1_clkctrl; |
||||
u32 pad124[1]; |
||||
u32 cm_l4per_mcspi2_clkctrl; |
||||
u32 pad125[1]; |
||||
u32 cm_l4per_mcspi3_clkctrl; |
||||
u32 pad126[1]; |
||||
u32 cm_l4per_mcspi4_clkctrl; |
||||
u32 pad127[5]; |
||||
u32 cm_l4per_mmcsd3_clkctrl; |
||||
u32 pad128[1]; |
||||
u32 cm_l4per_mmcsd4_clkctrl; |
||||
u32 pad129[1]; |
||||
u32 cm_l4per_msprohg_clkctrl; |
||||
u32 pad130[1]; |
||||
u32 cm_l4per_slimbus2_clkctrl; |
||||
u32 pad131[1]; |
||||
u32 cm_l4per_uart1_clkctrl; |
||||
u32 pad132[1]; |
||||
u32 cm_l4per_uart2_clkctrl; |
||||
u32 pad133[1]; |
||||
u32 cm_l4per_uart3_clkctrl; |
||||
u32 pad134[1]; |
||||
u32 cm_l4per_uart4_clkctrl; |
||||
u32 pad135[1]; |
||||
u32 cm_l4per_mmcsd5_clkctrl; |
||||
u32 pad136[1]; |
||||
u32 cm_l4per_i2c5_clkctrl; |
||||
u32 pad137[5]; |
||||
u32 cm_l4sec_clkstctrl; |
||||
u32 cm_l4sec_staticdep; |
||||
u32 cm_l4sec_dynamicdep; |
||||
u32 pad138[5]; |
||||
u32 cm_l4sec_aes1_clkctrl; |
||||
u32 pad139[1]; |
||||
u32 cm_l4sec_aes2_clkctrl; |
||||
u32 pad140[1]; |
||||
u32 cm_l4sec_des3des_clkctrl; |
||||
u32 pad141[1]; |
||||
u32 cm_l4sec_pkaeip29_clkctrl; |
||||
u32 pad142[1]; |
||||
u32 cm_l4sec_rng_clkctrl; |
||||
u32 pad143[1]; |
||||
u32 cm_l4sec_sha2md51_clkctrl; |
||||
u32 pad144[3]; |
||||
u32 cm_l4sec_cryptodma_clkctrl; |
||||
u32 pad145[776841]; |
||||
|
||||
/* l4 wkup regs */ |
||||
u32 pad201[6211]; |
||||
u32 cm_abe_pll_ref_clksel; |
||||
u32 cm_sys_clksel; |
||||
u32 pad202[1467]; |
||||
u32 cm_wkup_clkstctrl; |
||||
u32 pad203[7]; |
||||
u32 cm_wkup_l4wkup_clkctrl; |
||||
u32 pad204; |
||||
u32 cm_wkup_wdtimer1_clkctrl; |
||||
u32 pad205; |
||||
u32 cm_wkup_wdtimer2_clkctrl; |
||||
u32 pad206; |
||||
u32 cm_wkup_gpio1_clkctrl; |
||||
u32 pad207; |
||||
u32 cm_wkup_gptimer1_clkctrl; |
||||
u32 pad208; |
||||
u32 cm_wkup_gptimer12_clkctrl; |
||||
u32 pad209; |
||||
u32 cm_wkup_synctimer_clkctrl; |
||||
u32 pad210; |
||||
u32 cm_wkup_usim_clkctrl; |
||||
u32 pad211; |
||||
u32 cm_wkup_sarram_clkctrl; |
||||
u32 pad212[5]; |
||||
u32 cm_wkup_keyboard_clkctrl; |
||||
u32 pad213; |
||||
u32 cm_wkup_rtc_clkctrl; |
||||
u32 pad214; |
||||
u32 cm_wkup_bandgap_clkctrl; |
||||
u32 pad215[197]; |
||||
u32 prm_vc_val_bypass; |
||||
u32 prm_vc_cfg_channel; |
||||
u32 prm_vc_cfg_i2c_mode; |
||||
u32 prm_vc_cfg_i2c_clk; |
||||
|
||||
}; |
||||
|
||||
/* DPLL register offsets */ |
||||
#define CM_CLKMODE_DPLL 0 |
||||
#define CM_IDLEST_DPLL 0x4 |
||||
#define CM_AUTOIDLE_DPLL 0x8 |
||||
#define CM_CLKSEL_DPLL 0xC |
||||
#define CM_DIV_M2_DPLL 0x10 |
||||
#define CM_DIV_M3_DPLL 0x14 |
||||
#define CM_DIV_M4_DPLL 0x18 |
||||
#define CM_DIV_M5_DPLL 0x1C |
||||
#define CM_DIV_M6_DPLL 0x20 |
||||
#define CM_DIV_M7_DPLL 0x24 |
||||
|
||||
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ |
||||
|
||||
/* CM_CLKMODE_DPLL */ |
||||
#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 |
||||
#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) |
||||
#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 |
||||
#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) |
||||
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 |
||||
#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) |
||||
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 |
||||
#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
||||
#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 |
||||
#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) |
||||
#define CM_CLKMODE_DPLL_EN_SHIFT 0 |
||||
#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) |
||||
|
||||
#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 |
||||
#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 |
||||
|
||||
#define DPLL_EN_STOP 1 |
||||
#define DPLL_EN_MN_BYPASS 4 |
||||
#define DPLL_EN_LOW_POWER_BYPASS 5 |
||||
#define DPLL_EN_FAST_RELOCK_BYPASS 6 |
||||
#define DPLL_EN_LOCK 7 |
||||
|
||||
/* CM_IDLEST_DPLL fields */ |
||||
#define ST_DPLL_CLK_MASK 1 |
||||
|
||||
/* CM_CLKSEL_DPLL */ |
||||
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 |
||||
#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) |
||||
#define CM_CLKSEL_DPLL_M_SHIFT 8 |
||||
#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) |
||||
#define CM_CLKSEL_DPLL_N_SHIFT 0 |
||||
#define CM_CLKSEL_DPLL_N_MASK 0x7F |
||||
|
||||
#define OMAP4_DPLL_MAX_N 127 |
||||
|
||||
/* CM_SYS_CLKSEL */ |
||||
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 |
||||
|
||||
/* CM_CLKSEL_CORE */ |
||||
#define CLKSEL_CORE_SHIFT 0 |
||||
#define CLKSEL_L3_SHIFT 4 |
||||
#define CLKSEL_L4_SHIFT 8 |
||||
|
||||
#define CLKSEL_CORE_X2_DIV_1 0 |
||||
#define CLKSEL_L3_CORE_DIV_2 1 |
||||
#define CLKSEL_L4_L3_DIV_2 1 |
||||
|
||||
/* CM_ABE_PLL_REF_CLKSEL */ |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 |
||||
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 |
||||
|
||||
/* CM_BYPCLK_DPLL_IVA */ |
||||
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 |
||||
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 |
||||
|
||||
#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 |
||||
|
||||
/* CM_SHADOW_FREQ_CONFIG1 */ |
||||
#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 |
||||
#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 |
||||
#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 |
||||
|
||||
#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 |
||||
#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) |
||||
|
||||
#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 |
||||
#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) |
||||
|
||||
/*CM_<clock_domain>__CLKCTRL */ |
||||
#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 |
||||
#define CD_CLKCTRL_CLKTRCTRL_MASK 3 |
||||
|
||||
#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 |
||||
#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 |
||||
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 |
||||
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 |
||||
|
||||
|
||||
/* CM_<clock_domain>_<module>_CLKCTRL */ |
||||
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 |
||||
#define MODULE_CLKCTRL_MODULEMODE_MASK 3 |
||||
#define MODULE_CLKCTRL_IDLEST_SHIFT 16 |
||||
#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) |
||||
|
||||
#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 |
||||
#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 |
||||
#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 |
||||
|
||||
#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 |
||||
#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 |
||||
#define MODULE_CLKCTRL_IDLEST_IDLE 2 |
||||
#define MODULE_CLKCTRL_IDLEST_DISABLED 3 |
||||
|
||||
/* CM_L4PER_GPIO4_CLKCTRL */ |
||||
#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) |
||||
|
||||
/* CM_L3INIT_HSMMCn_CLKCTRL */ |
||||
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) |
||||
|
||||
/* CM_WKUP_GPTIMER1_CLKCTRL */ |
||||
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) |
||||
|
||||
/* CM_CAM_ISS_CLKCTRL */ |
||||
#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) |
||||
|
||||
/* CM_DSS_DSS_CLKCTRL */ |
||||
#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 |
||||
|
||||
/* CM_L3INIT_USBPHY_CLKCTRL */ |
||||
#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 |
||||
|
||||
/* Clock frequencies */ |
||||
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 |
||||
#define OMAP_SYS_CLK_IND_38_4_MHZ 6 |
||||
#define OMAP_32K_CLK_FREQ 32768 |
||||
|
||||
/* PRM_VC_CFG_I2C_CLK */ |
||||
#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 |
||||
#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF |
||||
#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 |
||||
#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) |
||||
|
||||
/* PRM_VC_VAL_BYPASS */ |
||||
#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 |
||||
|
||||
#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 |
||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 |
||||
#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F |
||||
#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 |
||||
#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF |
||||
#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 |
||||
#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF |
||||
|
||||
#define SMPS_I2C_SLAVE_ADDR 0x12 |
||||
#define SMPS_REG_ADDR_VCORE1 0x55 |
||||
#define SMPS_REG_ADDR_VCORE2 0x5B |
||||
#define SMPS_REG_ADDR_VCORE3 0x61 |
||||
|
||||
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 |
||||
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 |
||||
|
||||
/* Defines for DPLL setup */ |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 |
||||
#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 |
||||
|
||||
#define DPLL_NO_LOCK 0 |
||||
#define DPLL_LOCK 1 |
||||
|
||||
#define NUM_SYS_CLKS 7 |
||||
|
||||
struct dpll_regs { |
||||
u32 cm_clkmode_dpll; |
||||
u32 cm_idlest_dpll; |
||||
u32 cm_autoidle_dpll; |
||||
u32 cm_clksel_dpll; |
||||
u32 cm_div_m2_dpll; |
||||
u32 cm_div_m3_dpll; |
||||
u32 cm_div_m4_dpll; |
||||
u32 cm_div_m5_dpll; |
||||
u32 cm_div_m6_dpll; |
||||
u32 cm_div_m7_dpll; |
||||
}; |
||||
|
||||
/* DPLL parameter table */ |
||||
struct dpll_params { |
||||
u32 m; |
||||
u32 n; |
||||
u8 m2; |
||||
u8 m3; |
||||
u8 m4; |
||||
u8 m5; |
||||
u8 m6; |
||||
u8 m7; |
||||
}; |
||||
|
||||
#endif /* _CLOCKS_OMAP4_H_ */ |
@ -0,0 +1,197 @@ |
||||
/*
|
||||
* Program for finding M & N values for DPLLs |
||||
* To be run on Host PC |
||||
* |
||||
* (C) Copyright 2010 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* Aneesh V <aneesh@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <stdlib.h> |
||||
#include <stdio.h> |
||||
typedef unsigned int u32; |
||||
#define MAX_N 127 |
||||
|
||||
/*
|
||||
* get_m_n_optimized() - Finds optimal DPLL multiplier(M) and divider(N) |
||||
* values based on the reference frequency, required output frequency, |
||||
* maximum tolerance for output frequency etc. |
||||
* |
||||
* target_freq_khz - output frequency required in KHz |
||||
* ref_freq_khz - reference(input) frequency in KHz |
||||
* m - pointer to computed M value |
||||
* n - pointer to computed N value |
||||
* tolerance_khz - tolerance for the output frequency. When the algorithm |
||||
* succeeds in finding vialble M and N values the corresponding output |
||||
* frequency will be in the range: |
||||
* [target_freq_khz - tolerance_khz, target_freq_khz] |
||||
* |
||||
* Formula: |
||||
* Fdpll = (2 * M * Fref) / (N + 1) |
||||
* |
||||
* Considerations for lock-time: |
||||
* - Smaller the N, better lock-time, especially lock-time will be |
||||
* - For acceptable lock-times: |
||||
* Fref / (M + 1) >= 1 MHz |
||||
* |
||||
* Considerations for power: |
||||
* - The difference in power for different N values giving the same |
||||
* output is negligible. So, we optimize for lock-time |
||||
* |
||||
* Hard-constraints: |
||||
* - N can not be greater than 127(7 bit field for representing N) |
||||
* |
||||
* Usage: |
||||
* $ gcc clocks_get_m_n.c |
||||
* $ ./a.out |
||||
*/ |
||||
int get_m_n_optimized(u32 target_freq_khz, u32 ref_freq_khz, u32 *m, u32 *n, |
||||
u32 tolerance_khz) |
||||
{ |
||||
u32 min_freq = target_freq_khz - tolerance_khz; |
||||
u32 max_freq = target_freq_khz; |
||||
u32 freq, freq_old; |
||||
*n = 1; |
||||
while (1) { |
||||
*m = min_freq / ref_freq_khz / 2 * (*n) ; |
||||
freq_old = 0; |
||||
while (1) { |
||||
freq = ref_freq_khz * 2 * (*m) / (*n); |
||||
if (abs(target_freq_khz - freq_old) <= |
||||
abs(target_freq_khz - freq)) { |
||||
freq = freq_old; |
||||
(*m)--; |
||||
break; |
||||
} |
||||
(*m)++; |
||||
freq_old = freq; |
||||
} |
||||
if (freq >= min_freq && freq <= max_freq) |
||||
break; |
||||
(*n)++; |
||||
if ((*n) > MAX_N + 1) { |
||||
printf("ref %d m %d n %d target %d : ", |
||||
ref_freq_khz, *m, *n, target_freq_khz); |
||||
printf("can not find m & n - please consider" |
||||
" increasing tolerance\n"); |
||||
return -1; |
||||
} |
||||
} |
||||
(*n)--; |
||||
printf("ref %d m %d n %d target %d locked %d\n", |
||||
ref_freq_khz, *m, *n, target_freq_khz, freq); |
||||
if ((ref_freq_khz / (*n + 1)) < 1000) { |
||||
printf("\tREFCLK - CLKINP/(N+1) is less than 1 MHz - less than" |
||||
" ideal, locking time will be high!\n"); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
void main(void) |
||||
{ |
||||
u32 m, n; |
||||
printf("\nMPU - 2000000\n"); |
||||
get_m_n_optimized(2000000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(2000000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(2000000, 16800, &m, &n, 800); |
||||
get_m_n_optimized(2000000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(2000000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(2000000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(2000000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nMPU - 1200000\n"); |
||||
get_m_n_optimized(1200000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1200000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1200000, 16800, &m, &n, 800); |
||||
get_m_n_optimized(1200000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1200000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1200000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1200000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nMPU - 1584000\n"); |
||||
get_m_n_optimized(1584000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1584000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1584000, 16800, &m, &n, 400); |
||||
get_m_n_optimized(1584000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1584000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1584000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1584000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nCore 1600000\n"); |
||||
get_m_n_optimized(1600000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1600000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1600000, 16800, &m, &n, 200); |
||||
get_m_n_optimized(1600000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1600000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1600000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1600000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nPER 1536000\n"); |
||||
get_m_n_optimized(1536000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 16800, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1536000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nIVA 1862000\n"); |
||||
get_m_n_optimized(1862000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1862000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1862000, 16800, &m, &n, 0); |
||||
get_m_n_optimized(1862000, 19200, &m, &n, 900); |
||||
get_m_n_optimized(1862000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1862000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1862000, 38400, &m, &n, 800); |
||||
|
||||
printf("\nABE 196608 sys clk\n"); |
||||
get_m_n_optimized(196608, 12000, &m, &n, 700); |
||||
get_m_n_optimized(196608, 13000, &m, &n, 200); |
||||
get_m_n_optimized(196608, 16800, &m, &n, 700); |
||||
get_m_n_optimized(196608, 19200, &m, &n, 400); |
||||
get_m_n_optimized(196608, 26000, &m, &n, 200); |
||||
get_m_n_optimized(196608, 27000, &m, &n, 900); |
||||
get_m_n_optimized(196608, 38400, &m, &n, 0); |
||||
|
||||
printf("\nABE 196608 32K\n"); |
||||
get_m_n_optimized(196608000/4, 32768, &m, &n, 0); |
||||
|
||||
printf("\nUSB 1920000\n"); |
||||
get_m_n_optimized(1920000, 12000, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 16800, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 27000, &m, &n, 0); |
||||
get_m_n_optimized(1920000, 38400, &m, &n, 0); |
||||
|
||||
printf("\nCore ES1 1523712\n"); |
||||
get_m_n_optimized(1524000, 12000, &m, &n, 100); |
||||
get_m_n_optimized(1524000, 13000, &m, &n, 0); |
||||
get_m_n_optimized(1524000, 16800, &m, &n, 0); |
||||
get_m_n_optimized(1524000, 19200, &m, &n, 0); |
||||
get_m_n_optimized(1524000, 26000, &m, &n, 0); |
||||
get_m_n_optimized(1524000, 27000, &m, &n, 0); |
||||
|
||||
/* exact recommendation for SDPs */ |
||||
get_m_n_optimized(1523712, 38400, &m, &n, 0); |
||||
|
||||
} |
Loading…
Reference in new issue