Wolfgang Denk
18 years ago
committed by
Wolfgang Denk
commit
37896293bc
@ -0,0 +1,50 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,28 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC832XEMDS
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#
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,176 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#include <command.h> |
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#if defined(CONFIG_PCI) |
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#include <pci.h> |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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#include <spd_sdram.h> |
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#else |
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#include <asm/mmu.h> |
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#endif |
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#if defined(CONFIG_OF_FLAT_TREE) |
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#include <ft_build.h> |
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#endif |
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const qe_iop_conf_t qe_iop_conf_tab[] = { |
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/* ETH3 */ |
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{1, 0, 1, 0, 1}, /* TxD0 */ |
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{1, 1, 1, 0, 1}, /* TxD1 */ |
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{1, 2, 1, 0, 1}, /* TxD2 */ |
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{1, 3, 1, 0, 1}, /* TxD3 */ |
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{1, 9, 1, 0, 1}, /* TxER */ |
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{1, 12, 1, 0, 1}, /* TxEN */ |
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ |
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{1, 4, 2, 0, 1}, /* RxD0 */ |
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{1, 5, 2, 0, 1}, /* RxD1 */ |
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{1, 6, 2, 0, 1}, /* RxD2 */ |
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{1, 7, 2, 0, 1}, /* RxD3 */ |
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{1, 8, 2, 0, 1}, /* RxER */ |
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{1, 10, 2, 0, 1}, /* RxDV */ |
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ |
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{1, 11, 2, 0, 1}, /* COL */ |
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{1, 13, 2, 0, 1}, /* CRS */ |
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/* ETH4 */ |
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{1, 18, 1, 0, 1}, /* TxD0 */ |
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{1, 19, 1, 0, 1}, /* TxD1 */ |
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{1, 20, 1, 0, 1}, /* TxD2 */ |
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{1, 21, 1, 0, 1}, /* TxD3 */ |
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{1, 27, 1, 0, 1}, /* TxER */ |
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{1, 30, 1, 0, 1}, /* TxEN */ |
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{3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ |
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{1, 22, 2, 0, 1}, /* RxD0 */ |
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{1, 23, 2, 0, 1}, /* RxD1 */ |
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{1, 24, 2, 0, 1}, /* RxD2 */ |
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{1, 25, 2, 0, 1}, /* RxD3 */ |
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{1, 26, 1, 0, 1}, /* RxER */ |
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{1, 28, 2, 0, 1}, /* Rx_DV */ |
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{3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ |
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{1, 29, 2, 0, 1}, /* COL */ |
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{1, 31, 2, 0, 1}, /* CRS */ |
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{3, 4, 3, 0, 2}, /* MDIO */ |
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{3, 5, 1, 0, 2}, /* MDC */ |
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ |
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}; |
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int board_early_init_f(void) |
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{ |
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volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; |
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/* Enable flash write */ |
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bcsr[9] &= ~0x08; |
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return 0; |
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} |
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int fixed_sdram(void); |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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msize = fixed_sdram(); |
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puts("\n DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CFG_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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#if (CFG_DDR_SIZE != 128) |
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#warning Currenly any ddr size other than 128 is not supported |
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#endif |
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; |
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; |
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; |
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_mode2 = CFG_DDR_MODE2; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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__asm__ __volatile__ ("sync"); |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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__asm__ __volatile__ ("sync"); |
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return msize; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Freescale MPC832XEMDS\n"); |
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return 0; |
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} |
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
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void |
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ft_board_setup(void *blob, bd_t *bd) |
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{ |
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u32 *p; |
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int len; |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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ft_cpu_setup(blob, bd); |
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p = ft_get_prop(blob, "/memory/reg", &len); |
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if (p != NULL) { |
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*p++ = cpu_to_be32(bd->bi_memstart); |
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*p = cpu_to_be32(bd->bi_memsize); |
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} |
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} |
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#endif |
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@ -0,0 +1,316 @@ |
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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/*
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* PCI Configuration space access support for MPC83xx PCI Bridge |
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*/ |
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#include <asm/mmu.h> |
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#include <asm/io.h> |
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#include <common.h> |
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#include <pci.h> |
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#include <i2c.h> |
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#if defined(CONFIG_OF_FLAT_TREE) |
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#include <ft_build.h> |
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#endif |
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#include <asm/fsl_i2c.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_PCI) |
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#define PCI_FUNCTION_CONFIG 0x44 |
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#define PCI_FUNCTION_CFG_LOCK 0x20 |
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/*
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* Initialize PCI Devices, report devices found |
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*/ |
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#ifndef CONFIG_PCI_PNP |
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static struct pci_config_table pci_mpc83xxemds_config_table[] = { |
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{ |
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
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pci_cfgfunc_config_device, |
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{PCI_ENET0_IOADDR, |
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PCI_ENET0_MEMADDR, |
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} |
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}, |
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{} |
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} |
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#endif |
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static struct pci_controller hose[] = { |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxemds_config_table, |
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#endif |
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}, |
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}; |
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/**********************************************************************
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* pci_init_board() |
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*********************************************************************/ |
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void pci_init_board(void) |
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#ifdef CONFIG_PCISLAVE |
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{ |
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u16 reg16; |
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volatile immap_t *immr; |
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volatile law83xx_t *pci_law; |
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volatile pot83xx_t *pci_pot; |
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volatile pcictrl83xx_t *pci_ctrl; |
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volatile pciconf83xx_t *pci_conf; |
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immr = (immap_t *) CFG_IMMR; |
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pci_law = immr->sysconf.pcilaw; |
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pci_pot = immr->ios.pot; |
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pci_ctrl = immr->pci_ctrl; |
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pci_conf = immr->pci_conf; |
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/*
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* Configure PCI Inbound Translation Windows |
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*/ |
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pci_ctrl[0].pitar0 = 0x0; |
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pci_ctrl[0].pibar0 = 0x0; |
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pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | |
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PIWAR_WTT_SNOOP | PIWAR_IWS_4K; |
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pci_ctrl[0].pitar1 = 0x0; |
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pci_ctrl[0].pibar1 = 0x0; |
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pci_ctrl[0].piebar1 = 0x0; |
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pci_ctrl[0].piwar1 &= ~PIWAR_EN; |
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pci_ctrl[0].pitar2 = 0x0; |
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pci_ctrl[0].pibar2 = 0x0; |
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pci_ctrl[0].piebar2 = 0x0; |
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pci_ctrl[0].piwar2 &= ~PIWAR_EN; |
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hose[0].first_busno = 0; |
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hose[0].last_busno = 0xff; |
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pci_setup_indirect(&hose[0], |
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(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
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reg16 = 0xff; |
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pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_COMMAND, ®16); |
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; |
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_COMMAND, reg16); |
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/*
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* Clear non-reserved bits in status register. |
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*/ |
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_STATUS, 0xffff); |
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pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_LATENCY_TIMER, 0x80); |
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/*
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* Unlock configuration lock in PCI function configuration register. |
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*/ |
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pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_FUNCTION_CONFIG, ®16); |
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reg16 &= ~(PCI_FUNCTION_CFG_LOCK); |
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pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), |
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PCI_FUNCTION_CONFIG, reg16); |
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printf("Enabled PCI 32bit Agent Mode\n"); |
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} |
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#else |
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{ |
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volatile immap_t *immr; |
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volatile clk83xx_t *clk; |
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volatile law83xx_t *pci_law; |
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volatile pot83xx_t *pci_pot; |
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volatile pcictrl83xx_t *pci_ctrl; |
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volatile pciconf83xx_t *pci_conf; |
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|
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u8 val8, orig_i2c_bus; |
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u16 reg16; |
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u32 val32; |
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u32 dev; |
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immr = (immap_t *) CFG_IMMR; |
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clk = (clk83xx_t *) & immr->clk; |
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pci_law = immr->sysconf.pcilaw; |
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pci_pot = immr->ios.pot; |
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pci_ctrl = immr->pci_ctrl; |
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pci_conf = immr->pci_conf; |
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/*
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* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
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*/ |
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val32 = clk->occr; |
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udelay(2000); |
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#if defined(PCI_66M) |
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
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printf("PCI clock is 66MHz\n"); |
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#elif defined(PCI_33M) |
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | |
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OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; |
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printf("PCI clock is 33MHz\n"); |
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#else |
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clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; |
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printf("PCI clock is 66MHz\n"); |
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#endif |
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udelay(2000); |
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|
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/*
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* Configure PCI Local Access Windows |
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*/ |
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pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; |
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pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; |
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|
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pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; |
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pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; |
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|
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/*
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* Configure PCI Outbound Translation Windows |
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*/ |
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|
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/* PCI mem space - prefetch */ |
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pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; |
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pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; |
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pci_pot[0].pocmr = |
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POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); |
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|
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/* PCI mmio - non-prefetch mem space */ |
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pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; |
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pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
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pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
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|
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/* PCI IO space */ |
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pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; |
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pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; |
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pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
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|
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/*
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* Configure PCI Inbound Translation Windows |
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*/ |
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pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; |
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pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; |
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pci_ctrl[0].piebar1 = 0x0; |
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pci_ctrl[0].piwar1 = |
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PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
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PIWAR_IWS_2G; |
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|
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/*
|
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* Assign PIB PMC slot to desired PCI bus |
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*/ |
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|
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/* Switch temporarily to I2C bus #2 */ |
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orig_i2c_bus = i2c_get_bus_num(); |
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i2c_set_bus_num(1); |
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|
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val8 = 0; |
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i2c_write(0x23, 0x6, 1, &val8, 1); |
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i2c_write(0x23, 0x7, 1, &val8, 1); |
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val8 = 0xff; |
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i2c_write(0x23, 0x2, 1, &val8, 1); |
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i2c_write(0x23, 0x3, 1, &val8, 1); |
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|
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val8 = 0; |
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i2c_write(0x26, 0x6, 1, &val8, 1); |
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val8 = 0x34; |
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i2c_write(0x26, 0x7, 1, &val8, 1); |
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|
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val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ |
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i2c_write(0x26, 0x2, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x26, 0x3, 1, &val8, 1); |
||||
|
||||
val8 = 0; |
||||
i2c_write(0x27, 0x6, 1, &val8, 1); |
||||
i2c_write(0x27, 0x7, 1, &val8, 1); |
||||
val8 = 0xff; |
||||
i2c_write(0x27, 0x2, 1, &val8, 1); |
||||
val8 = 0xef; |
||||
i2c_write(0x27, 0x3, 1, &val8, 1); |
||||
asm("eieio"); |
||||
|
||||
/* Reset to original I2C bus */ |
||||
i2c_set_bus_num(orig_i2c_bus); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
udelay(2000); |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose[0].regions + 0, |
||||
CFG_PCI_MEM_BASE, |
||||
CFG_PCI_MEM_PHYS, |
||||
CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose[0].regions + 1, |
||||
CFG_PCI_MMIO_BASE, |
||||
CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose[0].regions + 2, |
||||
CFG_PCI_IO_BASE, |
||||
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose[0].regions + 3, |
||||
CFG_PCI_SLV_MEM_LOCAL, |
||||
CFG_PCI_SLV_MEM_BUS, |
||||
CFG_PCI_SLV_MEM_SIZE, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose[0].region_count = 4; |
||||
|
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(0, 0, 0); |
||||
pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
printf("PCI 32bit bus on PMC2 & PMC3\n"); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
#endif /* CONFIG_PCISLAVE */ |
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void |
||||
ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = hose[0].first_busno; |
||||
p[1] = hose[0].last_busno; |
||||
} |
||||
} |
||||
#endif /* CONFIG_OF_FLAT_TREE */ |
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,123 @@ |
||||
/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,49 @@ |
||||
#
|
||||
# Copyright (c) 2006 Wind River Systems, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pci.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,27 @@ |
||||
#
|
||||
# Copyright (c) 2006 Wind River Systems, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# SBC8349E
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFF00000
|
||||
@ -0,0 +1,348 @@ |
||||
/*
|
||||
* pci.c -- WindRiver SBC8349 PCI board support. |
||||
* Copyright (c) 2006 Wind River Systems, Inc. |
||||
* |
||||
* Based on MPC8349 PCI support but w/o PIB related code. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <asm/mmu.h> |
||||
#include <common.h> |
||||
#include <asm/global_data.h> |
||||
#include <pci.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
#include <i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
/* System RAM mapped to PCI space */ |
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc8349emds_config_table[] = { |
||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
||||
} |
||||
}, |
||||
{} |
||||
}; |
||||
#endif |
||||
|
||||
static struct pci_controller pci_hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349emds_config_table, |
||||
#endif |
||||
}, |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349emds_config_table, |
||||
#endif |
||||
} |
||||
}; |
||||
|
||||
/**************************************************************************
|
||||
* pci_init_board() |
||||
* |
||||
* NOTICE: PCI2 is not supported. There is only one |
||||
* physical PCI slot on the board. |
||||
* |
||||
*/ |
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
volatile immap_t * immr; |
||||
volatile clk83xx_t * clk; |
||||
volatile law83xx_t * pci_law; |
||||
volatile pot83xx_t * pci_pot; |
||||
volatile pcictrl83xx_t * pci_ctrl; |
||||
volatile pciconf83xx_t * pci_conf; |
||||
u16 reg16; |
||||
u32 reg32; |
||||
u32 dev; |
||||
struct pci_controller * hose; |
||||
|
||||
immr = (immap_t *)CFG_IMMR; |
||||
clk = (clk83xx_t *)&immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
|
||||
hose = &pci_hose[0]; |
||||
|
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
|
||||
reg32 = clk->occr; |
||||
udelay(2000); |
||||
clk->occr = 0xff000000; |
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
pci_ctrl[0].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
pci_ctrl[1].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[1].gcr = 1; |
||||
#endif |
||||
|
||||
/* We need to wait at least a 1sec based on PCI specs */ |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < 1000; ++i) |
||||
udelay (1000); |
||||
} |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; |
||||
|
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI1 mem space - prefetch */ |
||||
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI1 IO space */ |
||||
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/* PCI1 mmio - non-prefetch mem space */ |
||||
pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM|PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_MMIO_BASE, |
||||
CFG_PCI1_MMIO_PHYS, |
||||
CFG_PCI1_MMIO_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMR+0x8300), |
||||
(CFG_IMMR+0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW |
||||
printf("PCI: Bus Dev VenId DevId Class Int\n"); |
||||
#endif |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
hose = &pci_hose[1]; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI2 mem space - prefetch */ |
||||
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI2 IO space */ |
||||
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/* PCI2 mmio - non-prefetch mem space */ |
||||
pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[1].pitar1 = 0x0; |
||||
pci_ctrl[1].pibar1 = 0x0; |
||||
pci_ctrl[1].piebar1 = 0x0; |
||||
pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = pci_hose[0].last_busno + 1; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI2_MEM_BASE, |
||||
CFG_PCI2_MEM_PHYS, |
||||
CFG_PCI2_MEM_SIZE, |
||||
PCI_REGION_MEM|PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI2_MMIO_BASE, |
||||
CFG_PCI2_MMIO_PHYS, |
||||
CFG_PCI2_MMIO_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI2_IO_BASE, |
||||
CFG_PCI2_IO_PHYS, |
||||
CFG_PCI2_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMR+0x8380), |
||||
(CFG_IMMR+0x8384)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
#endif |
||||
|
||||
} |
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void |
||||
ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = pci_hose[0].first_busno; |
||||
p[1] = pci_hose[0].last_busno; |
||||
} |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); |
||||
if (p != NULL) { |
||||
p[0] = pci_hose[1].first_busno; |
||||
p[1] = pci_hose[1].last_busno; |
||||
} |
||||
#endif |
||||
} |
||||
#endif /* CONFIG_OF_FLAT_TREE */ |
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,585 @@ |
||||
/*
|
||||
* sbc8349.c -- WindRiver SBC8349 board support. |
||||
* Copyright (c) 2006-2007 Wind River Systems, Inc. |
||||
* |
||||
* Paul Gortmaker <paul.gortmaker@windriver.com> |
||||
* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc83xx.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
#include <i2c.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
#include <command.h> |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
#include <spd_sdram.h> |
||||
#endif |
||||
#if defined(CONFIG_OF_FLAT_TREE) |
||||
#include <ft_build.h> |
||||
#endif |
||||
|
||||
int fixed_sdram(void); |
||||
void sdram_init(void); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) |
||||
void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F |
||||
int board_early_init_f (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
u32 msize = 0; |
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
||||
return -1; |
||||
|
||||
puts("Initializing\n"); |
||||
|
||||
/* DDR SDRAM - Main SODIMM */ |
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
msize = spd_sdram(); |
||||
#else |
||||
msize = fixed_sdram(); |
||||
#endif |
||||
/*
|
||||
* Initialize SDRAM if it is on local bus. |
||||
*/ |
||||
sdram_init(); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize and enable DDR ECC. |
||||
*/ |
||||
ddr_enable_ecc(msize * 1024 * 1024); |
||||
#endif |
||||
puts(" DDR RAM: "); |
||||
/* return total bus SDRAM size(bytes) -- DDR */ |
||||
return (msize * 1024 * 1024); |
||||
} |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
int fixed_sdram(void) |
||||
{ |
||||
volatile immap_t *im = (immap_t *)CFG_IMMR; |
||||
u32 msize = 0; |
||||
u32 ddr_size; |
||||
u32 ddr_size_log2; |
||||
|
||||
msize = CFG_DDR_SIZE; |
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0; |
||||
(ddr_size > 1); |
||||
ddr_size = ddr_size>>1, ddr_size_log2++) { |
||||
if (ddr_size & 1) { |
||||
return -1; |
||||
} |
||||
} |
||||
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); |
||||
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
||||
|
||||
#if (CFG_DDR_SIZE != 256) |
||||
#warning Currently any ddr size other than 256 is not supported |
||||
#endif |
||||
im->ddr.csbnds[2].csbnds = 0x0000000f; |
||||
im->ddr.cs_config[2] = CFG_DDR_CONFIG; |
||||
|
||||
/* currently we use only one CS, so disable the other banks */ |
||||
im->ddr.cs_config[0] = 0; |
||||
im->ddr.cs_config[1] = 0; |
||||
im->ddr.cs_config[3] = 0; |
||||
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
|
||||
im->ddr.sdram_cfg = |
||||
SDRAM_CFG_SREN |
||||
#if defined(CONFIG_DDR_2T_TIMING) |
||||
| SDRAM_CFG_2T_EN |
||||
#endif |
||||
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; |
||||
#if defined (CONFIG_DDR_32BIT) |
||||
/* for 32-bit mode burst length is 8 */ |
||||
im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); |
||||
#endif |
||||
im->ddr.sdram_mode = CFG_DDR_MODE; |
||||
|
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
||||
udelay(200); |
||||
|
||||
/* enable DDR controller */ |
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
||||
return msize; |
||||
} |
||||
#endif/*!CFG_SPD_EEPROM*/ |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts("Board: Wind River SBC834x\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* if board is fitted with SDRAM |
||||
*/ |
||||
#if defined(CFG_BR2_PRELIM) \ |
||||
&& defined(CFG_OR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR2_PRELIM) |
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
|
||||
void sdram_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile lbus83xx_t *lbc= &immap->lbus; |
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
||||
|
||||
puts("\n SDRAM on Local Bus: "); |
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
||||
*/ |
||||
|
||||
/* setup mtrpt, lsrt and lbcr for LB bus */ |
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
asm("sync"); |
||||
|
||||
/*
|
||||
* Configure the SDRAM controller Machine Mode Register. |
||||
*/ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ |
||||
asm("sync"); |
||||
/*1 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*2 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*3 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*4 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*5 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*6 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*7 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
/*8 times*/ |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
/* 0x58636733; mode register write operation */ |
||||
lbc->lsdmr = CFG_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
udelay(100); |
||||
} |
||||
#else |
||||
void sdram_init(void) |
||||
{ |
||||
puts(" SDRAM on Local Bus: Disabled in config\n"); |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) |
||||
/*
|
||||
* ECC user commands |
||||
*/ |
||||
void ecc_print_status(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ddr83xx_t *ddr = &immap->ddr; |
||||
|
||||
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); |
||||
|
||||
/* Interrupts */ |
||||
printf("Memory Error Interrupt Enable:\n"); |
||||
printf(" Multiple-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); |
||||
printf(" Single-Bit Error Interrupt Enable: %d\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); |
||||
printf(" Memory Select Error Interrupt Enable: %d\n\n", |
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); |
||||
|
||||
/* Error disable */ |
||||
printf("Memory Error Disable:\n"); |
||||
printf(" Multiple-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); |
||||
printf(" Sinle-Bit Error Disable: %d\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); |
||||
printf(" Memory Select Error Disable: %d\n\n", |
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); |
||||
|
||||
/* Error injection */ |
||||
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", |
||||
ddr->data_err_inject_hi, ddr->data_err_inject_lo); |
||||
|
||||
printf("Memory Data Path Error Injection Mask ECC:\n"); |
||||
printf(" ECC Mirror Byte: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); |
||||
printf(" ECC Injection Enable: %d\n", |
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); |
||||
printf(" ECC Error Injection Mask: 0x%02x\n\n", |
||||
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); |
||||
|
||||
/* SBE counter/threshold */ |
||||
printf("Memory Single-Bit Error Management (0..255):\n"); |
||||
printf(" Single-Bit Error Threshold: %d\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); |
||||
printf(" Single-Bit Error Counter: %d\n\n", |
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); |
||||
|
||||
/* Error detect */ |
||||
printf("Memory Error Detect:\n"); |
||||
printf(" Multiple Memory Errors: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); |
||||
printf(" Multiple-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); |
||||
printf(" Single-Bit Error: %d\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); |
||||
printf(" Memory Select Error: %d\n\n", |
||||
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); |
||||
|
||||
/* Capture data */ |
||||
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); |
||||
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", |
||||
ddr->capture_data_hi, ddr->capture_data_lo); |
||||
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", |
||||
ddr->capture_ecc & CAPTURE_ECC_ECE); |
||||
|
||||
printf("Memory Error Attributes Capture:\n"); |
||||
printf(" Data Beat Number: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); |
||||
printf(" Transaction Size: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); |
||||
printf(" Transaction Source: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); |
||||
printf(" Transaction Type: %d\n", |
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); |
||||
printf(" Error Information Valid: %d\n\n", |
||||
ddr->capture_attributes & ECC_CAPT_ATTR_VLD); |
||||
} |
||||
|
||||
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ddr83xx_t *ddr = &immap->ddr; |
||||
volatile u32 val; |
||||
u64 *addr, count, val64; |
||||
register u64 *i; |
||||
|
||||
if (argc > 4) { |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
if (argc == 2) { |
||||
if (strcmp(argv[1], "status") == 0) { |
||||
ecc_print_status(); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "captureclear") == 0) { |
||||
ddr->capture_address = 0; |
||||
ddr->capture_data_hi = 0; |
||||
ddr->capture_data_lo = 0; |
||||
ddr->capture_ecc = 0; |
||||
ddr->capture_attributes = 0; |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
if (argc == 3) { |
||||
if (strcmp(argv[1], "sbecnt") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBEC_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "sbethr") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 10); |
||||
if (val > 255) { |
||||
printf("Incorrect Counter value, should be 0..255\n"); |
||||
return 1; |
||||
} |
||||
|
||||
val = (val << ECC_ERROR_MAN_SBET_SHIFT); |
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); |
||||
|
||||
ddr->err_sbe = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdisable") == 0) { |
||||
val = ddr->err_disable; |
||||
|
||||
if (strcmp(argv[2], "+sbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "+mbe") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "+mse") == 0) { |
||||
val |= ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "+all") == 0) { |
||||
val |= (ECC_ERROR_DISABLE_SBED | |
||||
ECC_ERROR_DISABLE_MBED | |
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else if (strcmp(argv[2], "-sbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_SBED; |
||||
} else if (strcmp(argv[2], "-mbe") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MBED; |
||||
} else if (strcmp(argv[2], "-mse") == 0) { |
||||
val &= ~ECC_ERROR_DISABLE_MSED; |
||||
} else if (strcmp(argv[2], "-all") == 0) { |
||||
val &= ~(ECC_ERROR_DISABLE_SBED | |
||||
ECC_ERROR_DISABLE_MBED | |
||||
ECC_ERROR_DISABLE_MSED); |
||||
} else { |
||||
printf("Incorrect err_disable field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_disable = val; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) { |
||||
val = ddr->err_detect; |
||||
|
||||
if (strcmp(argv[2], "mme") == 0) { |
||||
val |= ECC_ERROR_DETECT_MME; |
||||
} else if (strcmp(argv[2], "sbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_SBE; |
||||
} else if (strcmp(argv[2], "mbe") == 0) { |
||||
val |= ECC_ERROR_DETECT_MBE; |
||||
} else if (strcmp(argv[2], "mse") == 0) { |
||||
val |= ECC_ERROR_DETECT_MSE; |
||||
} else if (strcmp(argv[2], "all") == 0) { |
||||
val |= (ECC_ERROR_DETECT_MME | |
||||
ECC_ERROR_DETECT_MBE | |
||||
ECC_ERROR_DETECT_SBE | |
||||
ECC_ERROR_DETECT_MSE); |
||||
} else { |
||||
printf("Incorrect err_detect field\n"); |
||||
return 1; |
||||
} |
||||
|
||||
ddr->err_detect = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_hi = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
|
||||
ddr->data_err_inject_lo = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "injectecc") == 0) { |
||||
val = simple_strtoul(argv[2], NULL, 16); |
||||
if (val > 0xff) { |
||||
printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); |
||||
return 1; |
||||
} |
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} else if (strcmp(argv[1], "inject") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EIEN; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EIEN; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
return 0; |
||||
} else if (strcmp(argv[1], "mirror") == 0) { |
||||
val = ddr->ecc_err_inject; |
||||
|
||||
if (strcmp(argv[2], "en") == 0) |
||||
val |= ECC_ERR_INJECT_EMB; |
||||
else if (strcmp(argv[2], "dis") == 0) |
||||
val &= ~ECC_ERR_INJECT_EMB; |
||||
else |
||||
printf("Incorrect command\n"); |
||||
|
||||
ddr->ecc_err_inject = val; |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
if (argc == 4) { |
||||
if (strcmp(argv[1], "test") == 0) { |
||||
addr = (u64 *)simple_strtoul(argv[2], NULL, 16); |
||||
count = simple_strtoul(argv[3], NULL, 16); |
||||
|
||||
if ((u32)addr % 8) { |
||||
printf("Address not alligned on double word boundary\n"); |
||||
return 1; |
||||
} |
||||
|
||||
disable_interrupts(); |
||||
icache_disable(); |
||||
|
||||
for (i = addr; i < addr + count; i++) { |
||||
/* enable injects */ |
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* write memory location injecting errors */ |
||||
*i = 0x1122334455667788ULL; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* disable injects */ |
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* read data, this generates ECC error */ |
||||
val64 = *i; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* disable errors for ECC */ |
||||
ddr->err_disable |= ~ECC_ERROR_ENABLE; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
|
||||
/* re-initialize memory, write the location again
|
||||
* NOT injecting errors this time */ |
||||
*i = 0xcafecafecafecafeULL; |
||||
__asm__ __volatile__ ("sync"); |
||||
|
||||
/* enable errors for ECC */ |
||||
ddr->err_disable &= ECC_ERROR_ENABLE; |
||||
__asm__ __volatile__ ("sync"); |
||||
__asm__ __volatile__ ("isync"); |
||||
} |
||||
|
||||
icache_enable(); |
||||
enable_interrupts(); |
||||
|
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
ecc, 4, 0, do_ecc, |
||||
"ecc - support for DDR ECC features\n", |
||||
"status - print out status info\n" |
||||
"ecc captureclear - clear capture regs data\n" |
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n" |
||||
"ecc sbethr <val> - set Single-Bit Threshold\n" |
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n" |
||||
" [-|+]sbe - Single-Bit Error\n" |
||||
" [-|+]mbe - Multiple-Bit Error\n" |
||||
" [-|+]mse - Memory Select Error\n" |
||||
" [-|+]all - all errors\n" |
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n" |
||||
" mme - Multiple Memory Errors\n" |
||||
" sbe - Single-Bit Error\n" |
||||
" mbe - Multiple-Bit Error\n" |
||||
" mse - Memory Select Error\n" |
||||
" all - all errors\n" |
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n" |
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n" |
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n" |
||||
"ecc inject <en|dis> - enable/disable error injection\n" |
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n" |
||||
"ecc test <addr> <cnt> - test mem region:\n" |
||||
" - enables injects\n" |
||||
" - writes pattern injecting errors\n" |
||||
" - disables injects\n" |
||||
" - reads pattern back, generates error\n" |
||||
" - re-inits memory" |
||||
); |
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ |
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void |
||||
ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
#ifdef CONFIG_PCI |
||||
ft_pci_setup(blob, bd); |
||||
#endif |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len); |
||||
if (p != NULL) { |
||||
*p++ = cpu_to_be32(bd->bi_memstart); |
||||
*p = cpu_to_be32(bd->bi_memsize); |
||||
} |
||||
} |
||||
#endif |
||||
@ -0,0 +1,125 @@ |
||||
/* |
||||
* Copyright (c) 2006 Wind River Systems, Inc. |
||||
* u-boot.lds for WindRiver SBC8349. |
||||
* |
||||
* Based on the MPC8349 u-boot.lds |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,129 @@ |
||||
Freescale MPC832XEMDS Board |
||||
----------------------------------------- |
||||
1. Board Switches and Jumpers |
||||
1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board |
||||
For some reason, the HW designers describe the switch settings |
||||
in terms of 0 and 1, and then map that to physical switches where |
||||
the label "On" refers to logic 0 and "Off" is logic 1. |
||||
|
||||
Switch bits are numbered 1 through, like, 4 6 8 or 10, but the |
||||
bits may contribute to signals that are numbered based at 0, |
||||
and some of those signals may be high-bit-number-0 too. Heed |
||||
well the names and labels and do not get confused. |
||||
|
||||
"Off" == 1 |
||||
"On" == 0 |
||||
|
||||
SW3 is switch 18 as silk-screened onto the board. |
||||
SW4[8] is the bit labled 8 on Switch 4. |
||||
SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. |
||||
SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. |
||||
SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" |
||||
and bits labeled 8 is set as "Off". |
||||
|
||||
1.1 For the MPC832XEMDS PROTO Board |
||||
|
||||
First, make sure the board default setting is consistent with the document |
||||
shipped with your board. Then apply the following setting: |
||||
SW3[1-8]= 0000_1000 (core PLL setting, core enable) |
||||
SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) |
||||
SW5[1-8]= 0010_0110 (Boot from high end) |
||||
SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) |
||||
SW7[1-8]= 1000_0011 (QE PLL setting) |
||||
|
||||
ENET3/4 MII mode settings: |
||||
J1 1-2 (ETH3_TXER) |
||||
J2 2-3 (MII mode) |
||||
J3 2-3 (MII mode) |
||||
J4 2-3 (ADSL clockOscillator) |
||||
J5 1-2 (ETH4_TXER) |
||||
J6 2-3 (ClockOscillator) |
||||
JP1 removed (don't force PORESET) |
||||
JP2 mounted (ETH4/2 MII) |
||||
JP3 mounted (ETH3 MII) |
||||
JP4 mounted (HRCW from BCSR) |
||||
|
||||
ENET3/4 RMII mode settings: |
||||
J1 1-2 (ETH3_TXER) |
||||
J2 1-2 (RMII mode) |
||||
J3 1-2 (RMII mode) |
||||
J4 2-3 (ADSL clockOscillator) |
||||
J5 1-2 (ETH4_TXER) |
||||
J6 2-3 (ClockOscillator) |
||||
JP1 removed (don't force PORESET) |
||||
JP2 removed (ETH4/2 RMII) |
||||
JP3 removed (ETH3 RMII) |
||||
JP4 removed (HRCW from FLASH) |
||||
|
||||
on board Oscillator: 66M |
||||
|
||||
|
||||
2. Memory Map |
||||
|
||||
2.1 The memory map should look pretty much like this: |
||||
|
||||
0x0000_0000 0x7fff_ffff DDR 2G |
||||
0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M |
||||
0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M |
||||
0xc000_0000 0xdfff_ffff Empty 512M |
||||
0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M |
||||
0xe020_0000 0xe02f_ffff Empty 1M |
||||
0xe030_0000 0xe03f_ffff PCI IO 1M |
||||
0xe040_0000 0xefff_ffff Empty 252M |
||||
0xf400_0000 0xf7ff_ffff Empty 64M |
||||
0xf800_0000 0xf800_7fff BCSR on CS1 32K |
||||
0xf800_8000 0xf800_ffff PIB CS2 32K |
||||
0xf801_0000 0xf801_7fff PIB CS3 32K |
||||
0xfe00_0000 0xfeff_ffff FLASH on CS0 16M |
||||
|
||||
|
||||
3. Definitions |
||||
|
||||
3.1 Explanation of NEW definitions in: |
||||
|
||||
include/configs/MPC832XEPB.h |
||||
|
||||
CONFIG_MPC83XX MPC83XX family for MPC8349, MPC8360 and MPC832X |
||||
CONFIG_MPC832X MPC832X specific |
||||
CONFIG_MPC832XEMDS MPC832XEMDS board specific |
||||
|
||||
4. Compilation |
||||
|
||||
Assuming you're using BASH shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix |
||||
cd u-boot |
||||
make distclean |
||||
make MPC832XEMDS_config |
||||
make |
||||
|
||||
MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: |
||||
|
||||
1)Make sure the DIP SW support PCI mode as described in Section 1.1. |
||||
|
||||
2)To Make U-Boot image support PCI 33MHz, use |
||||
Make MPC832XEMDS_HOST_33_config |
||||
|
||||
3)To Make U-Boot image support PCI 66MHz, use |
||||
Make MPC832XEMDS_HOST_66M_config |
||||
|
||||
5. Downloading and Flashing Images |
||||
|
||||
5.0 Download over network: |
||||
|
||||
tftp 10000 u-boot.bin |
||||
|
||||
5.1 Reflash U-boot Image using U-boot |
||||
|
||||
tftp 20000 u-boot.bin |
||||
protect off fe000000 fe0fffff |
||||
erase fe000000 fe0fffff |
||||
cp.b 20000 fe000000 xxxx |
||||
|
||||
You have to supply the correct byte count with 'xxxx' from the TFTP result log. |
||||
Maybe 3ffff will work too, that corresponds to the erased sectors. |
||||
|
||||
|
||||
6. Notes |
||||
1) The console baudrate for MPC832XEMDS is 115200bps. |
||||
|
||||
@ -0,0 +1,187 @@ |
||||
Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards |
||||
--------------------------------------------------- |
||||
|
||||
1. Board Description |
||||
|
||||
The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring |
||||
the Freescale MPC8349E processor in a Mini-ITX form factor. |
||||
|
||||
The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: |
||||
|
||||
A) One 8MB on-board flash EEPROM chip, instead of two. |
||||
B) No SATA controller |
||||
C) No Compact Flash slot |
||||
D) No Mini-PCI slot |
||||
E) No Vitesse 7385 5-port Ethernet switch |
||||
F) No 4-port USB Type-A interface |
||||
|
||||
2. Board Switches and Jumpers |
||||
|
||||
2.0 Descriptions for all of the board jumpers can be found in the User |
||||
Guide. Of particular interest to U-Boot developers is jumper J22: |
||||
|
||||
Pos. Name Default Description |
||||
----------------------------------------------------------------------- |
||||
A LGPL0 ON (0) HRCW source, bit 0 |
||||
B LGPL1 ON (0) HRCW source, bit 1 |
||||
C LGPL3 ON (0) HRCW source, bit 2 |
||||
D LGPL5 OFF (1) PCI_SYNC_OUT frequency |
||||
E BOOT1 ON (0) Flash EEPROM boot device |
||||
F PCI_M66EN ON (0) PCI 66MHz enable |
||||
G I2C-WP ON (0) I2C EEPROM write protection |
||||
H F_WP OFF (1) Flash EEPROM write protection |
||||
|
||||
Jumper J22.E is only for the ITX, and it decides the configuration |
||||
of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip |
||||
U4 is located at address FE000000 and flash chip U7 is at FE800000. |
||||
If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. |
||||
|
||||
For U-Boot development, J22.E can be used to switch back-and-forth |
||||
between two U-Boot images. |
||||
|
||||
3. Memory Map |
||||
|
||||
3.1. The memory map should look pretty much like this: |
||||
|
||||
0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) |
||||
0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) |
||||
0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) |
||||
0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) |
||||
0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) |
||||
0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) |
||||
0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) |
||||
0xF001_0000 - 0xF001_FFFF Local bus expansion slot |
||||
0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) |
||||
0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory |
||||
0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) |
||||
|
||||
3.2 Flash EEPROM layout. |
||||
|
||||
On the ITX, jumper J22.E is used to determine which flash chips are |
||||
at which address. When J22.E is switched, addresses from FE000000 |
||||
to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. |
||||
|
||||
On the ITX, at the normal boot address (aka HIGHBOOT): |
||||
|
||||
FE00_0000 HRCW |
||||
FE70_0000 Alternative U-Boot image |
||||
FE80_0000 Alternative HRCW |
||||
FEF0_0000 U-Boot image |
||||
FEFF_FFFF End of flash |
||||
|
||||
On the ITX, at the low boot address (LOWBOOT) |
||||
|
||||
FE00_0000 HRCW and U-Boot image |
||||
FE04_0000 U-Boot environment variables |
||||
FE80_0000 Alternative HRCW and U-Boot image |
||||
FEFF_FFFF End of flash |
||||
|
||||
On the ITX-GP, the only option is LOWBOOT and there is only one chip |
||||
|
||||
FE00_0000 HRCW and U-Boot image |
||||
FE04_0000 U-Boot environment variables |
||||
F7FF_FFFF End of flash |
||||
|
||||
4. Definitions |
||||
|
||||
4.1 Explanation of NEW definitions in: |
||||
|
||||
include/configs/MPC8349ITX.h |
||||
|
||||
CONFIG_MPC83XX MPC83xx family |
||||
CONFIG_MPC8349 MPC8349 specific |
||||
CONFIG_MPC8349ITX MPC8349E-mITX |
||||
CONFIG_MPC8349ITXGP MPC8349E-mITX-GP |
||||
|
||||
5. Compilation |
||||
|
||||
Assuming you're using BASH shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix |
||||
cd u-boot |
||||
make distclean |
||||
|
||||
make MPC8349ITX_config |
||||
or: |
||||
make MPC8349ITXGP_config |
||||
or: |
||||
make MPC8349ITX_LOWBOOT_config |
||||
|
||||
make |
||||
|
||||
6. Downloading and Flashing Images |
||||
|
||||
6.1 Download via tftp: |
||||
|
||||
tftp $loadaddr <uboot> |
||||
|
||||
where "<uboot>" is the path and filename, on the TFTP server, of |
||||
the U-Boot image. |
||||
|
||||
6.1 Reflash U-Boot Image using U-Boot |
||||
|
||||
setenv uboot <uboot> |
||||
run tftpflash |
||||
|
||||
where "<uboot>" is the path and filename, on the TFTP server, of |
||||
the U-Boot image. |
||||
|
||||
6.2 Using the HRCW to switch between two different U-Boot images on the ITX |
||||
|
||||
Because the ITX has 16MB of flash, it is possible to keep two U-Boot |
||||
images in flash, and use the HRCW to specify which one is to be used |
||||
when the board boots. This trick is especially effective with a |
||||
hardware debugger that can override the HRCW, such as the BDI-2000. |
||||
|
||||
When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image |
||||
at address FE000000. When the BMS bit is 1, the ITX will boot the |
||||
image at address FEF00000. |
||||
|
||||
Therefore, just put a U-Boot image at both FE000000 and FEF00000 and |
||||
change the BMS bit whenever you want to boot the other image. |
||||
|
||||
Step-by-step instructions: |
||||
|
||||
1) Build an ITX image to be loaded at FEF00000 |
||||
|
||||
make distclean |
||||
make MPC8349ITX_config |
||||
make |
||||
|
||||
2) Take the u-boot.bin image and flash it at FEF00000. |
||||
|
||||
tftp $loadaddr u-boot.bin |
||||
protect off all |
||||
erase FEF00000 +$filesize |
||||
cp.b $loadaddr FEF00000 $filesize |
||||
|
||||
3) Build an ITX image to be loaded at FE000000 |
||||
|
||||
make distclean |
||||
make MPC8349ITX_LOWBOOT_config |
||||
make |
||||
|
||||
4) Take the u-boot.bin image and flash it at FE000000. |
||||
|
||||
tftp $loadaddr u-boot.bin |
||||
protect off FE000000 +$filesize |
||||
erase FE000000 +$filesize |
||||
cp.b $loadaddr FE000000 $filesize |
||||
|
||||
The HRCW in flash is currently set to boot the image at FE000000. |
||||
|
||||
If you have a hardware debugger, configure it to set the HRCW to |
||||
B460A000 04040000 if you want to boot the image at FEF00000, or set |
||||
it to B060A000 04040000 if you want to boot the image at FE000000. |
||||
|
||||
To change the HRCW in flash to boot the image at FEF00000, use these |
||||
U-Boot commands: |
||||
|
||||
cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 |
||||
mw.b 1020 b4 8 ; modify BMS bit |
||||
protect off FE000000 +10000 |
||||
erase FE000000 +10000 |
||||
cp.b 1000 FE000000 10000 |
||||
|
||||
7. Notes |
||||
1) The console baudrate for MPC8349EITX is 115200bps. |
||||
@ -0,0 +1,99 @@ |
||||
|
||||
|
||||
U-Boot for Wind River SBC834x Boards |
||||
==================================== |
||||
|
||||
|
||||
The Wind River SBC834x board is a 6U form factor (not CPCI) reference |
||||
design that uses the MPC8347E or MPC8349E processor. U-Boot support |
||||
for this board is heavily based on the existing U-Boot support for |
||||
Freescale MPC8349 reference boards. |
||||
|
||||
Support has been primarily tested on the SBC8349 version of the board, |
||||
although earlier versions were also tested on the SBC8347. The primary |
||||
difference in the two is the level of PCI functionality. |
||||
|
||||
http://www.windriver.com/products/OCD/SBC8347E_49E/ |
||||
|
||||
|
||||
Flash Details: |
||||
============== |
||||
|
||||
The flash type is intel 28F640Jx (4096x16) [one device]. Base address |
||||
is 0xFF80_0000 which is also where the Hardware Reset Configuration |
||||
Word (HRCW) is stored. Caution should be used to not overwrite the |
||||
HRCW, or "CF RCW" with a Wind River ICE will be required to restore |
||||
the HRCW and allow the board to enter background mode for further |
||||
steps in the flash process. |
||||
|
||||
|
||||
Restoring a corrupted or missing flash image: |
||||
============================================= |
||||
|
||||
Details for storing U-boot to flash using a Wind River ICE can be found |
||||
on page 19 of the board manual (request ERG-00328-001). The following |
||||
is a summary of that information: |
||||
|
||||
- Connect ICE and establish connection to it from WorkBench/OCD. |
||||
- Ensure you have background mode (BKM) in the OCD terminal window. |
||||
- Select the appropriate flash type (listed above) |
||||
- Prepare a u-boot image by using the Wind River Convert utility; |
||||
by using "Convert and Add file" on the ELF file from your build. |
||||
Convert from FFF0_0000 to FFFF_FFFF (or to FFF3_FFFF if you are |
||||
trying to preserve your old environment settings). |
||||
- Set the start address of the erase/flash process to FFF0_0000 |
||||
- Set the target RAM required to 64kB. |
||||
- Select sectors for erasing (see note on enviroment below) |
||||
- Select Erase and Reprogram. |
||||
|
||||
Note that some versions of the register files used with Workbench |
||||
would zero some TSEC registers, which inhibits ethernet operation |
||||
by u-boot when this register file is played to the target. Using |
||||
"INN" in the OCD terminal window instead of "IN" before the "GO" |
||||
will not play the register file, and allow u-boot to use the TSEC |
||||
interface while executed from the ICE "GO" command. |
||||
|
||||
Alternatively, you can locate the register file which will be named |
||||
WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines |
||||
beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to |
||||
use all the remaining register file content. |
||||
|
||||
If you wish to preserve your prior U-Boot environment settings, |
||||
then convert (and erase to) 0xFFF3FFFF instead of 0xFFFFFFFF. |
||||
The size for converting (and erasing) must be at least as large |
||||
as u-boot.bin. |
||||
|
||||
|
||||
Updating U-Boot with U-Boot: |
||||
============================ |
||||
|
||||
This procedure is very similar to other boards that have u-boot installed. |
||||
Assuming that the network has been configured, and that the new u-boot.bin |
||||
has been copied to the TFTP server, the commands are: |
||||
|
||||
tftp 200000 u-boot.bin |
||||
protect off all |
||||
erase fff00000 fff3ffff |
||||
cp.b 200000 fff00000 3ffff |
||||
protect on all |
||||
|
||||
|
||||
PCI: |
||||
==== |
||||
|
||||
This board and U-Boot have been tested with PCI built in, on a SBC8349 |
||||
and confirmed that the "pci" command showed the intel e1000 that was |
||||
present in the PCI slot. Note that if a 33MHz 32bit card is inserted |
||||
in the slot, then the whole board will clock down to a 33MHz base |
||||
clock instead of the default 66MHz. This will change the baud clocks |
||||
and mess up your serial console output. If you want to use a 33MHz PCI |
||||
card, then you should build a U-Boot with #undef PCI_66M in the |
||||
include/configs/sbc8349.h and store this to flash prior to powering down |
||||
the board and inserting the 33MHz PCI card. |
||||
|
||||
By default PCI support is disabled to better support very early |
||||
revision MPC834x chips with possible PCI issues. Also PCI support is |
||||
untested on the sbc8347 variants at this point in time. |
||||
|
||||
|
||||
Paul Gortmaker, 01/2007 |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,631 @@ |
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 family */ |
||||
#define CONFIG_QE 1 /* Has QE */ |
||||
#define CONFIG_MPC83XX 1 /* MPC83xx family */ |
||||
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ |
||||
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ |
||||
|
||||
/*
|
||||
* System Clock Setup |
||||
*/ |
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word |
||||
*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CSB_TO_CLKIN_2X1 |\
|
||||
HRCWL_CORE_TO_CSB_2X1 |\
|
||||
HRCWL_CE_PLL_VCO_DIV_2 |\
|
||||
HRCWL_CE_PLL_DIV_1X1 |\
|
||||
HRCWL_CE_TO_PLL_1X3) |
||||
|
||||
#ifdef CONFIG_PCISLAVE |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_AGENT |\
|
||||
HRCWH_PCI1_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_NORMAL) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_NORMAL) |
||||
#endif |
||||
|
||||
/*
|
||||
* System IO Config |
||||
*/ |
||||
#define CFG_SICRL 0x00000000 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
||||
#define CFG_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ |
||||
|
||||
#undef CONFIG_SPD_EEPROM |
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/* Determine DDR configuration from I2C interface
|
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ |
||||
#else |
||||
/* Manually set up DDR parameters
|
||||
*/ |
||||
#define CFG_DDR_SIZE 128 /* MB */ |
||||
#define CFG_DDR_CS0_CONFIG 0x80840102 |
||||
#define CFG_DDR_TIMING_0 0x00220802 |
||||
#define CFG_DDR_TIMING_1 0x3935d322 |
||||
#define CFG_DDR_TIMING_2 0x0f9048ca |
||||
#define CFG_DDR_TIMING_3 0x00000000 |
||||
#define CFG_DDR_CLK_CNTL 0x02000000 |
||||
#define CFG_DDR_MODE 0x44400232 |
||||
#define CFG_DDR_MODE2 0x8000c000 |
||||
#define CFG_DDR_INTERVAL 0x03200064 |
||||
#define CFG_DDR_CS0_BNDS 0x00000007 |
||||
#define CFG_DDR_SDRAM_CFG 0x43080000 |
||||
#define CFG_DDR_SDRAM_CFG2 0x00401000 |
||||
#endif |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ |
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
|
||||
/*
|
||||
* BCSR on the Local Bus |
||||
*/ |
||||
#define CFG_BCSR 0xF8000000 |
||||
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ |
||||
|
||||
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ |
||||
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ |
||||
|
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON 0x0063b723 |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* Windows to access PIB via local bus |
||||
*/ |
||||
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
||||
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ |
||||
|
||||
/*
|
||||
* CS2 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ |
||||
#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* CS3 on Local Bus, to PIB |
||||
*/ |
||||
#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ |
||||
#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8323@0" |
||||
#define OF_SOC "soc8323@e0000000" |
||||
#define OF_QE "qe@e0100000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI_MEM_BASE 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE |
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_IO_BASE 0xE0300000 |
||||
#define CFG_PCI_IO_PHYS 0xE0300000 |
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE |
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000 |
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000 |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* QE UEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_UEC_ETH |
||||
#define CONFIG_ETHPRIME "Freescale GETH" |
||||
|
||||
#define CONFIG_UEC_ETH1 /* ETH3 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH1 |
||||
#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ |
||||
#define CFG_UEC1_RX_CLK QE_CLK9 |
||||
#define CFG_UEC1_TX_CLK QE_CLK10 |
||||
#define CFG_UEC1_ETH_TYPE FAST_ETH |
||||
#define CFG_UEC1_PHY_ADDR 3 |
||||
#define CFG_UEC1_INTERFACE_MODE ENET_100_MII |
||||
#endif |
||||
|
||||
#define CONFIG_UEC_ETH2 /* ETH4 */ |
||||
|
||||
#ifdef CONFIG_UEC_ETH2 |
||||
#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ |
||||
#define CFG_UEC2_RX_CLK QE_CLK7 |
||||
#define CFG_UEC2_TX_CLK QE_CLK8 |
||||
#define CFG_UEC2_ETH_TYPE FAST_ETH |
||||
#define CFG_UEC2_PHY_ADDR 4 |
||||
#define CFG_UEC2_INTERFACE_MODE ENET_100_MII |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_I2C ) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* Cache Config |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* IMMRBAR & PCI IO: cache-inhibit and guarded */ |
||||
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* BCSR: cache-inhibit and guarded */ |
||||
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
#define CFG_IBAT4L (0) |
||||
#define CFG_IBAT4U (0) |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
|
||||
#ifdef CONFIG_PCI |
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#else |
||||
#define CFG_IBAT6L (0) |
||||
#define CFG_IBAT6U (0) |
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_UEC_ETH) |
||||
#define CONFIG_ETHADDR 00:04:9f:ef:03:01 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=mpc832xemds.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,734 @@ |
||||
/*
|
||||
* WindRiver SBC8349 U-Boot configuration file. |
||||
* Copyright (c) 2006, 2007 Wind River Systems, Inc. |
||||
* |
||||
* Paul Gortmaker <paul.gortmaker@windriver.com> |
||||
* Based on the MPC8349EMDS config. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* sbc8349 board configuration file. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 Family */ |
||||
#define CONFIG_MPC83XX 1 /* MPC83XX family */ |
||||
#define CONFIG_MPC834X 1 /* MPC834X family */ |
||||
#define CONFIG_MPC8349 1 /* MPC8349 specific */ |
||||
#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ |
||||
|
||||
#undef CONFIG_PCI |
||||
/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
||||
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ |
||||
|
||||
#define PCI_66M |
||||
#ifdef PCI_66M |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#ifdef PCI_66M |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ 33000000 |
||||
#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
||||
#endif |
||||
#endif |
||||
|
||||
#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
#define CFG_IMMR 0xE0000000 |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
||||
#define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
||||
|
||||
/*
|
||||
* 32-bit data path mode. |
||||
* |
||||
* Please note that using this mode for devices with the real density of 64-bit |
||||
* effectively reduces the amount of available memory due to the effect of |
||||
* wrapping around while translating address to row/columns, for example in the |
||||
* 256MB module the upper 128MB get aliased with contents of the lower |
||||
* 128MB); normally this define should be used for devices with real 32-bit |
||||
* data path. |
||||
*/ |
||||
#undef CONFIG_DDR_32BIT |
||||
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
||||
#define CONFIG_DDR_2T_TIMING |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ |
||||
|
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
* NB: manual DDR setup untested on sbc834x |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* MB */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
||||
#define CFG_DDR_TIMING_1 0x36332321 |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
||||
#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
||||
|
||||
#if defined(CONFIG_DDR_32BIT) |
||||
/* set burst length to 8 for 32-bit data path */ |
||||
#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ |
||||
#else |
||||
/* the default burst length is 4 - for 64-bit data path */ |
||||
#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ |
||||
#define CFG_FLASH_SIZE 8 /* flash size in MB */ |
||||
/* #define CFG_FLASH_USE_BUFFER_WRITE */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 32 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
|
||||
#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ |
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_MID_FLASH_JUMP 0x7F000000 |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
* LCRR: DLL bypass, Clock divider is 4 |
||||
* External Local Bus rate is |
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
#undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 |
||||
* |
||||
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* FIXME: the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ |
||||
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xFC006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ |
||||
| CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR8 \
|
||||
| CFG_LBC_LSDMR_PRETOACT6 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC3 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
) |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8349@0" |
||||
#define OF_SOC "soc8349@e0000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
||||
#define CFG_I2C1_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
#define CFG_I2C_OFFSET CFG_I2C2_OFFSET |
||||
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ |
||||
|
||||
/* TSEC */ |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
||||
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xE2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xA0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_MMIO_BASE 0xB0000000 |
||||
#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE |
||||
#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS 0xE2100000 |
||||
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
#define PCI_64BIT |
||||
#define PCI_ONE_PCI1 |
||||
#if defined(PCI_64BIT) |
||||
#undef PCI_ALL_PCI1 |
||||
#undef PCI_TWO_PCI1 |
||||
#undef PCI_ONE_PCI1 |
||||
#endif |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xFIXME |
||||
#define PCI_ENET0_MEMADDR 0xFIXME |
||||
#define PCI_IDSEL_NUMBER 0xFIXME |
||||
#endif |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
/*
|
||||
* TSEC configuration |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MPC83XX_TSEC1 1 |
||||
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_MPC83XX_TSEC2 1 |
||||
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
||||
#define CONFIG_PHY_BCM5421S 1 |
||||
#define TSEC1_PHY_ADDR 0x19 |
||||
#define TSEC2_PHY_ADDR 0x1a |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
|
||||
/* Options are: TSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "TSEC0" |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
|
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C \
|
||||
) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C \
|
||||
| CFG_CMD_MII \
|
||||
) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#if 1 /*528/264*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
#elif 0 /*396/132*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN |\
|
||||
HRCWL_VCO_1X4 |\
|
||||
HRCWL_CORE_TO_CSB_3X1) |
||||
#elif 0 /*264/132*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN |\
|
||||
HRCWL_VCO_1X4 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
#elif 0 /*132/132*/ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN |\
|
||||
HRCWL_VCO_1X4 |\
|
||||
HRCWL_CORE_TO_CSB_1X1) |
||||
#elif 0 /*264/264 */ |
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN |\
|
||||
HRCWL_VCO_1X4 |\
|
||||
HRCWL_CORE_TO_CSB_1X1) |
||||
#endif |
||||
|
||||
#if defined(PCI_64BIT) |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_64_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_32_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#endif |
||||
|
||||
/* System IO Config */ |
||||
#define CFG_SICRH SICRH_TSOBI1 |
||||
#define CFG_SICRL SICRL_LDP_A |
||||
|
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
||||
|
||||
/* #define CFG_HID0_FINAL (\
|
||||
HID0_ENABLE_INSTRUCTION_CACHE |\
|
||||
HID0_ENABLE_M_BIT |\
|
||||
HID0_ENABLE_ADDRESS_BROADCAST ) */ |
||||
|
||||
|
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI @ 0x80000000 */ |
||||
#ifdef CONFIG_PCI |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT1L (0) |
||||
#define CFG_IBAT1U (0) |
||||
#define CFG_IBAT2L (0) |
||||
#define CFG_IBAT2U (0) |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT3L (0) |
||||
#define CFG_IBAT3U (0) |
||||
#define CFG_IBAT4L (0) |
||||
#define CFG_IBAT4U (0) |
||||
#endif |
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ |
||||
#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
||||
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 192.168.1.234 |
||||
|
||||
#define CONFIG_HOSTNAME SBC8349 |
||||
#define CONFIG_ROOTPATH /tftpboot/rootfs |
||||
#define CONFIG_BOOTFILE uImage |
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=sbc8349\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
|
||||
"update=protect off fff00000 fff3ffff; " \
|
||||
"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=sbc8349.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in new issue