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arm: socfpga: Remove AV-specific parts from CV-SoCDK

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Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
master
Marek Vasut 9 years ago
parent c68eea0492
commit 37b3a30ae6
8 changed files with 0 additions and 1153 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 688
      board/altera/cyclone5-socdk/qts/iocsr_config.c
  2. 9
      board/altera/cyclone5-socdk/qts/iocsr_config.h
  3. 215
      board/altera/cyclone5-socdk/qts/pinmux_config.c
  4. 14
      board/altera/cyclone5-socdk/qts/sdram_config.h
  5. 20
      board/altera/cyclone5-socdk/qts/sequencer_auto.h
  6. 40
      board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h
  7. 132
      board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h
  8. 35
      board/altera/cyclone5-socdk/qts/sequencer_defines.h

688
board/altera/cyclone5-socdk/qts/iocsr_config.c
Unescape View File

@ -8,7 +8,6 @@
#include "iocsr_config.h"
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
@ -656,690 +655,3 @@ const unsigned long iocsr_scan_chain3_table[((
0x0000001F,
0x00004100,
};
#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
const unsigned long iocsr_scan_chain0_table[((
CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00008000,
0x00060180,
0x18060000,
0x18000060,
0x00018060,
0x06018060,
0x00004000,
0x0C0300C0,
0x0C030000,
0x00000030,
0x00000000,
0x00000000,
0x00002000,
0x00000000,
0x00000000,
0x06000000,
0x00006018,
0x01806018,
0x00001000,
0x0000C030,
0x04000000,
0x03000000,
0x0000300C,
0x00000000,
0x00000800,
0x00006018,
0x01806000,
0x01800000,
0x00000006,
0x00001806,
0x00000400,
0x0000300C,
0x00C03000,
0x00C00000,
0x00000003,
0x00000C03,
0x00000200,
};
const unsigned long iocsr_scan_chain1_table[((
CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
0x00100000,
0x300C0000,
0x300000C0,
0x000000C0,
0x000300C0,
0x00008000,
0x00060180,
0x18060000,
0x18000000,
0x00000060,
0x00018060,
0x00004000,
0x000300C0,
0x10000000,
0x0C000000,
0x00000030,
0x0000C030,
0x00002000,
0x06018060,
0x06018000,
0x01FE0000,
0xF8000000,
0x00000007,
0x00001000,
0x0000C030,
0x0300C000,
0x03000000,
0x0000300C,
0x0000300C,
0x00000800,
0x00006018,
0x01806000,
0x01800000,
0x00000006,
0x00002000,
0x00000400,
0x0000300C,
0x01000000,
0x00000000,
0x00000004,
0x00000C03,
0x00000200,
0x00001806,
0x00800000,
0x00000000,
0x00000002,
0x00000800,
0x00000100,
0x00001000,
0x00400000,
0xC0300000,
0x00000000,
0x00000400,
0x00000080,
};
const unsigned long iocsr_scan_chain2_table[((
CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
0x00100000,
0x40000000,
0x00000000,
0x00000100,
0x00040000,
0x00008000,
0x18060180,
0x20000000,
0x00000000,
0x00000080,
0x00020000,
0x00004000,
0x00040000,
0x10000000,
0x00000000,
0x00000000,
0x00010000,
0x00002000,
0x10038060,
0x00000000,
0x00000000,
0x00000020,
0x01806018,
0x00001000,
0x00010000,
0x04000000,
0x03000000,
0x0000801C,
0x00004000,
0x00000800,
0x01806018,
0x02000000,
0x00000000,
0x00000008,
0x00002000,
0x00000400,
0x00C0300C,
0x00C03000,
0x00C00003,
0x00000C03,
0x00300C03,
0x00000200,
0x00601806,
0x80601800,
0x80600001,
0x80000601,
0x00180601,
0x00000100,
};
const unsigned long iocsr_scan_chain3_table[((
CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
0x2C820D80,
0x082000FF,
0x0A804001,
0x07900000,
0x08020000,
0x00100000,
0x0A800000,
0x07900000,
0x08020000,
0x00100000,
0xC8800000,
0x00003001,
0x00C00722,
0x00000000,
0x00000021,
0x82000004,
0x05400000,
0x03C80000,
0x04010000,
0x00080000,
0x05400000,
0x03C80000,
0x05400000,
0x03C80000,
0xE4400000,
0x00001800,
0x00600391,
0x800E4400,
0x00000001,
0x40000002,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x72200000,
0x80000C00,
0x003001C8,
0xC0072200,
0x1C880000,
0x20000300,
0x00040000,
0x50670000,
0x00000050,
0x24590000,
0x00001000,
0xA0000034,
0x0D000001,
0x906808A2,
0xA2834024,
0x05141A00,
0x808A20D0,
0x34024906,
0x01A00A28,
0xA20D0000,
0x24906808,
0x00A28340,
0xD000001A,
0x06808A20,
0x10040000,
0x00200000,
0x10040000,
0x00200000,
0x15000000,
0x0F200000,
0x15000000,
0x0F200000,
0x01FE0000,
0x00000000,
0x01800E44,
0x00391000,
0x007F8006,
0x00000000,
0x0A800001,
0x07900000,
0x0A800000,
0x07900000,
0x0A800000,
0x07900000,
0x08020000,
0x00100000,
0xC8800000,
0x00003001,
0x00C00722,
0x00000FF0,
0x72200000,
0x80000C00,
0x05400000,
0x02480000,
0x04000000,
0x00080000,
0x05400000,
0x03C80000,
0x05400000,
0x03C80000,
0x6A1C0000,
0x00001800,
0x00600391,
0x800E4400,
0x1A870001,
0x40000600,
0x02A00040,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x02A00000,
0x01E40000,
0x72200000,
0x80000C00,
0x003001C8,
0xC0072200,
0x1C880000,
0x20000300,
0x00040000,
0x50670000,
0x00000050,
0x24590000,
0x00001000,
0xA0000034,
0x0D000001,
0x906808A2,
0xA2834024,
0x05141A00,
0x808A20D0,
0x34024906,
0x01A00040,
0xA20D0002,
0x24906808,
0x00A28340,
0xD005141A,
0x06808A20,
0x10040000,
0x00200000,
0x10040000,
0x00200000,
0x15000000,
0x0F200000,
0x15000000,
0x0F200000,
0x01FE0000,
0x00000000,
0x01800E44,
0x00391000,
0x007F8006,
0x00000000,
0x99300001,
0x34343400,
0xAA0D4000,
0x01C3A810,
0xAA0D4000,
0x01C3A808,
0xAA0D4000,
0x01C3A810,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x01000000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x0002A000,
0x0001E400,
0x5506A000,
0x00E1D404,
0x00000000,
0xC880090C,
0x00003001,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA04,
0x2A835000,
0x0070EA02,
0x2A835000,
0x0070EA04,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00002000,
0x80000000,
0x00104120,
0x00000200,
0xAC055F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xBA28A3D8,
0xF511451E,
0x0341D348,
0x821A0000,
0x0000D000,
0x04510680,
0xD859647A,
0x1EBA28A3,
0x48F51145,
0x000341D3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875011,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x00003FC2,
0x00820000,
0xAA0D4000,
0x01C3A810,
0xAA0D4000,
0x01C3A808,
0xAA0D4000,
0x01C3A810,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x00020080,
0x00000400,
0x5506A000,
0x00E1D404,
0x00000000,
0x0000090C,
0x00000010,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA04,
0x2A835000,
0x0070EA02,
0x2A835000,
0x0070EA04,
0x00015000,
0x0000F200,
0x00000000,
0x00000482,
0x00120800,
0x00600391,
0x80000000,
0x00104120,
0x00000200,
0xAC055F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xBA28A3D8,
0xF511451E,
0x8341D348,
0x821A0124,
0x0000D000,
0x00000680,
0xD859647A,
0x1EBA28A3,
0x48F51145,
0x000341D3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875011,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0xAA0D4000,
0x01C3A810,
0xAA0D4000,
0x01C3A808,
0xAA0D4000,
0x01C3A810,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x0002A000,
0x0001E400,
0x5506A000,
0x00E1D404,
0x00000000,
0xC880090C,
0x00003001,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA04,
0x2A835000,
0x0070EA02,
0x2A835000,
0x0070EA04,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00002000,
0x80000000,
0x00104120,
0x00000200,
0xAC055F80,
0xFFFFFFFF,
0x14F3690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xBA28A3D8,
0xF511451E,
0x0341D348,
0x821A0000,
0x0000D000,
0x00000680,
0xD859647A,
0x1EBA28A3,
0x48F51145,
0x000341D3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875011,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0xAA0D4000,
0x01C3A810,
0xAA0D4000,
0x01C3A808,
0xAA0D4000,
0x01C3A810,
0x00040100,
0x00000800,
0x00000000,
0x00001208,
0x00482000,
0x00008000,
0x00000000,
0x00410482,
0x0006A000,
0x0001B400,
0x00020000,
0x00000400,
0x00020080,
0x00000400,
0x5506A000,
0x00E1D404,
0x00000000,
0x0000090C,
0x00000010,
0x90400000,
0x00000000,
0x2020C243,
0x2A835000,
0x0070EA04,
0x2A835000,
0x0070EA02,
0x2A835000,
0x0070EA04,
0x00010040,
0x00000200,
0x00000000,
0x00000482,
0x00120800,
0x00400000,
0x80000000,
0x00104120,
0x00000200,
0xAC055F80,
0xFFFFFFFF,
0x14F1690D,
0x1A041414,
0x00D00000,
0x14864000,
0x59647A05,
0xBA28A3D8,
0xF511451E,
0x0341D348,
0x821A0000,
0x0000D000,
0x00000680,
0xD859647A,
0x1EBA28A3,
0x48F51145,
0x000341D3,
0x00080200,
0x00001000,
0x00080200,
0x00001000,
0x000A8000,
0x00075000,
0x541A8000,
0x03875011,
0x10000000,
0x00000000,
0x0080C000,
0x41000000,
0x04000002,
0x00820000,
0x00481800,
0x001A1A1A,
0x085506A0,
0x0000E1D4,
0x045506A0,
0x0000E1D4,
0x085506A0,
0x8000E1D4,
0x00000200,
0x00000004,
0x04000000,
0x00000009,
0x00002410,
0x00000040,
0x41000000,
0x00002082,
0x00000350,
0x000000DA,
0x00000100,
0x40000002,
0x00000100,
0x00000002,
0x022A8350,
0x000070EA,
0x86000000,
0x08000004,
0x00000000,
0x00482000,
0x21800000,
0x00101061,
0x021541A8,
0x00003875,
0x011541A8,
0x00003875,
0x021541A8,
0x20003875,
0x00000080,
0x00000001,
0x41000000,
0x00000002,
0x00FF0904,
0x00000000,
0x90400000,
0x00000820,
0xC0000001,
0xFFD602AF,
0x86FFFFFF,
0x0A0A78B4,
0x000D020A,
0x00006800,
0x028A4320,
0xEC2CB23D,
0x8F5D1451,
0xA47A88A2,
0x0001A0E9,
0x00410D00,
0x40000068,
0x3D000003,
0x51EC2CB2,
0xA28F5D14,
0xE9A47A88,
0x000001A0,
0x00000401,
0x00000008,
0x00000401,
0x00000008,
0x00000540,
0x000003A8,
0x08AA0D40,
0x8001C3A8,
0x0000007F,
0x00000000,
0x00004060,
0xE1208000,
0x0000001F,
0x00004100,
};
#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */

9
board/altera/cyclone5-socdk/qts/iocsr_config.h
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@ -9,18 +9,9 @@
#ifndef _PRELOADER_IOCSR_CONFIG_H_
#define _PRELOADER_IOCSR_CONFIG_H_
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
#endif
#endif /*_PRELOADER_IOCSR_CONFIG_H_*/

215
board/altera/cyclone5-socdk/qts/pinmux_config.c
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@ -2,7 +2,6 @@
#include "pinmux_config.h"
#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
/* pin mux configuration data */
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
3, /* EMACIO0 */
@ -213,217 +212,3 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
0, /* USB0USEFPGA */
0 /* SPIM0USEFPGA */
};
#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
/* pin mux configuration data */
unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
0, /* EMACIO0 */
2, /* EMACIO1 */
2, /* EMACIO2 */
2, /* EMACIO3 */
2, /* EMACIO4 */
2, /* EMACIO5 */
2, /* EMACIO6 */
2, /* EMACIO7 */
2, /* EMACIO8 */
0, /* EMACIO9 */
2, /* EMACIO10 */
2, /* EMACIO11 */
2, /* EMACIO12 */
2, /* EMACIO13 */
3, /* EMACIO14 */
3, /* EMACIO15 */
3, /* EMACIO16 */
3, /* EMACIO17 */
3, /* EMACIO18 */
3, /* EMACIO19 */
3, /* FLASHIO0 */
0, /* FLASHIO1 */
3, /* FLASHIO2 */
3, /* FLASHIO3 */
0, /* FLASHIO4 */
0, /* FLASHIO5 */
0, /* FLASHIO6 */
0, /* FLASHIO7 */
0, /* FLASHIO8 */
3, /* FLASHIO9 */
3, /* FLASHIO10 */
3, /* FLASHIO11 */
3, /* GENERALIO0 */
3, /* GENERALIO1 */
3, /* GENERALIO2 */
3, /* GENERALIO3 */
3, /* GENERALIO4 */
3, /* GENERALIO5 */
3, /* GENERALIO6 */
3, /* GENERALIO7 */
3, /* GENERALIO8 */
0, /* GENERALIO9 */
0, /* GENERALIO10 */
0, /* GENERALIO11 */
0, /* GENERALIO12 */
0, /* GENERALIO13 */
0, /* GENERALIO14 */
3, /* GENERALIO15 */
3, /* GENERALIO16 */
2, /* GENERALIO17 */
2, /* GENERALIO18 */
0, /* GENERALIO19 */
0, /* GENERALIO20 */
0, /* GENERALIO21 */
0, /* GENERALIO22 */
3, /* GENERALIO23 */
3, /* GENERALIO24 */
0, /* GENERALIO25 */
0, /* GENERALIO26 */
0, /* GENERALIO27 */
0, /* GENERALIO28 */
0, /* GENERALIO29 */
0, /* GENERALIO30 */
0, /* GENERALIO31 */
0, /* MIXED1IO0 */
0, /* MIXED1IO1 */
0, /* MIXED1IO2 */
0, /* MIXED1IO3 */
0, /* MIXED1IO4 */
0, /* MIXED1IO5 */
0, /* MIXED1IO6 */
0, /* MIXED1IO7 */
0, /* MIXED1IO8 */
0, /* MIXED1IO9 */
0, /* MIXED1IO10 */
0, /* MIXED1IO11 */
0, /* MIXED1IO12 */
0, /* MIXED1IO13 */
0, /* MIXED1IO14 */
3, /* MIXED1IO15 */
3, /* MIXED1IO16 */
3, /* MIXED1IO17 */
3, /* MIXED1IO18 */
3, /* MIXED1IO19 */
3, /* MIXED1IO20 */
0, /* MIXED1IO21 */
3, /* MIXED2IO0 */
3, /* MIXED2IO1 */
3, /* MIXED2IO2 */
3, /* MIXED2IO3 */
3, /* MIXED2IO4 */
3, /* MIXED2IO5 */
3, /* MIXED2IO6 */
3, /* MIXED2IO7 */
0, /* GPLINMUX48 */
0, /* GPLINMUX49 */
0, /* GPLINMUX50 */
0, /* GPLINMUX51 */
0, /* GPLINMUX52 */
0, /* GPLINMUX53 */
0, /* GPLINMUX54 */
0, /* GPLINMUX55 */
0, /* GPLINMUX56 */
0, /* GPLINMUX57 */
0, /* GPLINMUX58 */
0, /* GPLINMUX59 */
0, /* GPLINMUX60 */
0, /* GPLINMUX61 */
0, /* GPLINMUX62 */
0, /* GPLINMUX63 */
0, /* GPLINMUX64 */
0, /* GPLINMUX65 */
0, /* GPLINMUX66 */
0, /* GPLINMUX67 */
0, /* GPLINMUX68 */
0, /* GPLINMUX69 */
0, /* GPLINMUX70 */
1, /* GPLMUX0 */
1, /* GPLMUX1 */
1, /* GPLMUX2 */
1, /* GPLMUX3 */
1, /* GPLMUX4 */
1, /* GPLMUX5 */
1, /* GPLMUX6 */
1, /* GPLMUX7 */
1, /* GPLMUX8 */
1, /* GPLMUX9 */
1, /* GPLMUX10 */
1, /* GPLMUX11 */
1, /* GPLMUX12 */
1, /* GPLMUX13 */
1, /* GPLMUX14 */
1, /* GPLMUX15 */
1, /* GPLMUX16 */
1, /* GPLMUX17 */
1, /* GPLMUX18 */
1, /* GPLMUX19 */
1, /* GPLMUX20 */
1, /* GPLMUX21 */
1, /* GPLMUX22 */
1, /* GPLMUX23 */
1, /* GPLMUX24 */
1, /* GPLMUX25 */
1, /* GPLMUX26 */
1, /* GPLMUX27 */
1, /* GPLMUX28 */
1, /* GPLMUX29 */
1, /* GPLMUX30 */
1, /* GPLMUX31 */
1, /* GPLMUX32 */
1, /* GPLMUX33 */
1, /* GPLMUX34 */
1, /* GPLMUX35 */
1, /* GPLMUX36 */
1, /* GPLMUX37 */
1, /* GPLMUX38 */
1, /* GPLMUX39 */
1, /* GPLMUX40 */
1, /* GPLMUX41 */
1, /* GPLMUX42 */
1, /* GPLMUX43 */
1, /* GPLMUX44 */
1, /* GPLMUX45 */
1, /* GPLMUX46 */
1, /* GPLMUX47 */
1, /* GPLMUX48 */
1, /* GPLMUX49 */
1, /* GPLMUX50 */
1, /* GPLMUX51 */
1, /* GPLMUX52 */
1, /* GPLMUX53 */
1, /* GPLMUX54 */
1, /* GPLMUX55 */
1, /* GPLMUX56 */
1, /* GPLMUX57 */
1, /* GPLMUX58 */
1, /* GPLMUX59 */
1, /* GPLMUX60 */
1, /* GPLMUX61 */
1, /* GPLMUX62 */
1, /* GPLMUX63 */
1, /* GPLMUX64 */
1, /* GPLMUX65 */
1, /* GPLMUX66 */
1, /* GPLMUX67 */
1, /* GPLMUX68 */
1, /* GPLMUX69 */
1, /* GPLMUX70 */
0, /* NANDUSEFPGA */
0, /* UART0USEFPGA */
0, /* RGMII1USEFPGA */
0, /* SPIS0USEFPGA */
0, /* CAN0USEFPGA */
0, /* I2C0USEFPGA */
0, /* SDMMCUSEFPGA */
0, /* QSPIUSEFPGA */
0, /* SPIS1USEFPGA */
0, /* RGMII0USEFPGA */
0, /* UART1USEFPGA */
0, /* CAN1USEFPGA */
0, /* USB1USEFPGA */
0, /* I2C3USEFPGA */
0, /* I2C2USEFPGA */
0, /* I2C1USEFPGA */
0, /* SPIM1USEFPGA */
0, /* USB0USEFPGA */
0 /* SPIM0USEFPGA */
};
#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */

14
board/altera/cyclone5-socdk/qts/sdram_config.h
Unescape View File

@ -20,19 +20,6 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
#ifdef CONFIG_SOCFPGA_ARRIA5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
#else
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
@ -44,7 +31,6 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512

20
board/altera/cyclone5-socdk/qts/sequencer_auto.h
Unescape View File

@ -19,29 +19,14 @@
#define RW_MGR_MRS2 0x04
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
#define RW_MGR_MRS1 0x03
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP1 0x7A
#else
#define RW_MGR_IDLE_LOOP1 0x7C
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
#define RW_MGR_MRS3 0x05
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP2 0x79
#else
#define RW_MGR_IDLE_LOOP2 0x7B
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_RDIMM_CMD 0x78
#else
#define RW_MGR_RDIMM_CMD 0x7A
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
@ -54,12 +39,7 @@
#define RW_MGR_GUARANTEED_WRITE 0x17
#define RW_MGR_PRECHARGE_ALL 0x12
#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_SGLE_READ 0x7C
#else
#define RW_MGR_SGLE_READ 0x7E
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MRS0_USER_MIRR 0x0C
#define RW_MGR_RETURN 0x01
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35

40
board/altera/cyclone5-socdk/qts/sequencer_auto_ac_init.h
Unescape View File

@ -5,45 +5,6 @@
*/
const uint32_t ac_rom_init[] = {
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
0x20700000,
0x20780000,
0x10080831,
0x10080930,
0x10090004,
0x100a0008,
0x100b0000,
0x10380400,
0x10080849,
0x100808c8,
0x100a0004,
0x10090010,
0x100b0000,
0x30780000,
0x38780000,
0x30780000,
0x10680000,
0x106b0000,
0x10280400,
0x10480000,
0x1c980000,
0x1c9b0000,
0x1c980008,
0x1c9b0008,
0x38f80000,
0x3cf80000,
0x38780000,
0x18180000,
0x18980000,
0x13580000,
0x135b0000,
0x13580008,
0x135b0008,
0x33780000,
0x10580008,
0x10780000
#else
0x20700000,
0x20780000,
0x10080431,
@ -80,5 +41,4 @@ const uint32_t ac_rom_init[] = {
0x33780000,
0x10580008,
0x10780000
#endif /* CONFIG_SOCFPGA_ARRIA5 */
};

132
board/altera/cyclone5-socdk/qts/sequencer_auto_inst_init.h
Unescape View File

@ -4,137 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
const u32 inst_rom_init[] = {
0x80000,
0x80680,
0x8180,
0x8200,
0x8280,
0x8300,
0x8380,
0x8100,
0x8480,
0x8500,
0x8580,
0x8600,
0x8400,
0x800,
0x8680,
0x880,
0xa680,
0x80680,
0x900,
0x80680,
0x980,
0x8680,
0x80680,
0xb68,
0xcce8,
0xae8,
0x8ce8,
0xb88,
0xec88,
0xa08,
0xac88,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x20ce0,
0x20ce0,
0x20ce0,
0x20ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x60e80,
0x61080,
0x61080,
0x61080,
0xa680,
0x8680,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x30ce0,
0x30ce0,
0x30ce0,
0x30ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x70e80,
0x71080,
0x71080,
0x71080,
0xa680,
0x8680,
0x80680,
0x1158,
0x6d8,
0x80680,
0x1168,
0x7e8,
0x7e8,
0x87e8,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x1168,
0x7e8,
0x7e8,
0xa7e8,
0x80680,
0x40e88,
0x41088,
0x41088,
0x41088,
0x40f68,
0x410e8,
0x410e8,
0x410e8,
0xa680,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x41008,
0x41088,
0x41088,
0x41088,
0x1100,
0xc680,
0x8680,
0xe680,
0x80680,
0x0,
0x8000,
0xa000,
0xc000,
0x80000,
0x80,
0x8080,
0xa080,
0xc080,
0x80080,
0x9180,
0x8680,
0xa680,
0x80680,
0x40f08,
0x80680
};
#else
const u32 inst_rom_init[] = {
0x80000,
0x80680,
@ -265,4 +134,3 @@ const u32 inst_rom_init[] = {
0x40f08,
0x80680
};
#endif /* CONFIG_SOCFPGA_ARRIA5 */

35
board/altera/cyclone5-socdk/qts/sequencer_defines.h
Unescape View File

@ -12,39 +12,20 @@
#define AC_ROM_MR2_MIRR 0000000010000
#define AC_ROM_MR3_MIRR 0000000000000
#define AC_ROM_MR0_CALIB
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
#define AC_ROM_MR0_DLL_RESET 0100100110000
#define AC_ROM_MR0_MIRR 0100001001001
#define AC_ROM_MR0 0100000110001
#else
#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
#define AC_ROM_MR0_DLL_RESET 0010100110000
#define AC_ROM_MR0_MIRR 0010001001001
#define AC_ROM_MR0 0010000110001
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AC_ROM_MR1 0000000000100
#define AC_ROM_MR2 0000000001000
#define AC_ROM_MR3 0000000000000
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AFI_CLK_FREQ 534
#else
#define AFI_CLK_FREQ 401
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AFI_RATE_RATIO 1
#define AVL_CLK_FREQ 67
#define BFM_MODE 0
#define BURST2 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define CALIB_LFIFO_OFFSET 8
#define CALIB_VFIFO_OFFSET 6
#else
#define CALIB_LFIFO_OFFSET 7
#define CALIB_VFIFO_OFFSET 5
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define GUARANTEED_READ_BRINGUP_TEST 0
@ -54,23 +35,12 @@
#define HR_DDIO_OUT_HAS_THREE_REGS 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DELAY_PER_OPA_TAP 234
#else
#define IO_DELAY_PER_OPA_TAP 312
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DM_OUT_RESERVE 0
#define IO_DQDQS_OUT_PHASE_MAX 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DQS_EN_DELAY_MAX 15
#define IO_DQS_EN_DELAY_OFFSET 16
#else
#define IO_DQS_EN_DELAY_MAX 31
#define IO_DQS_EN_DELAY_OFFSET 0
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DQS_EN_PHASE_MAX 7
#define IO_DQS_IN_DELAY_MAX 31
#define IO_DQS_IN_RESERVE 4
@ -84,12 +54,7 @@
#define MAX_LATENCY_COUNT_WIDTH 5
#define MEM_ADDR_WIDTH 13
#define READ_VALID_FIFO_SIZE 16
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#else
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_ADDRESS_WIDTH 15
#define RW_MGR_MEM_BANK_WIDTH 3

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