@ -18,7 +18,6 @@
# define VTP_CTRL_READY (0x1 << 5)
# define VTP_CTRL_ENABLE (0x1 << 6)
# define VTP_CTRL_START_EN (0x1)
# define PHY_DLL_LOCK_DIFF 0x0
# define DDR_CKE_CTRL_NORMAL 0x1
# define PHY_EN_DYN_PWRDN (0x1 << 20)
@ -29,7 +28,6 @@
# define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
# define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
# define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
# define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
# define MT47H128M16RT25E_RATIO 0x80
# define MT47H128M16RT25E_INVERT_CLKOUT 0x00
# define MT47H128M16RT25E_RD_DQS 0x12
@ -38,7 +36,6 @@
# define MT47H128M16RT25E_PHY_GATELVL 0x00
# define MT47H128M16RT25E_PHY_WR_DATA 0x40
# define MT47H128M16RT25E_PHY_FIFO_WE 0x80
# define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
# define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
@ -49,7 +46,6 @@
# define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
# define MT41J128MJT125_EMIF_SDREF 0x0000093B
# define MT41J128MJT125_ZQ_CFG 0x50074BE4
# define MT41J128MJT125_DLL_LOCK_DIFF 0x1
# define MT41J128MJT125_RATIO 0x40
# define MT41J128MJT125_INVERT_CLKOUT 0x1
# define MT41J128MJT125_RD_DQS 0x3B
@ -72,7 +68,6 @@
# define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
# define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
# define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
# define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
# define MT41J256M8HX15E_RATIO 0x40
# define MT41J256M8HX15E_INVERT_CLKOUT 0x1
# define MT41J256M8HX15E_RD_DQS 0x3B
@ -89,7 +84,6 @@
# define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
# define MT41K256M16HA125E_EMIF_SDREF 0xC30
# define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
# define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
# define MT41K256M16HA125E_RATIO 0x80
# define MT41K256M16HA125E_INVERT_CLKOUT 0x0
# define MT41K256M16HA125E_RD_DQS 0x38
@ -106,7 +100,6 @@
# define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
# define MT41J512M8RH125_EMIF_SDREF 0x0000093B
# define MT41J512M8RH125_ZQ_CFG 0x50074BE4
# define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
# define MT41J512M8RH125_RATIO 0x80
# define MT41J512M8RH125_INVERT_CLKOUT 0x0
# define MT41J512M8RH125_RD_DQS 0x3B
@ -123,7 +116,6 @@
# define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
# define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
# define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
# define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
# define K4B2G1646EBIH9_RATIO 0x80
# define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
# define K4B2G1646EBIH9_RD_DQS 0x35
@ -155,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
struct ddr_cmd_regs {
unsigned int resv0 [ 7 ] ;
unsigned int cm0csratio ; /* offset 0x01C */
unsigned int resv1 [ 2 ] ;
unsigned int cm0dldiff ; /* offset 0x028 */
unsigned int resv1 [ 3 ] ;
unsigned int cm0iclkout ; /* offset 0x02C */
unsigned int resv2 [ 8 ] ;
unsigned int cm1csratio ; /* offset 0x050 */
unsigned int resv3 [ 2 ] ;
unsigned int cm1dldiff ; /* offset 0x05C */
unsigned int resv3 [ 3 ] ;
unsigned int cm1iclkout ; /* offset 0x060 */
unsigned int resv4 [ 8 ] ;
unsigned int cm2csratio ; /* offset 0x084 */
unsigned int resv5 [ 2 ] ;
unsigned int cm2dldiff ; /* offset 0x090 */
unsigned int resv5 [ 3 ] ;
unsigned int cm2iclkout ; /* offset 0x094 */
unsigned int resv6 [ 3 ] ;
} ;
@ -203,24 +192,21 @@ struct ddr_regs {
unsigned int cm0configclk ; /* offset 0x010 */
unsigned int resv1 [ 2 ] ;
unsigned int cm0csratio ; /* offset 0x01C */
unsigned int resv2 [ 2 ] ;
unsigned int cm0dldiff ; /* offset 0x028 */
unsigned int resv2 [ 3 ] ;
unsigned int cm0iclkout ; /* offset 0x02C */
unsigned int resv3 [ 4 ] ;
unsigned int cm1config ; /* offset 0x040 */
unsigned int cm1configclk ; /* offset 0x044 */
unsigned int resv4 [ 2 ] ;
unsigned int cm1csratio ; /* offset 0x050 */
unsigned int resv5 [ 2 ] ;
unsigned int cm1dldiff ; /* offset 0x05C */
unsigned int resv5 [ 3 ] ;
unsigned int cm1iclkout ; /* offset 0x060 */
unsigned int resv6 [ 4 ] ;
unsigned int cm2config ; /* offset 0x074 */
unsigned int cm2configclk ; /* offset 0x078 */
unsigned int resv7 [ 2 ] ;
unsigned int cm2csratio ; /* offset 0x084 */
unsigned int resv8 [ 2 ] ;
unsigned int cm2dldiff ; /* offset 0x090 */
unsigned int resv8 [ 3 ] ;
unsigned int cm2iclkout ; /* offset 0x094 */
unsigned int resv9 [ 12 ] ;
unsigned int dt0rdsratio0 ; /* offset 0x0C8 */
@ -249,17 +235,14 @@ struct cmd_control {
unsigned long cmd0csratio ;
unsigned long cmd0csforce ;
unsigned long cmd0csdelay ;
unsigned long cmd0dldiff ;
unsigned long cmd0iclkout ;
unsigned long cmd1csratio ;
unsigned long cmd1csforce ;
unsigned long cmd1csdelay ;
unsigned long cmd1dldiff ;
unsigned long cmd1iclkout ;
unsigned long cmd2csratio ;
unsigned long cmd2csforce ;
unsigned long cmd2csdelay ;
unsigned long cmd2dldiff ;
unsigned long cmd2iclkout ;
} ;
@ -273,8 +256,6 @@ struct ddr_data {
unsigned long datagiratio0 ;
unsigned long datafwsratio0 ;
unsigned long datawrsratio0 ;
unsigned long datauserank0delay ;
unsigned long datadldiff0 ;
} ;
/**