@ -73,6 +73,9 @@ ENDPROC(smp_kick_all_cpus)
ENTRY( l o w l e v e l _ i n i t )
mov x29 , l r / * S a v e L R * /
switch_ e l x1 , 1 f , 1 0 0 f , 1 0 0 f / * s k i p i f n o t i n E L 3 * /
1 :
# ifdef C O N F I G _ F S L _ L S C H 3
/* Set Wuo bit for RN-I 20 */
@ -193,6 +196,7 @@ ENTRY(lowlevel_init)
# endif
# endif
100 :
branch_ i f _ m a s t e r x0 , x1 , 2 f
# if d e f i n e d ( C O N F I G _ M P ) & & d e f i n e d ( C O N F I G _ A R M V 8 _ M U L T I E N T R Y )
@ -201,6 +205,8 @@ ENTRY(lowlevel_init)
# endif
2 :
switch_ e l x1 , 1 f , 1 0 0 f , 1 0 0 f / * s k i p i f n o t i n E L 3 * /
1 :
# ifdef C O N F I G _ F S L _ T Z P C _ B P 1 4 7
/* Set Non Secure access for all devices protected via TZPC */
ldr x1 , =TZPCDECPROT_0_SET_BASE / * D e c o d e P r o t e c t i o n - 0 S e t R e g * /
@ -266,8 +272,11 @@ ENTRY(lowlevel_init)
isb
dsb s y
# endif
100 :
1 :
# ifdef C O N F I G _ A R C H _ L S 1 0 4 6 A
switch_ e l x1 , 1 f , 1 0 0 f , 1 0 0 f / * s k i p i f n o t i n E L 3 * /
1 :
/* Initialize the L2 RAM latency */
mrs x1 , S 3 _ 1 _ c11 _ c0 _ 2
mov x0 , #0x1C7
@ -279,6 +288,7 @@ ENTRY(lowlevel_init)
orr x1 , x1 , #0x80
msr S 3 _ 1 _ c11 _ c0 _ 2 , x1
isb
100 :
# endif
# if d e f i n e d ( C O N F I G _ F S L _ L S C H 2 ) & & ! d e f i n e d ( C O N F I G _ S P L _ B U I L D )
@ -379,11 +389,14 @@ ENTRY(__asm_flush_l3_dcache)
/ *
* Return s t a t u s i n x0
* success 0
* tmeout 1 f o r s e t t i n g S F O N L Y , 2 f o r F A M , 3 f o r b o t h
* ti meout 1 f o r s e t t i n g S F O N L Y , 2 f o r F A M , 3 f o r b o t h
* /
mov x29 , l r
mov x8 , #0
switch_ e l x0 , 1 f , 1 0 0 f , 1 0 0 f / * s k i p i f n o t i n E L 3 * /
1 :
dsb s y
mov x0 , #0x1 / * H N F P S T A T _ S F O N L Y * /
bl h n f _ s e t _ p s t a t e
@ -401,6 +414,7 @@ ENTRY(__asm_flush_l3_dcache)
bl h n f _ p s t a t e _ p o l l
cbz x0 , 1 f
add x8 , x8 , #0x2
100 :
1 :
mov x0 , x8
mov l r , x29