The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>master
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/*
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* Sunxi A31 Power Management Unit |
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* |
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* (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> |
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* http://linux-sunxi.org
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* |
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* Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work |
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* |
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* (C) Copyright 2006-2013 |
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
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* Berg Xing <bergxing@allwinnertech.com> |
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* Tom Cubie <tangliang@allwinnertech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/p2wi.h> |
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#include <asm/arch/prcm.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> |
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void p2wi_init(void) |
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{ |
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; |
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/* Enable p2wi and PIO clk, and de-assert their resets */ |
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prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); |
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sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK); |
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sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA); |
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/* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ |
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writel(P2WI_CTRL_RESET, &p2wi->ctrl); |
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sdelay(0x100); |
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writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8), |
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&p2wi->cc); |
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} |
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int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) |
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{ |
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; |
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unsigned long tmo = timer_get_us() + 1000000; |
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writel(P2WI_PM_DEV_ADDR(slave_addr) | |
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P2WI_PM_CTRL_ADDR(ctrl_reg) | |
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P2WI_PM_INIT_DATA(init_data) | |
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P2WI_PM_INIT_SEND, |
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&p2wi->pm); |
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while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) { |
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if (timer_get_us() > tmo) |
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return -ETIME; |
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} |
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return 0; |
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} |
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static int p2wi_await_trans(void) |
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{ |
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; |
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unsigned long tmo = timer_get_us() + 1000000; |
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int ret; |
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u8 reg; |
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while (1) { |
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reg = readl(&p2wi->status); |
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if (reg & P2WI_STAT_TRANS_ERR) { |
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ret = -EIO; |
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break; |
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} |
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if (reg & P2WI_STAT_TRANS_DONE) { |
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ret = 0; |
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break; |
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} |
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if (timer_get_us() > tmo) { |
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ret = -ETIME; |
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break; |
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} |
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} |
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writel(reg, &p2wi->status); /* Clear status bits */ |
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return ret; |
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} |
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int p2wi_read(const u8 addr, u8 *data) |
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{ |
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; |
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int ret; |
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writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); |
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writel(P2WI_DATA_NUM_BYTES(1) | |
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P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes); |
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writel(P2WI_STAT_TRANS_DONE, &p2wi->status); |
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writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); |
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ret = p2wi_await_trans(); |
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*data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK; |
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return ret; |
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} |
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int p2wi_write(const u8 addr, u8 data) |
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{ |
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struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; |
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writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); |
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writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); |
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writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes); |
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writel(P2WI_STAT_TRANS_DONE, &p2wi->status); |
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writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl); |
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return p2wi_await_trans(); |
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} |
@ -0,0 +1,140 @@ |
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/*
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* Sunxi platform Push-Push i2c register definition. |
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* |
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* (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> |
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* http://linux-sunxi.org
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* |
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* (c)Copyright 2006-2013 |
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com> |
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* Berg Xing <bergxing@allwinnertech.com> |
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* Tom Cubie <tangliang@allwinnertech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SUNXI_P2WI_H |
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#define _SUNXI_P2WI_H |
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#include <linux/types.h> |
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#define P2WI_CTRL_RESET (0x1 << 0) |
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#define P2WI_CTRL_IRQ_EN (0x1 << 1) |
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#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) |
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#define P2WI_CTRL_TRANS_START (0x1 << 7) |
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#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) |
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#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) |
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#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) |
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#define P2WI_CC_CLK_DIV(n) \ |
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__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) |
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#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) |
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#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) |
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#define P2WI_IRQ_TRANS_DONE (0x1 << 0) |
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#define P2WI_IRQ_TRANS_ERR (0x1 << 1) |
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#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) |
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#define P2WI_STAT_TRANS_DONE (0x1 << 0) |
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#define P2WI_STAT_TRANS_ERR (0x1 << 1) |
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#define P2WI_STAT_LOAD_BUSY (0x1 << 2) |
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#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) |
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#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) |
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#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 |
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#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 |
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#define P2WI_STAT_TRANS_ERR_BYTE_1 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) |
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#define P2WI_STAT_TRANS_ERR_BYTE_2 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) |
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#define P2WI_STAT_TRANS_ERR_BYTE_3 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) |
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#define P2WI_STAT_TRANS_ERR_BYTE_4 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) |
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#define P2WI_STAT_TRANS_ERR_BYTE_5 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) |
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#define P2WI_STAT_TRANS_ERR_BYTE_6 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) |
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#define P2WI_STAT_TRANS_ERR_BYTE_7 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) |
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#define P2WI_STAT_TRANS_ERR_BYTE_8 \ |
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) |
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#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) |
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#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) |
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#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) |
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#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) |
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#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) |
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#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) |
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#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) |
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#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) |
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#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) |
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#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) |
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#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) |
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#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) |
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#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) |
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#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) |
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#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) |
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#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) |
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#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) |
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#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) |
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#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) |
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#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) |
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#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) |
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#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) |
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#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) |
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#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) |
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#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) |
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#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) |
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#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) |
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#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) |
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#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) |
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#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) |
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#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) |
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#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) |
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#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) |
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#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) |
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#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) |
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#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) |
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#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) |
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#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) |
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#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) |
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#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) |
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#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) |
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#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) |
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#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) |
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#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) |
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#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) |
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#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) |
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#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) |
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#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) |
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#define P2WI_PM_INIT_SEND (0x1 << 31) |
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struct sunxi_p2wi_reg { |
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u32 ctrl; /* 0x00 control */ |
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u32 cc; /* 0x04 clock control */ |
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u32 irq; /* 0x08 interrupt */ |
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u32 status; /* 0x0c status */ |
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u32 dataddr0; /* 0x10 data address 0 */ |
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u32 dataddr1; /* 0x14 data address 1 */ |
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u32 numbytes; /* 0x18 num bytes */ |
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u32 data0; /* 0x1c data buffer 0 */ |
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u32 data1; /* 0x20 data buffer 1 */ |
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u32 linectrl; /* 0x24 line control */ |
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u32 pm; /* 0x28 power management */ |
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}; |
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void p2wi_init(void); |
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int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); |
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int p2wi_read(const u8 addr, u8 *data); |
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int p2wi_write(const u8 addr, u8 data); |
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#endif /* _SUNXI_P2WI_H */ |
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