wdenk
23 years ago
parent
2acb895783
commit
3b759bd63b
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/*
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* PowerPC memory management structures |
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*/ |
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#ifndef _PPC_MMU_H_ |
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#define _PPC_MMU_H_ |
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#include <linux/config.h> |
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#ifndef __ASSEMBLY__ |
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/* Hardware Page Table Entry */ |
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typedef struct _PTE { |
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#ifdef CONFIG_PPC64BRIDGE |
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unsigned long long vsid:52; |
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unsigned long api:5; |
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unsigned long :5; |
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unsigned long h:1; |
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unsigned long v:1; |
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unsigned long long rpn:52; |
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#else /* CONFIG_PPC64BRIDGE */ |
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unsigned long v:1; /* Entry is valid */ |
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unsigned long vsid:24; /* Virtual segment identifier */ |
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unsigned long h:1; /* Hash algorithm indicator */ |
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unsigned long api:6; /* Abbreviated page index */ |
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unsigned long rpn:20; /* Real (physical) page number */ |
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#endif /* CONFIG_PPC64BRIDGE */ |
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unsigned long :3; /* Unused */ |
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unsigned long r:1; /* Referenced */ |
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unsigned long c:1; /* Changed */ |
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unsigned long w:1; /* Write-thru cache mode */ |
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unsigned long i:1; /* Cache inhibited */ |
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unsigned long m:1; /* Memory coherence */ |
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unsigned long g:1; /* Guarded */ |
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unsigned long :1; /* Unused */ |
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unsigned long pp:2; /* Page protection */ |
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} PTE; |
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/* Values for PP (assumes Ks=0, Kp=1) */ |
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#define PP_RWXX 0 /* Supervisor read/write, User none */ |
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#define PP_RWRX 1 /* Supervisor read/write, User read */ |
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */ |
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#define PP_RXRX 3 /* Supervisor read, User read */ |
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/* Segment Register */ |
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typedef struct _SEGREG { |
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unsigned long t:1; /* Normal or I/O type */ |
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unsigned long ks:1; /* Supervisor 'key' (normally 0) */ |
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unsigned long kp:1; /* User 'key' (normally 1) */ |
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unsigned long n:1; /* No-execute */ |
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unsigned long :4; /* Unused */ |
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unsigned long vsid:24; /* Virtual Segment Identifier */ |
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} SEGREG; |
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/* Block Address Translation (BAT) Registers */ |
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typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ |
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unsigned long bepi:15; /* Effective page index (virtual address) */ |
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unsigned long :8; /* unused */ |
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unsigned long w:1; |
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unsigned long i:1; /* Cache inhibit */ |
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unsigned long m:1; /* Memory coherence */ |
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unsigned long ks:1; /* Supervisor key (normally 0) */ |
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unsigned long kp:1; /* User key (normally 1) */ |
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unsigned long pp:2; /* Page access protections */ |
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} P601_BATU; |
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typedef struct _BATU { /* Upper part of BAT (all except 601) */ |
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#ifdef CONFIG_PPC64BRIDGE |
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unsigned long long bepi:47; |
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#else /* CONFIG_PPC64BRIDGE */ |
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unsigned long bepi:15; /* Effective page index (virtual address) */ |
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#endif /* CONFIG_PPC64BRIDGE */ |
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unsigned long :4; /* Unused */ |
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unsigned long bl:11; /* Block size mask */ |
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unsigned long vs:1; /* Supervisor valid */ |
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unsigned long vp:1; /* User valid */ |
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} BATU; |
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typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ |
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unsigned long brpn:15; /* Real page index (physical address) */ |
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unsigned long :10; /* Unused */ |
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unsigned long v:1; /* Valid bit */ |
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unsigned long bl:6; /* Block size mask */ |
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} P601_BATL; |
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typedef struct _BATL { /* Lower part of BAT (all except 601) */ |
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#ifdef CONFIG_PPC64BRIDGE |
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unsigned long long brpn:47; |
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#else /* CONFIG_PPC64BRIDGE */ |
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unsigned long brpn:15; /* Real page index (physical address) */ |
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#endif /* CONFIG_PPC64BRIDGE */ |
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unsigned long :10; /* Unused */ |
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unsigned long w:1; /* Write-thru cache */ |
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unsigned long i:1; /* Cache inhibit */ |
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unsigned long m:1; /* Memory coherence */ |
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unsigned long g:1; /* Guarded (MBZ in IBAT) */ |
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unsigned long :1; /* Unused */ |
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unsigned long pp:2; /* Page access protections */ |
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} BATL; |
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typedef struct _BAT { |
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BATU batu; /* Upper register */ |
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BATL batl; /* Lower register */ |
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} BAT; |
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typedef struct _P601_BAT { |
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P601_BATU batu; /* Upper register */ |
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P601_BATL batl; /* Lower register */ |
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} P601_BAT; |
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/*
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* Simulated two-level MMU. This structure is used by the kernel |
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* to keep track of MMU mappings and is used to update/maintain |
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* the hardware HASH table which is really a cache of mappings. |
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* |
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* The simulated structures mimic the hardware available on other |
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* platforms, notably the 80x86 and 680x0. |
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*/ |
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typedef struct _pte { |
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unsigned long page_num:20; |
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unsigned long flags:12; /* Page flags (some unused bits) */ |
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} pte; |
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#define PD_SHIFT (10+12) /* Page directory */ |
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#define PD_MASK 0x02FF |
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#define PT_SHIFT (12) /* Page Table */ |
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#define PT_MASK 0x02FF |
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#define PG_SHIFT (12) /* Page Entry */ |
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/* MMU context */ |
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typedef struct _MMU_context { |
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SEGREG segs[16]; /* Segment registers */ |
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pte **pmap; /* Two-level page-map structure */ |
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} MMU_context; |
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extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ |
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extern void _tlbia(void); /* invalidate all TLB entries */ |
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typedef enum { |
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IBAT0 = 0, IBAT1, IBAT2, IBAT3, |
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DBAT0, DBAT1, DBAT2, DBAT3 |
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} ppc_bat_t; |
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extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); |
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extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); |
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#endif /* __ASSEMBLY__ */ |
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/* Block size masks */ |
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#define BL_128K 0x000 |
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#define BL_256K 0x001 |
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#define BL_512K 0x003 |
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#define BL_1M 0x007 |
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#define BL_2M 0x00F |
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#define BL_4M 0x01F |
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#define BL_8M 0x03F |
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#define BL_16M 0x07F |
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#define BL_32M 0x0FF |
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#define BL_64M 0x1FF |
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#define BL_128M 0x3FF |
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#define BL_256M 0x7FF |
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/* BAT Access Protection */ |
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#define BPP_XX 0x00 /* No access */ |
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#define BPP_RX 0x01 /* Read only */ |
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#define BPP_RW 0x02 /* Read/write */ |
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/* Used to set up SDR1 register */ |
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#define HASH_TABLE_SIZE_64K 0x00010000 |
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#define HASH_TABLE_SIZE_128K 0x00020000 |
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#define HASH_TABLE_SIZE_256K 0x00040000 |
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#define HASH_TABLE_SIZE_512K 0x00080000 |
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#define HASH_TABLE_SIZE_1M 0x00100000 |
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#define HASH_TABLE_SIZE_2M 0x00200000 |
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#define HASH_TABLE_SIZE_4M 0x00400000 |
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#define HASH_TABLE_MASK_64K 0x000 |
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#define HASH_TABLE_MASK_128K 0x001 |
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#define HASH_TABLE_MASK_256K 0x003 |
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#define HASH_TABLE_MASK_512K 0x007 |
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#define HASH_TABLE_MASK_1M 0x00F |
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#define HASH_TABLE_MASK_2M 0x01F |
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#define HASH_TABLE_MASK_4M 0x03F |
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/* Control/status registers for the MPC8xx.
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* A write operation to these registers causes serialized access. |
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* During software tablewalk, the registers used perform mask/shift-add |
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* operations when written/read. A TLB entry is created when the Mx_RPN |
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* is written, and the contents of several registers are used to |
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* create the entry. |
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*/ |
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#define MI_CTR 784 /* Instruction TLB control register */ |
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#define MI_GPM 0x80000000 /* Set domain manager mode */ |
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#define MI_PPM 0x40000000 /* Set subpage protection */ |
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#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
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#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
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#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
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#define MI_RESETVAL 0x00000000 /* Value of register at reset */ |
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1. |
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*/ |
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#define MI_AP 786 |
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#define MI_Ks 0x80000000 /* Should not be set */ |
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#define MI_Kp 0x40000000 /* Should always be set */ |
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MI_RPN is written, bits in |
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* this register are used to create the TLB entry. |
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*/ |
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#define MI_EPN 787 |
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#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ |
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#define MI_EVALID 0x00000200 /* Entry is valid */ |
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#define MI_ASIDMASK 0x0000000f /* ASID match value */ |
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/* Reset value is undefined */ |
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the instruction TLB, it contains bits that get loaded into the |
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* TLB entry when the MI_RPN is written. |
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*/ |
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#define MI_TWC 789 |
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#define MI_APG 0x000001e0 /* Access protection group (0) */ |
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#define MI_GUARDED 0x00000010 /* Guarded storage */ |
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#define MI_PSMASK 0x0000000c /* Mask of page size bits */ |
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#define MI_PS8MEG 0x0000000c /* 8M page size */ |
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#define MI_PS512K 0x00000004 /* 512K page size */ |
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#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
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#define MI_SVALID 0x00000001 /* Segment entry is valid */ |
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/* Reset value is undefined */ |
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the instruction TLB, using |
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* additional information from the MI_EPN, and MI_TWC registers. |
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*/ |
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#define MI_RPN 790 |
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/* Define an RPN value for mapping kernel memory to large virtual
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* pages for boot initialization. This has real page number of 0, |
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* large page size, shared page, cache enabled, and valid. |
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* Also mark all subpages valid and write access. |
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*/ |
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#define MI_BOOTINIT 0x000001fd |
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#define MD_CTR 792 /* Data TLB control register */ |
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#define MD_GPM 0x80000000 /* Set domain manager mode */ |
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#define MD_PPM 0x40000000 /* Set subpage protection */ |
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#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ |
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#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
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#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ |
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#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
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#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
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#define MD_RESETVAL 0x04000000 /* Value of register at reset */ |
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#define M_CASID 793 /* Address space ID (context) to match */ |
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#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ |
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/* These are the Ks and Kp from the PowerPC books. For proper operation,
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* Ks = 0, Kp = 1. |
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*/ |
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#define MD_AP 794 |
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#define MD_Ks 0x80000000 /* Should not be set */ |
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#define MD_Kp 0x40000000 /* Should always be set */ |
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/* The effective page number register. When read, contains the information
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* about the last instruction TLB miss. When MD_RPN is written, bits in |
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* this register are used to create the TLB entry. |
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*/ |
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#define MD_EPN 795 |
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#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ |
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#define MD_EVALID 0x00000200 /* Entry is valid */ |
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#define MD_ASIDMASK 0x0000000f /* ASID match value */ |
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/* Reset value is undefined */ |
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/* The pointer to the base address of the first level page table.
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* During a software tablewalk, reading this register provides the address |
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* of the entry associated with MD_EPN. |
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*/ |
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#define M_TWB 796 |
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#define M_L1TB 0xfffff000 /* Level 1 table base address */ |
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#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ |
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/* Reset value is undefined */ |
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/* A "level 1" or "segment" or whatever you want to call it register.
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* For the data TLB, it contains bits that get loaded into the TLB entry |
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* when the MD_RPN is written. It is also provides the hardware assist |
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* for finding the PTE address during software tablewalk. |
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*/ |
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#define MD_TWC 797 |
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#define MD_L2TB 0xfffff000 /* Level 2 table base address */ |
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#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ |
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#define MD_APG 0x000001e0 /* Access protection group (0) */ |
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#define MD_GUARDED 0x00000010 /* Guarded storage */ |
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#define MD_PSMASK 0x0000000c /* Mask of page size bits */ |
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#define MD_PS8MEG 0x0000000c /* 8M page size */ |
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#define MD_PS512K 0x00000004 /* 512K page size */ |
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#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
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#define MD_WT 0x00000002 /* Use writethrough page attribute */ |
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#define MD_SVALID 0x00000001 /* Segment entry is valid */ |
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/* Reset value is undefined */ |
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/* Real page number. Defined by the pte. Writing this register
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* causes a TLB entry to be created for the data TLB, using |
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* additional information from the MD_EPN, and MD_TWC registers. |
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*/ |
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#define MD_RPN 798 |
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/* This is a temporary storage register that could be used to save
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* a processor working register during a tablewalk. |
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*/ |
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#define M_TW 799 |
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/*
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* At present, all PowerPC 400-class processors share a similar TLB |
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* architecture. The instruction and data sides share a unified, |
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* 64-entry, fully-associative TLB which is maintained totally under |
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* software control. In addition, the instruction side has a |
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* hardware-managed, 4-entry, fully- associative TLB which serves as a |
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* first level to the shared TLB. These two TLBs are known as the UTLB |
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* and ITLB, respectively. |
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*/ |
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#define PPC4XX_TLB_SIZE 64 |
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/*
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* TLB entries are defined by a "high" tag portion and a "low" data |
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* portion. On all architectures, the data portion is 32-bits. |
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* |
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* TLB entries are managed entirely under software control by reading, |
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* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx |
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* instructions. |
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*/ |
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#define TLB_LO 1 |
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#define TLB_HI 0 |
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#define TLB_DATA TLB_LO |
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#define TLB_TAG TLB_HI |
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/* Tag portion */ |
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#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
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#define TLB_PAGESZ_MASK 0x00000380 |
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#define TLB_PAGESZ(x) (((x) & 0x7) << 7) |
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#define PAGESZ_1K 0 |
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#define PAGESZ_4K 1 |
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#define PAGESZ_16K 2 |
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#define PAGESZ_64K 3 |
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#define PAGESZ_256K 4 |
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#define PAGESZ_1M 5 |
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#define PAGESZ_4M 6 |
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#define PAGESZ_16M 7 |
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#define TLB_VALID 0x00000040 /* Entry is valid */ |
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/* Data portion */ |
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#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
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#define TLB_PERM_MASK 0x00000300 |
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#define TLB_EX 0x00000200 /* Instruction execution allowed */ |
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#define TLB_WR 0x00000100 /* Writes permitted */ |
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#define TLB_ZSEL_MASK 0x000000F0 |
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#define TLB_ZSEL(x) (((x) & 0xF) << 4) |
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#define TLB_ATTR_MASK 0x0000000F |
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#define TLB_W 0x00000008 /* Caching is write-through */ |
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#define TLB_I 0x00000004 /* Caching is inhibited */ |
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#define TLB_M 0x00000002 /* Memory is coherent */ |
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#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ |
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#endif /* _PPC_MMU_H_ */ |
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