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@ -163,8 +163,6 @@ struct diu_addr { |
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unsigned int offset; |
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}; |
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#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */ |
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/*
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* Modes of operation of DIU |
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*/ |
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@ -197,7 +195,7 @@ static void disable_lcdc(void); |
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static int fsl_diu_enable_panel(struct fb_info *info); |
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static int fsl_diu_disable_panel(struct fb_info *info); |
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static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); |
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static u32 get_busfreq(void); |
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void diu_set_pixel_clock(unsigned int pixclock); |
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int fsl_diu_init(int xres, |
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unsigned int pixel_format, |
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@ -209,15 +207,11 @@ int fsl_diu_init(int xres, |
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struct diu *hw; |
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struct fb_info *info = &fsl_fb_info; |
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struct fb_var_screeninfo *var = &info->var; |
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volatile immap_t *immap = (immap_t *)CFG_IMMR; |
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volatile ccsr_gur_t *gur = &immap->im_gur; |
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volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; |
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unsigned char *gamma_table_base; |
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unsigned int i, j; |
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unsigned long speed_ccb, temp, pixval; |
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DPRINTF("Enter fsl_diu_init\n"); |
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dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET); |
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dr.diu_reg = (struct diu *) (CFG_DIU_ADDR); |
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hw = (struct diu *) dr.diu_reg; |
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disable_lcdc(); |
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@ -336,30 +330,15 @@ int fsl_diu_init(int xres, |
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var->vsync_len << 11 | /* PW_V */ |
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var->lower_margin; /* FP_V */ |
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/* Pixel Clock configuration */ |
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DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq()); |
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speed_ccb = get_busfreq(); |
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DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); |
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temp = 1; |
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temp *= 1000000000; |
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temp /= var->pixclock; |
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temp *= 1000; |
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pixval = speed_ccb / temp; |
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DPRINTF("DIU pixval = %lu\n", pixval); |
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hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ |
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hw->thresholds = 0x00037800; /* The Thresholds */ |
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hw->int_status = 0; /* INTERRUPT STATUS */ |
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hw->int_mask = 0; /* INT MASK */ |
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hw->plut = 0x01F5F666; |
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/* Modify PXCLK in GUTS CLKDVDR */ |
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DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); |
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temp = *guts_clkdvdr & 0x2000FFFF; |
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*guts_clkdvdr = temp; /* turn off clock */ |
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*guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); |
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DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); |
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/* Pixel Clock configuration */ |
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DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); |
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diu_set_pixel_clock(var->pixclock); |
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fb_initialized = 1; |
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@ -466,14 +445,6 @@ static void disable_lcdc(void) |
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} |
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} |
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static u32 get_busfreq(void) |
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{ |
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u32 fs_busfreq = 0; |
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fs_busfreq = get_bus_freq(0); |
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return fs_busfreq; |
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} |
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/*
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* Align to 64-bit(8-byte), 32-byte, etc. |
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*/ |
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