The board includes: * ADSP-BF561 rev. 0.5 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG) * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell) * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB) * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB) * Spartan6-LX150 (memory-mapped; both PPIs also connected) * See http://www.skutek.com/ Signed-off-by: Wojtek Skulski <skulski@pas.rochester.edu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>master
Wojtek Skulski
15 years ago
committed by
Mike Frysinger
parent
48c00fe25c
commit
3bbed7f88a
@ -0,0 +1,54 @@ |
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,31 @@ |
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/* U-boot - blackvme.c board specific routines
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* (c) Wojtek Skulski 2010 info@skutek.com |
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* Board info: http://www.skutek.com
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* Copyright (c) 2005-2009 Analog Devices Inc. |
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* |
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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int checkboard(void) |
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{ |
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printf("Board: BlackVME\n"); |
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printf("Support: http://www.skutek.com/\n"); |
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return 0; |
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} |
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#ifdef CONFIG_DRIVER_AX88180 |
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/*
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* The ax88180 driver had to be patched to work around a bug |
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* in Marvell 88E1111 B2 silicon. E-mail me for explanations. |
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*/ |
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int board_eth_init(bd_t *bis) |
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{ |
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return ax88180_initialize(bis); |
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} |
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#endif /* CONFIG_DRIVER_AX88180 */ |
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@ -0,0 +1,32 @@ |
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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CONFIG_BFIN_CPU = bf561-0.5
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,246 @@ |
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/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
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* The board includes ADSP-BF561 rev. 0.5, |
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* 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), |
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* Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), |
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* SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB), |
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* FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB), |
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* Spartan6-LX150 (memory-mapped; both PPIs also connected). |
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* See http://www.skutek.com
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*/ |
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#ifndef __CONFIG_BLACKVME_H__ |
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#define __CONFIG_BLACKVME_H__ |
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#include <asm/config-pre.h> |
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/* Debugging: Set these options if you're having problems
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* #define CONFIG_DEBUG_EARLY_SERIAL |
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* #define DEBUG |
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* #define CONFIG_DEBUG_DUMP |
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* #define CONFIG_DEBUG_DUMP_SYMS |
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* CONFIG_PANIC_HANG means that the board will not auto-reboot |
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*/ |
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#define CONFIG_PANIC_HANG 0 |
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/* CPU Options */ |
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER |
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/*
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* CLOCK SETTINGS CAVEAT |
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* You CANNOT just change the clock settings, esp. the SCLK. |
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* The SDRAM timing, SPI baud, and the serial UART baud |
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* use SCLK frequency to set their own frequencies. Therefore, |
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* if you change the SCLK_DIV, you may also have to adjust |
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* SDRAM refresh and other timings. |
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* -------------------------------------------------------------- |
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
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* 25 * 8 / 1 = 200 MHz |
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* 25 * 16 / 1 = 400 MHz |
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* 25 * 24 / 1 = 600 MHz |
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
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* 25 * 8 / 2 = 100 MHz |
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* 25 * 24 / 6 = 100 MHz |
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* 25 * 24 / 5 = 120 MHz |
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* 25 * 16 / 3 = 133 MHz |
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* 25 MHz because the oscillator also feeds the ether chip. |
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* CONFIG_CLKIN_HZ is 25 MHz written in Hz |
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* CLKIN_HALF controls the DF bit in PLL_CTL |
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* 0 = CLKIN 1 = CLKIN / 2 |
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* PLL_BYPASS controls the BYPASS bit in PLL_CTL |
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* 0 = do not bypass 1 = bypass PLL |
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* VCO_MULT = MSEL (multiplier) in PLL_CTL |
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* Values can range from 0-63 (where 0 means 64) |
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* CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY) |
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* SCLK_DIV = system clock divider, 1 to 15 |
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*/ |
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#define CONFIG_CLKIN_HZ 25000000 |
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#define CONFIG_CLKIN_HALF 0 |
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#define CONFIG_PLL_BYPASS 0 |
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#define CONFIG_VCO_MULT 8 |
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#define CONFIG_CCLK_DIV 1 |
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#define CONFIG_SCLK_DIV 2 |
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/*
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* Ether chip in async memory space AMS3, same as BF561-EZ-KIT. |
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* Used in 32-bit mode. 16-bit mode not supported. |
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* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
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*/ |
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/*
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* Network settings using a dedicated 2nd ether card in PC |
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* Windows will automatically acquire IP of that card |
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* Then use the dedicated card IP + 1 for the board |
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* http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
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*/ |
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#define CONFIG_NET_MULTI |
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#define CONFIG_DRIVER_AX88180 1 |
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#define AX88180_BASE 0x2c000000 |
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#define CONFIG_CMD_MII /* enable probing PHY */ |
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#ifdef CONFIG_NET_MULTI /* also used as the network enabler */ |
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# define CONFIG_HOSTNAME blackvme /* Bfin board */ |
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# define CONFIG_IPADDR 169.254.144.145 /* Bfin board */ |
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# define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */ |
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# define CONFIG_SERVERIP 169.254.144.144 /* tftp server */ |
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# define CONFIG_NETMASK 255.255.255.0 |
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# define CONFIG_ROOTPATH /export/uClinux-dist/romfs /*NFS*/ |
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# define CFG_AUTOLOAD "no" |
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# define CONFIG_CMD_DHCP |
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# define CONFIG_CMD_PING |
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# define CONFIG_ENV_OVERWRITE 1 /* enable changing MAC at runtime */ |
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/* Comment out hardcoded MAC to enable MAC storage in EEPROM */ |
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/* # define CONFIG_ETHADDR ff:ee:dd:cc:bb:aa */ |
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#endif |
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/*
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* SDRAM settings & memory map |
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*/ |
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#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ |
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#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ |
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/*
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* SDRAM reference page |
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* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
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* NOTE: BlackVME populates only SDRAM bank 0 |
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*/ |
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/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */ |
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#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */ |
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#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */ |
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/* Async memory global settings. (ASRAM, not SDRAM)
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* HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1 |
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* CLKOUT enabled, all async banks enabled, core has priority |
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* bank 0&1 16 bit (FPGA) |
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* bank 2&3 32 bit (ether and USB chips) |
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*/ |
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#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */ |
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/* Async mem timing: BF561 HRM page 16-12 and 16-15.
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* Default values 0xFFC2 FFC2 are the slowest supported. |
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* Example settings of CONFIG_EBIU_AMBCTL1_VAL |
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* 1. EZ-KIT settings: 0xFFC2 7BB0 |
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* 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx |
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* See the following page: |
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* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
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* 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz: |
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* AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz |
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* One extra clock needed because AX88180 is asynchronous to CPU. |
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*/ |
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/* bank 1 0 */ |
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#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 |
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/* bank 3 2 */ |
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 |
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/* memory layout */ |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
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#define CONFIG_SYS_MALLOC_LEN (384 << 10) |
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/*
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* Serial SPI Flash |
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* For the M25P64 SCK should be kept < 15 MHz |
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*/ |
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#define CONFIG_BFIN_SPI |
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#define CONFIG_ENV_IS_IN_SPI_FLASH |
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#define CONFIG_ENV_OFFSET 0x40000 |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_ENV_SECT_SIZE 0x40000 |
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#define CONFIG_ENV_SPI_MAX_HZ 15000000 |
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#define CONFIG_SF_DEFAULT_SPEED 15000000 |
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#define CONFIG_SPI_FLASH |
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#define CONFIG_SPI_FLASH_STMICRO |
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/*
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* Interactive command settings |
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*/ |
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#define CONFIG_SYS_LONGHELP 1 |
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#define CONFIG_CMDLINE_EDITING 1 |
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#define CONFIG_AUTO_COMPLETE 1 |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_BOOTLDR |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_CPLBINFO |
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#define CONFIG_CMD_SF |
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#define CONFIG_CMD_ELF |
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/*
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* Default: boot from SPI flash. |
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* "sfboot" is a composite command defined in extra settings |
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*/ |
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#define CONFIG_BOOTDELAY 5 |
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#define CONFIG_BOOTCOMMAND "run sfboot" |
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/*
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* Console settings |
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*/ |
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#define CONFIG_BAUDRATE 57600 |
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#define CONFIG_LOADS_ECHO 1 |
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#define CONFIG_UART_CONSOLE 0 |
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/*
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* U-Boot environment variables. Use "printenv" to examine. |
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* http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
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*/ |
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#define CONFIG_BOOTARGS \ |
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"root=/dev/mtdblock0 rw " \
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"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
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"earlyprintk=serial,uart0," \
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MK_STR(CONFIG_BAUDRATE) " " \
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"console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " " |
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/* Convenience env variables & commands.
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* Reserve kernstart = 0x20000 = 128 kB for U-Boot. |
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* Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size). |
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* U-Boot image is saved at flash offset=0. |
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* Kernel image is saved at flash offset=$kernstart. |
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* Instructions. Ksave takes about a minute to complete. |
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* 1. Update U-Boot: run uget; run usave |
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* 2. Update kernel: run kget; run ksave |
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* After updating U-Boot also update the kernel per above instructions |
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* to make the saved environment consistent with the flash. |
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*/ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"kernstart=0x20000\0" \
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"kernarea=0x500000\0" \
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"uget=tftp u-boot.ldr\0" \
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"kget=tftp uImage\0" \
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"usave=sf probe 2; " \
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"sf erase 0 $(kernstart); " \
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"sf write $(fileaddr) 0 $(filesize)\0" \
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"ksave=sf probe 2; " \
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"saveenv; " \
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"echo Now patiently wait for the prompt...; " \
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"sf erase $(kernstart) $(kernarea); " \
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"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
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"sfboot=sf probe 2; " \
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"sf read $(loadaddr) $(kernstart) $(filesize); " \
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"run addip; bootm\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):" \
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"$(netmask):$(hostname):eth0:off\0" |
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/*
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* Soft I2C settings (BF561 does not have hard I2C) |
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* PF12,13 on SPI connector 0. |
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*/ |
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#ifdef CONFIG_SOFT_I2C |
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# define CONFIG_CMD_I2C |
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# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12 |
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# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13 |
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# define CONFIG_SYS_I2C_SPEED 50000 |
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# define CONFIG_SYS_I2C_SLAVE 0xFE |
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#endif |
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/*
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* No Parallel Flash on this board |
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*/ |
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#define CONFIG_SYS_NO_FLASH |
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#undef CONFIG_CMD_IMLS |
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#undef CONFIG_CMD_JFFS2 |
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#undef CONFIG_CMD_FLASH |
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#endif |
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