Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference Platform support. * Patch by Masami Komiya, 08 Mar 2004: Don't overwrite server IP address or boot file name when the boot server does not return values * Patch by listmember@orkun.us, 5 Mar 2004: Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTCmaster
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#
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# (C) Copyright 2000-2004
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004
|
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# ARM Ltd.
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# Philippe Robin, <philippe.robin@arm.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := integratorap.o flash.o
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SOBJS := platform.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,5 @@ |
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#
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# image should be loaded at 0x01000000
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#
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TEXT_BASE = 0x01000000
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@ -0,0 +1,473 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* Kshitij Gupta <Kshitij@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) __swab16(x) |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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/* Flash Organization Structure */ |
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typedef struct OrgDef { |
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unsigned int sector_number; |
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unsigned int sector_size; |
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} OrgDef; |
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/* Flash Organizations */ |
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OrgDef OrgIntel_28F256L18T[] = { |
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{4, 32 * 1024}, /* 4 * 32kBytes sectors */ |
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{255, 128 * 1024}, /* 255 * 128kBytes sectors */ |
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}; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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unsigned long flash_init (void); |
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static ulong flash_get_size (FPW * addr, flash_info_t * info); |
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static int write_data (flash_info_t * info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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void inline spin_wheel (void); |
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void flash_print_info (flash_info_t * info); |
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void flash_unprotect_sectors (FPWV * addr); |
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int flash_erase (flash_info_t * info, int s_first, int s_last); |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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break; |
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default: |
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panic ("configured too many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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/* Protect monitor and environment sectors
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*/ |
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flash_protect (FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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OrgDef *pOrgDef; |
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pOrgDef = OrgIntel_28F256L18T; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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if (i > 255) { |
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info->start[i] = base + (i * 0x8000); |
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info->protect[i] = 0; |
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} else { |
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info->start[i] = base + |
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(i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F256L18T: |
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printf ("FLASH 28F256L18T\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) (INTEL_ID_28F256L18T): |
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info->flash_id += FLASH_28F256L18T; |
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info->sector_count = 259; |
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info->size = 0x02000000; |
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break; /* => 32 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/* unprotects a sector for write and erase
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* on some intel parts, this unprotects the entire chip, but it |
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* wont hurt to call this additional times per sector... |
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*/ |
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void flash_unprotect_sectors (FPWV * addr) |
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{ |
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#define PD_FINTEL_WSMS_READY_MASK 0x0080 |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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/* this sends the clear lock bit command */ |
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*addr = (FPW) 0x00600060; |
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*addr = (FPW) 0x00D000D0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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start = get_timer (0); |
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last = start; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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flash_unprotect_sectors (addr); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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*addr = (FPW) 0x00500050;/* clear status register */ |
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*addr = (FPW) 0x00200020;/* erase setup */ |
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*addr = (FPW) 0x00D000D0;/* erase confirm */ |
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while (((status = |
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*addr) & (FPW) 0x00800080) != |
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(FPW) 0x00800080) { |
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if (get_timer_masked () > |
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CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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/* suspend erase */ |
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*addr = (FPW) 0x00B000B0; |
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/* reset to read mode */ |
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*addr = (FPW) 0x00FF00FF; |
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rcode = 1; |
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break; |
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} |
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} |
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/* clear status register cmd. */ |
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*addr = (FPW) 0x00500050; |
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*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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|
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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for (; i < port_width && cnt > 0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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|
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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|
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i = 0; i < port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) { |
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spin_wheel (); |
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count = 0; |
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} |
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} |
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|
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if (cnt == 0) { |
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return (0); |
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} |
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|
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/*
|
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
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data = (data << 8) | *src++; |
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--cnt; |
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} |
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for (; i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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|
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return (write_data (info, wp, SWAP (data))); |
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} |
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|
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/*-----------------------------------------------------------------------
|
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t * info, ulong dest, FPW data) |
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{ |
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FPWV *addr = (FPWV *) dest; |
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ulong status; |
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int flag; |
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|
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
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return (2); |
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} |
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flash_unprotect_sectors (addr); |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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*addr = (FPW) 0x00400040; /* write setup */ |
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*addr = data; |
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|
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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|
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/* wait while polling the status register */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); |
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} |
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|
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void inline spin_wheel (void) |
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{ |
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static int p = 0; |
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static char w[] = "\\/-"; |
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|
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printf ("\010%c", w[p]); |
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(++p == 3) ? (p = 0) : 0; |
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} |
@ -0,0 +1,455 @@ |
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/*
|
||||
* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_PCI |
||||
# include <pci.h> |
||||
#endif |
||||
|
||||
void flash__init (void); |
||||
void ether__init (void); |
||||
void peripheral_power_enable (void); |
||||
|
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS) |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
printf("Boot reached stage %d\n", progress); |
||||
} |
||||
#endif |
||||
|
||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of Integrator Board */ |
||||
gd->bd->bi_arch_number = 21; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
|
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
pci_init(); |
||||
#endif |
||||
setenv("verify", "n"); |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
#ifdef CONFIG_PCI |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
|
||||
static struct pci_config_table pci_integrator_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
// V3 access routines
|
||||
#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) |
||||
#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) |
||||
|
||||
#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) |
||||
#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) |
||||
|
||||
// Compute address necessary to access PCI config space for the given
|
||||
// bus and device.
|
||||
#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \ |
||||
({ \
|
||||
unsigned int __address, __devicebit; \
|
||||
unsigned short __mapaddress; \
|
||||
unsigned int __dev = PCI_DEV(__devfn); /* FIXME to check!! (slot?) */ \
|
||||
\
|
||||
if (__bus == 0) { \
|
||||
/* local bus segment so need a type 0 config cycle */ \
|
||||
/* build the PCI configuration "address" with one-hot in A31-A11 */ \
|
||||
__address = PCI_CONFIG_BASE; \
|
||||
__address |= ((__devfn & 0x07) << 8); \
|
||||
__address |= __offset & 0xFF; \
|
||||
__mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
|
||||
__devicebit = (1 << (__dev + 11)); \
|
||||
\
|
||||
if ((__devicebit & 0xFF000000) != 0) { \
|
||||
/* high order bits are handled by the MAP register */ \
|
||||
__mapaddress |= (__devicebit >> 16); \
|
||||
} else { \
|
||||
/* low order bits handled directly in the address */ \
|
||||
__address |= __devicebit; \
|
||||
} \
|
||||
} else { /* bus !=0 */ \
|
||||
/* not the local bus segment so need a type 1 config cycle */ \
|
||||
/* A31-A24 are don't care (so clear to 0) */ \
|
||||
__mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
|
||||
__address = PCI_CONFIG_BASE; \
|
||||
__address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
|
||||
__address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
|
||||
__address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number*/ \
|
||||
__address |= __offset & 0xFF; /* bits 7..0 = register number*/ \
|
||||
} \
|
||||
_V3Write16(V3_LB_MAP1, __mapaddress); \
|
||||
\
|
||||
__address; \
|
||||
}) |
||||
|
||||
// _V3OpenConfigWindow - open V3 configuration window
|
||||
#define _V3OpenConfigWindow() \ |
||||
{ \
|
||||
/* Set up base0 to see all 512Mbytes of memory space (not */ \
|
||||
/* prefetchable), this frees up base1 for re-use by configuration*/ \
|
||||
/* memory */ \
|
||||
\
|
||||
_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
|
||||
0x90 | V3_LB_BASE_M_ENABLE)); \
|
||||
/* Set up base1 to point into configuration space, note that MAP1 */ \
|
||||
/* register is set up by pciMakeConfigAddress(). */ \
|
||||
\
|
||||
_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
|
||||
0x40 | V3_LB_BASE_M_ENABLE)); \
|
||||
} |
||||
|
||||
// _V3CloseConfigWindow - close V3 configuration window
|
||||
#define _V3CloseConfigWindow() \ |
||||
{ \
|
||||
/* Reassign base1 for use by prefetchable PCI memory */ \
|
||||
_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
|
||||
| 0x84 | V3_LB_BASE_M_ENABLE)); \
|
||||
_V3Write16 (V3_LB_MAP1, \
|
||||
(((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
|
||||
\
|
||||
/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
|
||||
\
|
||||
_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
|
||||
0x80 | V3_LB_BASE_M_ENABLE)); \
|
||||
} |
||||
|
||||
|
||||
static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset, unsigned char *val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset, unsigned short *val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset, unsigned int *val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
||||
*val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16; |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset, unsigned char val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val; |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset,unsigned short val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val; |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev, |
||||
int offset, unsigned int val) |
||||
{ |
||||
_V3OpenConfigWindow(); |
||||
*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF); |
||||
*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF); |
||||
_V3CloseConfigWindow(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/******************************
|
||||
* PCI initialisation |
||||
******************************/ |
||||
|
||||
struct pci_controller integrator_hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_integrator_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
volatile int i, j; |
||||
struct pci_controller *hose = &integrator_hose; |
||||
|
||||
/* setting this register will take the V3 out of reset */ |
||||
|
||||
*(volatile unsigned int *)(INTEGRATOR_SC_PCIENABLE) = 1; |
||||
|
||||
/* wait a few usecs to settle the device and the PCI bus */ |
||||
|
||||
for (i = 0; i < 100 ; i++) |
||||
j = i + 1; |
||||
|
||||
/* Now write the Base I/O Address Word to V3_BASE + 0x6C */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16); |
||||
|
||||
do { |
||||
*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) = 0xAA; |
||||
*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55; |
||||
} while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA || |
||||
*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55); |
||||
|
||||
/* Make sure that V3 register access is not locked, if it is, unlock it */ |
||||
|
||||
if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK) |
||||
== V3_SYSTEM_M_LOCK) |
||||
*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = 0xA05F; |
||||
|
||||
/* Ensure that the slave accesses from PCI are disabled while we */ |
||||
/* setup windows */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) &= |
||||
~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); |
||||
|
||||
/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT; |
||||
|
||||
/* Make all accesses from PCI space retry until we're ready for them */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN; |
||||
|
||||
/* Set up any V3 PCI Configuration Registers that we absolutely have to */ |
||||
/* LB_CFG controls Local Bus protocol. */ |
||||
/* Enable LocalBus byte strobes for READ accesses too. */ |
||||
/* set bit 7 BE_IMODE and bit 6 BE_OMODE */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_LB_CFG) |= 0x0C0; |
||||
|
||||
/* PCI_CMD controls overall PCI operation. */ |
||||
/* Enable PCI bus master. */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) |= 0x04; |
||||
|
||||
/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus*/ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) | |
||||
(V3_PCI_MAP_M_ADR_SIZE_512M | |
||||
V3_PCI_MAP_M_REG_EN | |
||||
V3_PCI_MAP_M_ENABLE); |
||||
|
||||
/* PCI_BASE0 is the PCI address of the start of the window */ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE; |
||||
|
||||
/* PCI_MAP1 is LOCAL address of the start of the window */ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) | |
||||
(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN | |
||||
V3_PCI_MAP_M_ENABLE); |
||||
|
||||
/* PCI_BASE1 is the PCI address of the start of the window */ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE; |
||||
|
||||
/* Set up the windows from local bus memory into PCI configuration, */ |
||||
/* I/O and Memory. */ |
||||
/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE +V3_LB_BASE2) = |
||||
((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; |
||||
*(volatile unsigned short *)(V3_BASE + V3_LB_MAP2) = 0; |
||||
|
||||
/* PCI Configuration, use LB_BASE1/LB_MAP1. */ |
||||
|
||||
/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ |
||||
/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ |
||||
/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_LB_BASE0) = |
||||
INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_LB_MAP0) = |
||||
((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; |
||||
|
||||
/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ |
||||
|
||||
*(volatile unsigned int *)(V3_BASE + V3_LB_BASE1) = |
||||
INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_LB_MAP1) = |
||||
(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; |
||||
|
||||
/* Allow accesses to PCI Configuration space */ |
||||
/* and set up A1, A0 for type 1 config cycles */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) = |
||||
((*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG)) & |
||||
~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1) ) | |
||||
V3_PCI_CFG_M_AD_LOW0; |
||||
|
||||
/* now we can allow in PCI MEMORY accesses */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD) = |
||||
(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN; |
||||
|
||||
/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ |
||||
/* initialise and lock the V3 system register so that no one else */ |
||||
/* can play with it */ |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = |
||||
(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT; |
||||
|
||||
*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) = |
||||
(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK; |
||||
|
||||
/*
|
||||
* Register the hose |
||||
*/ |
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 0, |
||||
0x00000000, 0x40000000, 0x01000000, |
||||
PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
/* PCI Memory - config space */ |
||||
pci_set_region(hose->regions + 1, |
||||
0x00000000, 0x62000000, 0x01000000, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI V3 regs */ |
||||
pci_set_region(hose->regions + 2, |
||||
0x00000000, 0x61000000, 0x00080000, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI I/O space */ |
||||
pci_set_region(hose->regions + 3, |
||||
0x00000000, 0x60000000, 0x00010000, |
||||
PCI_REGION_IO); |
||||
|
||||
pci_set_ops(hose, |
||||
pci_integrator_read_byte, |
||||
pci_integrator_read__word, |
||||
pci_integrator_read_dword, |
||||
pci_integrator_write_byte, |
||||
pci_integrator_write_word, |
||||
pci_integrator_write_dword); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
pciauto_config_init(hose); |
||||
pciauto_config_device(hose, 0); |
||||
|
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
#endif |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
void flash__init (void) |
||||
{ |
||||
} |
||||
/*************************************************************
|
||||
Routine:ether__init |
||||
Description: take the Ethernet controller out of reset and wait |
||||
for the EEPROM load to complete. |
||||
*************************************************************/ |
||||
void ether__init (void) |
||||
{ |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
int dram_init (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
@ -0,0 +1,33 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2004, ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
.globl platformsetup
|
||||
platformsetup: |
||||
|
||||
/* All done by Integrator's boot monitor! */ |
||||
mov pc, lr |
@ -0,0 +1,50 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
armboot_end_data = .; |
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,47 @@ |
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := integratorcp.o flash.o
|
||||
SOBJS := platform.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,5 @@ |
||||
#
|
||||
# image should be loaded at 0x01000000
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x01000000
|
@ -0,0 +1,473 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2001-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/byteorder/swab.h> |
||||
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/* Board support for 1 or 2 flash devices */ |
||||
#undef FLASH_PORT_WIDTH32 |
||||
#define FLASH_PORT_WIDTH16 |
||||
|
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
#define FLASH_PORT_WIDTH ushort |
||||
#define FLASH_PORT_WIDTHV vu_short |
||||
#define SWAP(x) __swab16(x) |
||||
#else |
||||
#define FLASH_PORT_WIDTH ulong |
||||
#define FLASH_PORT_WIDTHV vu_long |
||||
#define SWAP(x) __swab32(x) |
||||
#endif |
||||
|
||||
#define FPW FLASH_PORT_WIDTH |
||||
#define FPWV FLASH_PORT_WIDTHV |
||||
|
||||
#define mb() __asm__ __volatile__ ("" : : : "memory") |
||||
|
||||
|
||||
/* Flash Organization Structure */ |
||||
typedef struct OrgDef { |
||||
unsigned int sector_number; |
||||
unsigned int sector_size; |
||||
} OrgDef; |
||||
|
||||
|
||||
/* Flash Organizations */ |
||||
OrgDef OrgIntel_28F256L18T[] = { |
||||
{4, 32 * 1024}, /* 4 * 32kBytes sectors */ |
||||
{255, 128 * 1024}, /* 255 * 128kBytes sectors */ |
||||
}; |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
unsigned long flash_init (void); |
||||
static ulong flash_get_size (FPW * addr, flash_info_t * info); |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
void inline spin_wheel (void); |
||||
void flash_print_info (flash_info_t * info); |
||||
void flash_unprotect_sectors (FPWV * addr); |
||||
int flash_erase (flash_info_t * info, int s_first, int s_last); |
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
int i; |
||||
ulong size = 0; |
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
||||
switch (i) { |
||||
case 0: |
||||
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
||||
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
||||
break; |
||||
default: |
||||
panic ("configured too many flash banks!\n"); |
||||
break; |
||||
} |
||||
size += flash_info[i].size; |
||||
} |
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_FLASH_BASE, |
||||
CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t * info) |
||||
{ |
||||
int i; |
||||
OrgDef *pOrgDef; |
||||
|
||||
pOrgDef = OrgIntel_28F256L18T; |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return; |
||||
} |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
if (i > 255) { |
||||
info->start[i] = base + (i * 0x8000); |
||||
info->protect[i] = 0; |
||||
} else { |
||||
info->start[i] = base + |
||||
(i * PHYS_FLASH_SECT_SIZE); |
||||
info->protect[i] = 0; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_INTEL: |
||||
printf ("INTEL "); |
||||
break; |
||||
default: |
||||
printf ("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_28F256L18T: |
||||
printf ("FLASH 28F256L18T\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
static ulong flash_get_size (FPW * addr, flash_info_t * info) |
||||
{ |
||||
volatile FPW value; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
addr[0x5555] = (FPW) 0x00AA00AA; |
||||
addr[0x2AAA] = (FPW) 0x00550055; |
||||
addr[0x5555] = (FPW) 0x00900090; |
||||
|
||||
mb (); |
||||
value = addr[0]; |
||||
|
||||
switch (value) { |
||||
|
||||
case (FPW) INTEL_MANUFACT: |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
mb (); |
||||
value = addr[1]; /* device ID */ |
||||
switch (value) { |
||||
|
||||
case (FPW) (INTEL_ID_28F256L18T): |
||||
info->flash_id += FLASH_28F256L18T; |
||||
info->sector_count = 259; |
||||
info->size = 0x02000000; |
||||
break; /* => 32 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
break; |
||||
} |
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) { |
||||
printf ("** ERROR: sector count %d > max (%d) **\n", |
||||
info->sector_count, CFG_MAX_FLASH_SECT); |
||||
info->sector_count = CFG_MAX_FLASH_SECT; |
||||
} |
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/* unprotects a sector for write and erase
|
||||
* on some intel parts, this unprotects the entire chip, but it |
||||
* wont hurt to call this additional times per sector... |
||||
*/ |
||||
void flash_unprotect_sectors (FPWV * addr) |
||||
{ |
||||
#define PD_FINTEL_WSMS_READY_MASK 0x0080 |
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */ |
||||
|
||||
/* this sends the clear lock bit command */ |
||||
*addr = (FPW) 0x00600060; |
||||
*addr = (FPW) 0x00D000D0; |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
int flag, prot, sect; |
||||
ulong type, start, last; |
||||
int rcode = 0; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK); |
||||
if ((type != FLASH_MAN_INTEL)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
FPWV *addr = (FPWV *) (info->start[sect]); |
||||
FPW status; |
||||
|
||||
printf ("Erasing sector %2d ... ", sect); |
||||
|
||||
flash_unprotect_sectors (addr); |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked (); |
||||
|
||||
*addr = (FPW) 0x00500050;/* clear status register */ |
||||
*addr = (FPW) 0x00200020;/* erase setup */ |
||||
*addr = (FPW) 0x00D000D0;/* erase confirm */ |
||||
|
||||
while (((status = |
||||
*addr) & (FPW) 0x00800080) != |
||||
(FPW) 0x00800080) { |
||||
if (get_timer_masked () > |
||||
CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
/* suspend erase */ |
||||
*addr = (FPW) 0x00B000B0; |
||||
/* reset to read mode */ |
||||
*addr = (FPW) 0x00FF00FF; |
||||
rcode = 1; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* clear status register cmd. */ |
||||
*addr = (FPW) 0x00500050; |
||||
*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
||||
printf (" done\n"); |
||||
} |
||||
} |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
* 4 - Flash not identified |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp; |
||||
FPW data; |
||||
int count, i, l, rc, port_width; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return 4; |
||||
} |
||||
/* get lower word aligned address */ |
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
wp = (addr & ~1); |
||||
port_width = 2; |
||||
#else |
||||
wp = (addr & ~3); |
||||
port_width = 4; |
||||
#endif |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
for (; i < port_width && cnt > 0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
count = 0; |
||||
while (cnt >= port_width) { |
||||
data = 0; |
||||
for (i = 0; i < port_width; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
cnt -= port_width; |
||||
if (count++ > 0x800) { |
||||
spin_wheel (); |
||||
count = 0; |
||||
} |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
return (write_data (info, wp, SWAP (data))); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data) |
||||
{ |
||||
FPWV *addr = (FPWV *) dest; |
||||
ulong status; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
||||
return (2); |
||||
} |
||||
flash_unprotect_sectors (addr); |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
*addr = (FPW) 0x00400040; /* write setup */ |
||||
*addr = data; |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked (); |
||||
|
||||
/* wait while polling the status register */ |
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (1); |
||||
} |
||||
} |
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (0); |
||||
} |
||||
|
||||
void inline spin_wheel (void) |
||||
{ |
||||
static int p = 0; |
||||
static char w[] = "\\/-"; |
||||
|
||||
printf ("\010%c", w[p]); |
||||
(++p == 3) ? (p = 0) : 0; |
||||
} |
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
void flash__init (void); |
||||
void ether__init (void); |
||||
void peripheral_power_enable (void); |
||||
|
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS) |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
printf("Boot reached stage %d\n", progress); |
||||
} |
||||
#endif |
||||
|
||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* arch number of Integrator Board */ |
||||
gd->bd->bi_arch_number = 275; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
|
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
setenv("verify", "n"); |
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
void flash__init (void) |
||||
{ |
||||
} |
||||
/*************************************************************
|
||||
Routine:ether__init |
||||
Description: take the Ethernet controller out of reset and wait |
||||
for the EEPROM load to complete. |
||||
*************************************************************/ |
||||
void ether__init (void) |
||||
{ |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
int dram_init (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
@ -0,0 +1,33 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003, ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
.globl platformsetup
|
||||
platformsetup: |
||||
|
||||
/* All done by IntegratorCP's boot monitor! */ |
||||
mov pc, lr |
@ -0,0 +1,50 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
armboot_end_data = .; |
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,47 @@ |
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := versatile.o flash.o
|
||||
SOBJS := platform.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,5 @@ |
||||
#
|
||||
# image should be loaded at 0x01000000
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x01000000
|
@ -0,0 +1,473 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
||||
* |
||||
* (C) Copyright 2001-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/byteorder/swab.h> |
||||
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/* Board support for 1 or 2 flash devices */ |
||||
#undef FLASH_PORT_WIDTH32 |
||||
#define FLASH_PORT_WIDTH16 |
||||
|
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
#define FLASH_PORT_WIDTH ushort |
||||
#define FLASH_PORT_WIDTHV vu_short |
||||
#define SWAP(x) __swab16(x) |
||||
#else |
||||
#define FLASH_PORT_WIDTH ulong |
||||
#define FLASH_PORT_WIDTHV vu_long |
||||
#define SWAP(x) __swab32(x) |
||||
#endif |
||||
|
||||
#define FPW FLASH_PORT_WIDTH |
||||
#define FPWV FLASH_PORT_WIDTHV |
||||
|
||||
#define mb() __asm__ __volatile__ ("" : : : "memory") |
||||
|
||||
|
||||
/* Flash Organization Structure */ |
||||
typedef struct OrgDef { |
||||
unsigned int sector_number; |
||||
unsigned int sector_size; |
||||
} OrgDef; |
||||
|
||||
|
||||
/* Flash Organizations */ |
||||
OrgDef OrgIntel_28F256L18T[] = { |
||||
{4, 32 * 1024}, /* 4 * 32kBytes sectors */ |
||||
{255, 128 * 1024}, /* 255 * 128kBytes sectors */ |
||||
}; |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
unsigned long flash_init (void); |
||||
static ulong flash_get_size (FPW * addr, flash_info_t * info); |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
void inline spin_wheel (void); |
||||
void flash_print_info (flash_info_t * info); |
||||
void flash_unprotect_sectors (FPWV * addr); |
||||
int flash_erase (flash_info_t * info, int s_first, int s_last); |
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
int i; |
||||
ulong size = 0; |
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
||||
switch (i) { |
||||
case 0: |
||||
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
||||
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
||||
break; |
||||
default: |
||||
panic ("configured too many flash banks!\n"); |
||||
break; |
||||
} |
||||
size += flash_info[i].size; |
||||
} |
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_FLASH_BASE, |
||||
CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); |
||||
|
||||
return size; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t * info) |
||||
{ |
||||
int i; |
||||
OrgDef *pOrgDef; |
||||
|
||||
pOrgDef = OrgIntel_28F256L18T; |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return; |
||||
} |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
if (i > 255) { |
||||
info->start[i] = base + (i * 0x8000); |
||||
info->protect[i] = 0; |
||||
} else { |
||||
info->start[i] = base + |
||||
(i * PHYS_FLASH_SECT_SIZE); |
||||
info->protect[i] = 0; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_INTEL: |
||||
printf ("INTEL "); |
||||
break; |
||||
default: |
||||
printf ("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_28F256L18T: |
||||
printf ("FLASH 28F256L18T\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
static ulong flash_get_size (FPW * addr, flash_info_t * info) |
||||
{ |
||||
volatile FPW value; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
addr[0x5555] = (FPW) 0x00AA00AA; |
||||
addr[0x2AAA] = (FPW) 0x00550055; |
||||
addr[0x5555] = (FPW) 0x00900090; |
||||
|
||||
mb (); |
||||
value = addr[0]; |
||||
|
||||
switch (value) { |
||||
|
||||
case (FPW) INTEL_MANUFACT: |
||||
info->flash_id = FLASH_MAN_INTEL; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
mb (); |
||||
value = addr[1]; /* device ID */ |
||||
switch (value) { |
||||
|
||||
case (FPW) (INTEL_ID_28F256L18T): |
||||
info->flash_id += FLASH_28F256L18T; |
||||
info->sector_count = 259; |
||||
info->size = 0x02000000; |
||||
break; /* => 32 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
break; |
||||
} |
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) { |
||||
printf ("** ERROR: sector count %d > max (%d) **\n", |
||||
info->sector_count, CFG_MAX_FLASH_SECT); |
||||
info->sector_count = CFG_MAX_FLASH_SECT; |
||||
} |
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/* unprotects a sector for write and erase
|
||||
* on some intel parts, this unprotects the entire chip, but it |
||||
* wont hurt to call this additional times per sector... |
||||
*/ |
||||
void flash_unprotect_sectors (FPWV * addr) |
||||
{ |
||||
#define PD_FINTEL_WSMS_READY_MASK 0x0080 |
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */ |
||||
|
||||
/* this sends the clear lock bit command */ |
||||
*addr = (FPW) 0x00600060; |
||||
*addr = (FPW) 0x00D000D0; |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
int flag, prot, sect; |
||||
ulong type, start, last; |
||||
int rcode = 0; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK); |
||||
if ((type != FLASH_MAN_INTEL)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
FPWV *addr = (FPWV *) (info->start[sect]); |
||||
FPW status; |
||||
|
||||
printf ("Erasing sector %2d ... ", sect); |
||||
|
||||
flash_unprotect_sectors (addr); |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked (); |
||||
|
||||
*addr = (FPW) 0x00500050;/* clear status register */ |
||||
*addr = (FPW) 0x00200020;/* erase setup */ |
||||
*addr = (FPW) 0x00D000D0;/* erase confirm */ |
||||
|
||||
while (((status = |
||||
*addr) & (FPW) 0x00800080) != |
||||
(FPW) 0x00800080) { |
||||
if (get_timer_masked () > |
||||
CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
/* suspend erase */ |
||||
*addr = (FPW) 0x00B000B0; |
||||
/* reset to read mode */ |
||||
*addr = (FPW) 0x00FF00FF; |
||||
rcode = 1; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* clear status register cmd. */ |
||||
*addr = (FPW) 0x00500050; |
||||
*addr = (FPW) 0x00FF00FF;/* resest to read mode */ |
||||
printf (" done\n"); |
||||
} |
||||
} |
||||
return rcode; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
* 4 - Flash not identified |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp; |
||||
FPW data; |
||||
int count, i, l, rc, port_width; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return 4; |
||||
} |
||||
/* get lower word aligned address */ |
||||
#ifdef FLASH_PORT_WIDTH16 |
||||
wp = (addr & ~1); |
||||
port_width = 2; |
||||
#else |
||||
wp = (addr & ~3); |
||||
port_width = 4; |
||||
#endif |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
for (; i < port_width && cnt > 0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
count = 0; |
||||
while (cnt >= port_width) { |
||||
data = 0; |
||||
for (i = 0; i < port_width; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += port_width; |
||||
cnt -= port_width; |
||||
if (count++ > 0x800) { |
||||
spin_wheel (); |
||||
count = 0; |
||||
} |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i < port_width; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
return (write_data (info, wp, SWAP (data))); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_data (flash_info_t * info, ulong dest, FPW data) |
||||
{ |
||||
FPWV *addr = (FPWV *) dest; |
||||
ulong status; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
||||
return (2); |
||||
} |
||||
flash_unprotect_sectors (addr); |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
*addr = (FPW) 0x00400040; /* write setup */ |
||||
*addr = data; |
||||
|
||||
/* arm simple, non interrupt dependent timer */ |
||||
reset_timer_masked (); |
||||
|
||||
/* wait while polling the status register */ |
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (1); |
||||
} |
||||
} |
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||
return (0); |
||||
} |
||||
|
||||
void inline spin_wheel (void) |
||||
{ |
||||
static int p = 0; |
||||
static char w[] = "\\/-"; |
||||
|
||||
printf ("\010%c", w[p]); |
||||
(++p == 3) ? (p = 0) : 0; |
||||
} |
@ -0,0 +1,33 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003, ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
.globl platformsetup
|
||||
platformsetup: |
||||
|
||||
/* All done by Versatile's boot monitor! */ |
||||
mov pc, lr |
@ -0,0 +1,50 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm926ejs/start.o (.text) |
||||
*(.text) |
||||
} |
||||
.rodata : { *(.rodata) } |
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
armboot_end_data = .; |
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,120 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
void flash__init (void); |
||||
void ether__init (void); |
||||
void peripheral_power_enable (void); |
||||
|
||||
#if defined(CONFIG_SHOW_BOOT_PROGRESS) |
||||
void show_boot_progress(int progress) |
||||
{ |
||||
printf("Boot reached stage %d\n", progress); |
||||
} |
||||
#endif |
||||
|
||||
#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
|
||||
/*
|
||||
* set clock frequency: |
||||
* VERSATILE_REFCLK is 32KHz |
||||
* VERSATILE_TIMCLK is 1MHz |
||||
*/ |
||||
*(volatile unsigned int *)(VERSATILE_SCTL_BASE) |= |
||||
((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | |
||||
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); |
||||
|
||||
/* arch number of Versatile Board */ |
||||
gd->bd->bi_arch_number = 387; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
|
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
setenv("verify", "n"); |
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
void flash__init (void) |
||||
{ |
||||
} |
||||
/*************************************************************
|
||||
Routine:ether__init |
||||
Description: take the Ethernet controller out of reset and wait |
||||
for the EEPROM load to complete. |
||||
*************************************************************/ |
||||
void ether__init (void) |
||||
{ |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
int dram_init (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
@ -0,0 +1,177 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ |
||||
/* Should be fairly simple to make it work with the PL010 as well */ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CFG_PL010_SERIAL |
||||
|
||||
#include "serial_pl011.h" |
||||
|
||||
#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) |
||||
#define IO_READ(addr) (*(volatile unsigned int *)(addr)) |
||||
|
||||
/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ |
||||
#define NUM_PORTS 2 |
||||
#define CONSOLE_PORT CONFIG_CONS_INDEX |
||||
#define baudRate CONFIG_BAUDRATE |
||||
static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0), |
||||
(void*)(CFG_SERIAL1)}; |
||||
|
||||
|
||||
static void pl010_putc(int portnum, char c); |
||||
static int pl010_getc(int portnum); |
||||
static int pl010_tstc(int portnum); |
||||
|
||||
|
||||
int serial_init (void) |
||||
{ |
||||
unsigned int temp; |
||||
unsigned int divisor; |
||||
|
||||
/*
|
||||
** First, disable everything. |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, 0x0); |
||||
|
||||
/*
|
||||
** Set baud rate |
||||
** |
||||
*/ |
||||
switch (baudRate) { |
||||
case 9600: |
||||
divisor = UART_PL010_BAUD_9600; |
||||
break; |
||||
|
||||
case 19200: |
||||
divisor = UART_PL010_BAUD_9600; |
||||
break; |
||||
|
||||
case 38400: |
||||
divisor = UART_PL010_BAUD_38400; |
||||
break; |
||||
|
||||
case 57600: |
||||
divisor = UART_PL010_BAUD_57600; |
||||
break; |
||||
|
||||
case 115200: |
||||
divisor = UART_PL010_BAUD_115200; |
||||
break; |
||||
|
||||
default: |
||||
divisor = UART_PL010_BAUD_38400; |
||||
} |
||||
|
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRM, ((divisor & 0xf00) >> 8)); |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); |
||||
|
||||
/*
|
||||
** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL010_LCRH, |
||||
(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); |
||||
|
||||
/*
|
||||
** Finally, enable the UART |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
void |
||||
serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
pl010_putc(CONSOLE_PORT, '\r'); |
||||
|
||||
pl010_putc(CONSOLE_PORT, c); |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) { |
||||
serial_putc (*s++); |
||||
} |
||||
} |
||||
|
||||
int |
||||
serial_getc(void) |
||||
{ |
||||
return pl010_getc(CONSOLE_PORT); |
||||
} |
||||
|
||||
int |
||||
serial_tstc(void) |
||||
{ |
||||
return pl010_tstc(CONSOLE_PORT); |
||||
} |
||||
|
||||
void |
||||
serial_setbrg (void) |
||||
{ |
||||
} |
||||
|
||||
static void pl010_putc(int portnum, char c) |
||||
{ |
||||
/* Wait until there is space in the FIFO */ |
||||
while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); |
||||
|
||||
/* Send the character */ |
||||
IO_WRITE(port[portnum] + UART_PL01x_DR, c); |
||||
} |
||||
|
||||
static int pl010_getc(int portnum) |
||||
{ |
||||
unsigned int data; |
||||
|
||||
/* Wait until there is data in the FIFO */ |
||||
while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); |
||||
|
||||
data = IO_READ(port[portnum] + UART_PL01x_DR); |
||||
|
||||
/* Check for an error flag */ |
||||
if (data & 0xFFFFFF00) |
||||
{ |
||||
/* Clear the error */ |
||||
IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); |
||||
return -1; |
||||
} |
||||
|
||||
return (int)data; |
||||
} |
||||
|
||||
static int pl010_tstc(int portnum) |
||||
{ |
||||
return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); |
||||
} |
||||
|
||||
#endif |
@ -0,0 +1,175 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ |
||||
/* Should be fairly simple to make it work with the PL010 as well */ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CFG_PL011_SERIAL |
||||
|
||||
#include "serial_pl011.h" |
||||
|
||||
#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) |
||||
#define IO_READ(addr) (*(volatile unsigned int *)(addr)) |
||||
|
||||
/*
|
||||
* IntegratorCP has two UARTs, use the first one, at 38400-8-N-1
|
||||
* Versatile PB has four UARTs. |
||||
*/ |
||||
#define NUM_PORTS 2 |
||||
#define CONSOLE_PORT CONFIG_CONS_INDEX |
||||
#define baudRate CONFIG_BAUDRATE |
||||
static volatile unsigned char * const port[NUM_PORTS] = {(void*)(CFG_SERIAL0), |
||||
(void*)(CFG_SERIAL1)}; |
||||
|
||||
|
||||
static void pl011_putc(int portnum, char c); |
||||
static int pl011_getc(int portnum); |
||||
static int pl011_tstc(int portnum); |
||||
|
||||
|
||||
int serial_init (void) |
||||
{ |
||||
unsigned int temp; |
||||
unsigned int divider; |
||||
unsigned int remainder; |
||||
unsigned int fraction; |
||||
|
||||
/*
|
||||
** First, disable everything. |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR, 0x0); |
||||
|
||||
/*
|
||||
** Set baud rate |
||||
** |
||||
** IBRD = UART_CLK / (16 * BAUD_RATE) |
||||
** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) |
||||
*/ |
||||
#ifdef CONFIG_VERSATILE |
||||
temp = 16 * baudRate; |
||||
divider = 24000000 / temp; |
||||
remainder = 24000000 % temp; |
||||
temp = (8 * remainder) / baudRate; |
||||
fraction = (temp >> 1) + (temp & 1); |
||||
#endif |
||||
#ifdef CONFIG_INTEGRATOR |
||||
temp = 16 * baudRate; |
||||
divider = 14745600 / temp; |
||||
remainder = 14745600 % temp; |
||||
temp = (8 * remainder) / baudRate; |
||||
fraction = (temp >> 1) + (temp & 1); |
||||
#endif |
||||
|
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL011_IBRD, divider); |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); |
||||
|
||||
/*
|
||||
** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL011_LCRH, |
||||
(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); |
||||
|
||||
/*
|
||||
** Finally, enable the UART |
||||
*/ |
||||
IO_WRITE(port[CONSOLE_PORT] + UART_PL011_CR, |
||||
(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE)); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
void |
||||
serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
pl011_putc(CONSOLE_PORT, '\r'); |
||||
|
||||
pl011_putc(CONSOLE_PORT, c); |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) { |
||||
serial_putc (*s++); |
||||
} |
||||
} |
||||
|
||||
int |
||||
serial_getc(void) |
||||
{ |
||||
return pl011_getc(CONSOLE_PORT); |
||||
} |
||||
|
||||
int |
||||
serial_tstc(void) |
||||
{ |
||||
return pl011_tstc(CONSOLE_PORT); |
||||
} |
||||
|
||||
void |
||||
serial_setbrg (void) |
||||
{ |
||||
} |
||||
|
||||
static void pl011_putc(int portnum, char c) |
||||
{ |
||||
/* Wait until there is space in the FIFO */ |
||||
while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); |
||||
|
||||
/* Send the character */ |
||||
IO_WRITE(port[portnum] + UART_PL01x_DR, c); |
||||
} |
||||
|
||||
static int pl011_getc(int portnum) |
||||
{ |
||||
unsigned int data; |
||||
|
||||
/* Wait until there is data in the FIFO */ |
||||
while (IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); |
||||
|
||||
data = IO_READ(port[portnum] + UART_PL01x_DR); |
||||
|
||||
/* Check for an error flag */ |
||||
if (data & 0xFFFFFF00) |
||||
{ |
||||
/* Clear the error */ |
||||
IO_WRITE(port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); |
||||
return -1; |
||||
} |
||||
|
||||
return (int)data; |
||||
} |
||||
|
||||
static int pl011_tstc(int portnum) |
||||
{ |
||||
return !(IO_READ(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); |
||||
} |
||||
|
||||
#endif |
@ -0,0 +1,137 @@ |
||||
/*
|
||||
* (C) Copyright 2003, 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* ARM PrimeCell UART's (PL010 & PL011)
|
||||
* ------------------------------------ |
||||
*
|
||||
* Definitions common to both PL010 & PL011 |
||||
*
|
||||
*/ |
||||
#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ |
||||
#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ |
||||
#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ |
||||
#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ |
||||
|
||||
#define UART_PL01x_RSR_OE 0x08 |
||||
#define UART_PL01x_RSR_BE 0x04 |
||||
#define UART_PL01x_RSR_PE 0x02 |
||||
#define UART_PL01x_RSR_FE 0x01 |
||||
|
||||
#define UART_PL01x_FR_TXFE 0x80 |
||||
#define UART_PL01x_FR_RXFF 0x40 |
||||
#define UART_PL01x_FR_TXFF 0x20 |
||||
#define UART_PL01x_FR_RXFE 0x10 |
||||
#define UART_PL01x_FR_BUSY 0x08 |
||||
#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) |
||||
|
||||
/*
|
||||
* PL010 definitions |
||||
*
|
||||
*/ |
||||
#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ |
||||
#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ |
||||
#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ |
||||
#define UART_PL010_CR 0x14 /* Control register. */ |
||||
#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ |
||||
#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ |
||||
#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ |
||||
|
||||
#define UART_PL010_CR_LPE (1 << 7) |
||||
#define UART_PL010_CR_RTIE (1 << 6) |
||||
#define UART_PL010_CR_TIE (1 << 5) |
||||
#define UART_PL010_CR_RIE (1 << 4) |
||||
#define UART_PL010_CR_MSIE (1 << 3) |
||||
#define UART_PL010_CR_IIRLP (1 << 2) |
||||
#define UART_PL010_CR_SIREN (1 << 1) |
||||
#define UART_PL010_CR_UARTEN (1 << 0) |
||||
|
||||
#define UART_PL010_LCRH_WLEN_8 (3 << 5) |
||||
#define UART_PL010_LCRH_WLEN_7 (2 << 5) |
||||
#define UART_PL010_LCRH_WLEN_6 (1 << 5) |
||||
#define UART_PL010_LCRH_WLEN_5 (0 << 5) |
||||
#define UART_PL010_LCRH_FEN (1 << 4) |
||||
#define UART_PL010_LCRH_STP2 (1 << 3) |
||||
#define UART_PL010_LCRH_EPS (1 << 2) |
||||
#define UART_PL010_LCRH_PEN (1 << 1) |
||||
#define UART_PL010_LCRH_BRK (1 << 0) |
||||
|
||||
|
||||
#define UART_PL010_BAUD_460800 1 |
||||
#define UART_PL010_BAUD_230400 3 |
||||
#define UART_PL010_BAUD_115200 7 |
||||
#define UART_PL010_BAUD_57600 15 |
||||
#define UART_PL010_BAUD_38400 23 |
||||
#define UART_PL010_BAUD_19200 47 |
||||
#define UART_PL010_BAUD_14400 63 |
||||
#define UART_PL010_BAUD_9600 95 |
||||
#define UART_PL010_BAUD_4800 191 |
||||
#define UART_PL010_BAUD_2400 383 |
||||
#define UART_PL010_BAUD_1200 767 |
||||
/*
|
||||
* PL011 definitions |
||||
*
|
||||
*/ |
||||
#define UART_PL011_IBRD 0x24 |
||||
#define UART_PL011_FBRD 0x28 |
||||
#define UART_PL011_LCRH 0x2C |
||||
#define UART_PL011_CR 0x30 |
||||
#define UART_PL011_IMSC 0x38 |
||||
#define UART_PL011_PERIPH_ID0 0xFE0 |
||||
|
||||
#define UART_PL011_LCRH_SPS (1 << 7) |
||||
#define UART_PL011_LCRH_WLEN_8 (3 << 5) |
||||
#define UART_PL011_LCRH_WLEN_7 (2 << 5) |
||||
#define UART_PL011_LCRH_WLEN_6 (1 << 5) |
||||
#define UART_PL011_LCRH_WLEN_5 (0 << 5) |
||||
#define UART_PL011_LCRH_FEN (1 << 4) |
||||
#define UART_PL011_LCRH_STP2 (1 << 3) |
||||
#define UART_PL011_LCRH_EPS (1 << 2) |
||||
#define UART_PL011_LCRH_PEN (1 << 1) |
||||
#define UART_PL011_LCRH_BRK (1 << 0) |
||||
|
||||
#define UART_PL011_CR_CTSEN (1 << 15) |
||||
#define UART_PL011_CR_RTSEN (1 << 14) |
||||
#define UART_PL011_CR_OUT2 (1 << 13) |
||||
#define UART_PL011_CR_OUT1 (1 << 12) |
||||
#define UART_PL011_CR_RTS (1 << 11) |
||||
#define UART_PL011_CR_DTR (1 << 10) |
||||
#define UART_PL011_CR_RXE (1 << 9) |
||||
#define UART_PL011_CR_TXE (1 << 8) |
||||
#define UART_PL011_CR_LPE (1 << 7) |
||||
#define UART_PL011_CR_IIRLP (1 << 2) |
||||
#define UART_PL011_CR_SIREN (1 << 1) |
||||
#define UART_PL011_CR_UARTEN (1 << 0) |
||||
|
||||
#define UART_PL011_IMSC_OEIM (1 << 10) |
||||
#define UART_PL011_IMSC_BEIM (1 << 9) |
||||
#define UART_PL011_IMSC_PEIM (1 << 8) |
||||
#define UART_PL011_IMSC_FEIM (1 << 7) |
||||
#define UART_PL011_IMSC_RTIM (1 << 6) |
||||
#define UART_PL011_IMSC_TXIM (1 << 5) |
||||
#define UART_PL011_IMSC_RXIM (1 << 4) |
||||
#define UART_PL011_IMSC_DSRMIM (1 << 3) |
||||
#define UART_PL011_IMSC_DCDMIM (1 << 2) |
||||
#define UART_PL011_IMSC_CTSMIM (1 << 1) |
||||
#define UART_PL011_IMSC_RIMIM (1 << 0) |
@ -0,0 +1,269 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* Configuration for Integrator AP board. |
||||
*. |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
||||
#define CONFIG_INTEGRATOR 1 /* in an Integrator board */ |
||||
#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */ |
||||
|
||||
|
||||
#define CFG_MEMTEST_START 0x100000 |
||||
#define CFG_MEMTEST_END 0x10000000 |
||||
#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */ |
||||
#define CFG_TIMERBASE 0x13000100 |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* PL010 Configuration |
||||
*/ |
||||
#define CFG_PL010_SERIAL |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
#define CFG_SERIAL0 0x16000000 |
||||
#define CFG_SERIAL1 0x17000000 |
||||
|
||||
//#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI)
|
||||
//#define CONFIG_NET_MULTI
|
||||
//#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
|
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) |
||||
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 2 |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" |
||||
#define CONFIG_BOOTCOMMAND "" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define CFG_FLASH_BASE 0x24000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ |
||||
#define CFG_MAX_FLASH_SECT 128 |
||||
#define CFG_ENV_SIZE 32768 |
||||
|
||||
#define PHYS_FLASH_1 (CFG_FLASH_BASE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI definitions |
||||
*/ |
||||
|
||||
//#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP |
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
||||
#define DEBUG |
||||
|
||||
#define CONFIG_EEPRO100 |
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
|
||||
|
||||
#define INTEGRATOR_BOOT_ROM_BASE 0x20000000 |
||||
#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
||||
|
||||
// PCI Base area
|
||||
#define INTEGRATOR_PCI_BASE 0x40000000 |
||||
#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF |
||||
|
||||
// memory map as seen by the CPU on the local bus
|
||||
#define CPU_PCI_IO_ADRS 0x60000000 // PCI I/O space base
|
||||
#define CPU_PCI_IO_SIZE 0x10000 |
||||
|
||||
#define CPU_PCI_CNFG_ADRS 0x61000000 // PCI config space
|
||||
#define CPU_PCI_CNFG_SIZE 0x1000000 |
||||
|
||||
#define PCI_MEM_BASE 0x40000000 // 512M to xxx
|
||||
// unused 256M from A0000000-AFFFFFFF might be used for I2O ???
|
||||
#define INTEGRATOR_PCI_IO_BASE 0x60000000 // 16M to xxx
|
||||
// unused (128-16)M from B1000000-B7FFFFFF
|
||||
#define PCI_CONFIG_BASE 0x61000000 // 16M to xxx
|
||||
// unused ((128-16)M - 64K) from XXX
|
||||
|
||||
#define PCI_V3_BASE 0x62000000 |
||||
|
||||
// V3 PCI bridge controller
|
||||
#define V3_BASE 0x62000000 // V360EPC registers
|
||||
|
||||
#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS) |
||||
#define PCI_ENET0_MEMADDR (PCI_MEM_BASE) |
||||
|
||||
|
||||
#define V3_PCI_VENDOR 0x00000000 |
||||
#define V3_PCI_DEVICE 0x00000002 |
||||
#define V3_PCI_CMD 0x00000004 |
||||
#define V3_PCI_STAT 0x00000006 |
||||
#define V3_PCI_CC_REV 0x00000008 |
||||
#define V3_PCI_HDR_CF 0x0000000C |
||||
#define V3_PCI_IO_BASE 0x00000010 |
||||
#define V3_PCI_BASE0 0x00000014 |
||||
#define V3_PCI_BASE1 0x00000018 |
||||
#define V3_PCI_SUB_VENDOR 0x0000002C |
||||
#define V3_PCI_SUB_ID 0x0000002E |
||||
#define V3_PCI_ROM 0x00000030 |
||||
#define V3_PCI_BPARAM 0x0000003C |
||||
#define V3_PCI_MAP0 0x00000040 |
||||
#define V3_PCI_MAP1 0x00000044 |
||||
#define V3_PCI_INT_STAT 0x00000048 |
||||
#define V3_PCI_INT_CFG 0x0000004C |
||||
#define V3_LB_BASE0 0x00000054 |
||||
#define V3_LB_BASE1 0x00000058 |
||||
#define V3_LB_MAP0 0x0000005E |
||||
#define V3_LB_MAP1 0x00000062 |
||||
#define V3_LB_BASE2 0x00000064 |
||||
#define V3_LB_MAP2 0x00000066 |
||||
#define V3_LB_SIZE 0x00000068 |
||||
#define V3_LB_IO_BASE 0x0000006E |
||||
#define V3_FIFO_CFG 0x00000070 |
||||
#define V3_FIFO_PRIORITY 0x00000072 |
||||
#define V3_FIFO_STAT 0x00000074 |
||||
#define V3_LB_ISTAT 0x00000076 |
||||
#define V3_LB_IMASK 0x00000077 |
||||
#define V3_SYSTEM 0x00000078 |
||||
#define V3_LB_CFG 0x0000007A |
||||
#define V3_PCI_CFG 0x0000007C |
||||
#define V3_DMA_PCI_ADR0 0x00000080 |
||||
#define V3_DMA_PCI_ADR1 0x00000090 |
||||
#define V3_DMA_LOCAL_ADR0 0x00000084 |
||||
#define V3_DMA_LOCAL_ADR1 0x00000094 |
||||
#define V3_DMA_LENGTH0 0x00000088 |
||||
#define V3_DMA_LENGTH1 0x00000098 |
||||
#define V3_DMA_CSR0 0x0000008B |
||||
#define V3_DMA_CSR1 0x0000009B |
||||
#define V3_DMA_CTLB_ADR0 0x0000008C |
||||
#define V3_DMA_CTLB_ADR1 0x0000009C |
||||
#define V3_DMA_DELAY 0x000000E0 |
||||
#define V3_MAIL_DATA 0x000000C0 |
||||
#define V3_PCI_MAIL_IEWR 0x000000D0 |
||||
#define V3_PCI_MAIL_IERD 0x000000D2 |
||||
#define V3_LB_MAIL_IEWR 0x000000D4 |
||||
#define V3_LB_MAIL_IERD 0x000000D6 |
||||
#define V3_MAIL_WR_STAT 0x000000D8 |
||||
#define V3_MAIL_RD_STAT 0x000000DA |
||||
#define V3_QBA_MAP 0x000000DC |
||||
|
||||
// SYSTEM register bits
|
||||
#define V3_SYSTEM_M_RST_OUT (1 << 15) |
||||
#define V3_SYSTEM_M_LOCK (1 << 14) |
||||
|
||||
// PCI_CFG bits
|
||||
#define V3_PCI_CFG_M_RETRY_EN (1 << 10) |
||||
#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) |
||||
#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) |
||||
|
||||
// PCI MAP register bits (PCI -> Local bus)
|
||||
#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 |
||||
#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) |
||||
#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) |
||||
#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) |
||||
#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 |
||||
#define V3_PCI_MAP_M_REG_EN (1 << 1) |
||||
#define V3_PCI_MAP_M_ENABLE (1 << 0) |
||||
|
||||
// 9 => 512M window size
|
||||
#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 |
||||
|
||||
// A => 1024M window size
|
||||
#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 |
||||
|
||||
// LB_BASE register bits (Local bus -> PCI)
|
||||
#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 |
||||
#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) |
||||
#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 |
||||
#define V3_LB_BASE_M_PREFETCH (1 << 3) |
||||
#define V3_LB_BASE_M_ENABLE (1 << 0) |
||||
|
||||
// PCI COMMAND REGISTER bits
|
||||
#define V3_COMMAND_M_FBB_EN (1 << 9) |
||||
#define V3_COMMAND_M_SERR_EN (1 << 8) |
||||
#define V3_COMMAND_M_PAR_EN (1 << 6) |
||||
#define V3_COMMAND_M_MASTER_EN (1 << 2) |
||||
#define V3_COMMAND_M_MEM_EN (1 << 1) |
||||
#define V3_COMMAND_M_IO_EN (1 << 0) |
||||
|
||||
#define INTEGRATOR_SC_BASE 0x11000000 |
||||
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 |
||||
#define INTEGRATOR_SC_PCIENABLE \ |
||||
(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,131 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* Configuration for Compact Integrator board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
||||
#define CONFIG_INTEGRATOR 1 /* in an Integrator board */ |
||||
#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */ |
||||
|
||||
|
||||
#define CFG_MEMTEST_START 0x100000 |
||||
#define CFG_MEMTEST_END 0x10000000 |
||||
#define CFG_HZ (1000000 / 256) /* Timer 1 is clocked at 1Mhz, with 256 divider */ |
||||
#define CFG_TIMERBASE 0x13000100 |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_DRIVER_SMC91111 |
||||
#define CONFIG_SMC_USE_32_BIT |
||||
#define CONFIG_SMC91111_BASE 0xC8000000 |
||||
#undef CONFIG_SMC91111_EXT_PHY |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_PL011_SERIAL |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
#define CFG_SERIAL0 0x16000000 |
||||
#define CFG_SERIAL1 0x17000000 |
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY) |
||||
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 2 |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" |
||||
#define CONFIG_BOOTCOMMAND "bootp ; bootm" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define CFG_FLASH_BASE 0x24000000 |
||||
#define PHYS_FLASH_1 (CFG_FLASH_BASE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ |
||||
#define CFG_MAX_FLASH_SECT 128 |
||||
#define CFG_ENV_SIZE 32768 |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,165 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* ARM Ltd. |
||||
* Philippe Robin, <philippe.robin@arm.com> |
||||
* Configuration for Versatile PB. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
||||
#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ |
||||
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ |
||||
|
||||
|
||||
#define CFG_MEMTEST_START 0x100000 |
||||
#define CFG_MEMTEST_END 0x10000000 |
||||
#define CFG_HZ (1000000 / 256) |
||||
#define CFG_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ |
||||
|
||||
#define CFG_TIMER_INTERVAL 10000 |
||||
#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL >> 4) /* Divide by 16 */ |
||||
#define CFG_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ |
||||
|
||||
/*
|
||||
* control registers |
||||
*/ |
||||
#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ |
||||
|
||||
/*
|
||||
* System controller bit assignment |
||||
*/ |
||||
#define VERSATILE_REFCLK 0 |
||||
#define VERSATILE_TIMCLK 1 |
||||
|
||||
#define VERSATILE_TIMER1_EnSel 15 |
||||
#define VERSATILE_TIMER2_EnSel 17 |
||||
#define VERSATILE_TIMER3_EnSel 19 |
||||
#define VERSATILE_TIMER4_EnSel 21 |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
#define CONFIG_DRIVER_SMC91111 |
||||
#define CONFIG_SMC_USE_32_BIT |
||||
#define CONFIG_SMC91111_BASE 0x10010000 |
||||
#undef CONFIG_SMC91111_EXT_PHY |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_PL011_SERIAL |
||||
#define CONFIG_CONS_INDEX 0 |
||||
#define CONFIG_BAUDRATE 38400 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
#define CFG_SERIAL0 0x101F1000 |
||||
#define CFG_SERIAL1 0x101F2000 |
||||
|
||||
#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY) |
||||
|
||||
//#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
|
||||
|
||||
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 2 |
||||
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0" |
||||
//#define CONFIG_BOOTCOMMAND "bootp ; bootm"
|
||||
|
||||
/*
|
||||
* Static configuration when assigning fixed address |
||||
*/ |
||||
//#define CONFIG_NETMASK 255.255.255.0 /* talk on MY local net */
|
||||
//#define CONFIG_IPADDR xx.xx.xx.xx /* static IP I currently own */
|
||||
//#define CONFIG_SERVERIP xx.xx.xx.xx /* current IP of my dev pc */
|
||||
#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "Versatile # " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
||||
|
||||
#define CFG_FLASH_BASE 0x34000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ |
||||
/* timeout values are in ticks */ |
||||
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ |
||||
#define CFG_MAX_FLASH_SECT 128 |
||||
#define CFG_ENV_SIZE 32768 |
||||
|
||||
#define PHYS_FLASH_1 (CFG_FLASH_BASE) |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue