The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>master
Khoronzhuk, Ivan
10 years ago
committed by
Tom Rini
parent
99907176a0
commit
3e01ed00da
@ -1,72 +0,0 @@ |
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _EMIF_DEFS_H_ |
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#define _EMIF_DEFS_H_ |
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#include <asm/arch/hardware.h> |
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struct davinci_emif_regs { |
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u_int32_t ercsr; |
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u_int32_t awccr; |
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u_int32_t sdbcr; |
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u_int32_t sdrcr; |
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u_int32_t ab1cr; |
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u_int32_t ab2cr; |
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u_int32_t ab3cr; |
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u_int32_t ab4cr; |
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u_int32_t sdtimr; |
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u_int32_t ddrsr; |
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u_int32_t ddrphycr; |
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u_int32_t ddrphysr; |
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u_int32_t totar; |
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u_int32_t totactr; |
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u_int32_t ddrphyid_rev; |
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u_int32_t sdsretr; |
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u_int32_t eirr; |
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u_int32_t eimr; |
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u_int32_t eimsr; |
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u_int32_t eimcr; |
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u_int32_t ioctrlr; |
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u_int32_t iostatr; |
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u_int8_t rsvd0[8]; |
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u_int32_t nandfcr; |
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u_int32_t nandfsr; |
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u_int8_t rsvd1[8]; |
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u_int32_t nandfecc[4]; |
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u_int8_t rsvd2[60]; |
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u_int32_t nand4biteccload; |
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u_int32_t nand4bitecc[4]; |
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u_int32_t nanderradd1; |
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u_int32_t nanderradd2; |
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u_int32_t nanderrval1; |
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u_int32_t nanderrval2; |
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}; |
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#define davinci_emif_regs \ |
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((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) |
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#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) |
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) |
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) |
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#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) |
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#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) |
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#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) |
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#define DAVINCI_NANDFCR_CS2NAND (1 << 0) |
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/* Chip Select setup */ |
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#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) |
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#define DAVINCI_ABCR_EXT_WAIT (1 << 30) |
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#define DAVINCI_ABCR_WSETUP(n) (n << 26) |
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#define DAVINCI_ABCR_WSTROBE(n) (n << 20) |
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#define DAVINCI_ABCR_WHOLD(n) (n << 17) |
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#define DAVINCI_ABCR_RSETUP(n) (n << 13) |
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#define DAVINCI_ABCR_RSTROBE(n) (n << 7) |
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#define DAVINCI_ABCR_RHOLD(n) (n << 4) |
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#define DAVINCI_ABCR_TA(n) (n << 2) |
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#define DAVINCI_ABCR_ASIZE_16BIT 1 |
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#define DAVINCI_ABCR_ASIZE_8BIT 0 |
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#endif |
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@ -1,38 +0,0 @@ |
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* Parts shamelesly stolen from Linux Kernel source tree. |
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* |
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* ------------------------------------------------------------ |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _NAND_DEFS_H_ |
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#define _NAND_DEFS_H_ |
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#include <asm/arch/hardware.h> |
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#ifdef CONFIG_SOC_DM646X |
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#define MASK_CLE 0x80000 |
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#define MASK_ALE 0x40000 |
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#else |
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#define MASK_CLE 0x10 |
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#define MASK_ALE 0x08 |
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#endif |
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#ifdef CONFIG_SYS_NAND_MASK_CLE |
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#undef MASK_CLE |
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#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE |
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#endif |
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#ifdef CONFIG_SYS_NAND_MASK_ALE |
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#undef MASK_ALE |
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#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE |
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#endif |
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#define NAND_READ_START 0x00 |
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#define NAND_READ_END 0x30 |
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#define NAND_STATUS 0x70 |
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extern void davinci_nand_init(struct nand_chip *nand); |
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#endif |
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@ -1,23 +0,0 @@ |
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/*
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* nand driver definitions to re-use davinci nand driver on Keystone2 |
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* |
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* (C) Copyright 2012-2014 |
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* Texas Instruments Incorporated, <www.ti.com> |
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* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _NAND_DEFS_H_ |
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#define _NAND_DEFS_H_ |
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#include <asm/arch/hardware.h> |
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#include <linux/mtd/nand.h> |
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#define MASK_CLE 0x4000 |
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#define MASK_ALE 0x2000 |
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#define NAND_READ_START 0x00 |
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#define NAND_READ_END 0x30 |
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#define NAND_STATUS 0x70 |
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#endif |
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@ -1 +0,0 @@ |
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#include <asm/arch-davinci/emif_defs.h> |
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@ -1,23 +0,0 @@ |
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/*
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* TNETV107X: NAND definitions |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _NAND_DEFS_H_ |
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#define _NAND_DEFS_H_ |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/emif_defs.h> |
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE |
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#define MASK_CLE 0x4000 |
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#define MASK_ALE 0x2000 |
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#define NAND_READ_START 0x00 |
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#define NAND_READ_END 0x30 |
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#define NAND_STATUS 0x70 |
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extern void davinci_nand_init(struct nand_chip *nand); |
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#endif |
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