@ -273,11 +273,13 @@
* General PCI
* Addresses are mapped 1 - 1.
*/
# define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
# define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
# define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
# define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
# define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
# define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
# define CONFIG_SYS_PCI1_IO_BASE 0x0 0000000
# define CONFIG_SYS_PCI1_IO_BUS 0x 0000000
# define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
# define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
# define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
/* For RTL8139 */
@ -285,18 +287,18 @@
# define _IO_BASE 0x00000000
/* controller 1, Base address 0xa000 */
# define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
# define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
# define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
# define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
# define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
# define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
# define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
# define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
# define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
/* controller 2, Base Address 0x9000 */
# define CONFIG_SYS_PCIE2_MEM_BASE 0x90000000
# define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
# define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
# define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
# define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
# define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */
# define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
# define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
# define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
@ -364,7 +366,7 @@
# define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE )
# define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
# define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
# define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
# define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
@ -375,7 +377,7 @@
# define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE )
# define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
# define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
# define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
# define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U