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Merge git://git.denx.de/u-boot-spi

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master
Tom Rini 7 years ago
parent 78cb000b84 1050998728
commit 3efd018954
4 changed files with 191 additions and 45 deletions
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  1. 5
      drivers/mtd/spi/spi_flash_ids.c
  2. 46
      drivers/spi/fsl_qspi.c
  3. 4
      drivers/spi/fsl_qspi.h
  4. 181
      drivers/spi/mxc_spi.c

5
drivers/mtd/spi/spi_flash_ids.c
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@ -92,7 +92,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) },
{"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) },
{"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) },
{"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 128, 0) },
{"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) },
{"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) },
{"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) },
{"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) },
@ -101,8 +101,8 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) },
{"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) },
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) },
{"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) },
{"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
{"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) },
{"s25fs512s", INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) },
{"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) },
@ -135,6 +135,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
{"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
{"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) },
{"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_SST /* SST */
{"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) },

46
drivers/spi/fsl_qspi.c
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@ -14,6 +14,7 @@
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
#include <wait_bit.h>
#include "fsl_qspi.h"
DECLARE_GLOBAL_DATA_PTR;
@ -663,22 +664,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
tx_size = (len > TX_BUFFER_SIZE) ?
TX_BUFFER_SIZE : len;
size = tx_size / 4;
for (i = 0; i < size; i++) {
size = tx_size / 16;
/*
* There must be atleast 128bit data
* available in TX FIFO for any pop operation
*/
if (tx_size % 16)
size++;
for (i = 0; i < size * 4; i++) {
memcpy(&data, txbuf, 4);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, &regs->tbdr, data);
txbuf += 4;
}
size = tx_size % 4;
if (size) {
data = 0;
memcpy(&data, txbuf, size);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, &regs->tbdr, data);
}
qspi_write32(priv->flags, &regs->ipcr,
(seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
@ -991,7 +990,7 @@ static int fsl_qspi_probe(struct udevice *bus)
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
int i;
int i, ret;
dm_spi_bus = bus->uclass_priv;
@ -1011,6 +1010,18 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
/* make sure controller is not busy anywhere */
ret = wait_for_bit(__func__, &priv->regs->sr,
QSPI_SR_BUSY_MASK |
QSPI_SR_AHB_ACC_MASK |
QSPI_SR_IP_ACC_MASK,
false, 100, false);
if (ret) {
debug("ERROR : The controller is busy\n");
return ret;
}
mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
qspi_write32(priv->flags, &priv->regs->mcr,
QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
@ -1156,10 +1167,23 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
struct fsl_qspi_priv *priv;
struct udevice *bus;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
int ret;
bus = dev->parent;
priv = dev_get_priv(bus);
/* make sure controller is not busy anywhere */
ret = wait_for_bit(__func__, &priv->regs->sr,
QSPI_SR_BUSY_MASK |
QSPI_SR_AHB_ACC_MASK |
QSPI_SR_IP_ACC_MASK,
false, 100, false);
if (ret) {
debug("ERROR : The controller is busy\n");
return ret;
}
priv->cur_amba_base = priv->amba_base[slave_plat->cs];
qspi_module_disable(priv, 0);

4
drivers/spi/fsl_qspi.h
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@ -105,6 +105,10 @@ struct fsl_qspi_regs {
#define QSPI_RBCT_RXBRD_SHIFT 8
#define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
#define QSPI_SR_AHB_ACC_SHIFT 2
#define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT)
#define QSPI_SR_IP_ACC_SHIFT 1
#define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT)
#define QSPI_SR_BUSY_SHIFT 0
#define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)

181
drivers/spi/mxc_spi.c
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@ -5,6 +5,7 @@
*/
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <spi.h>
#include <linux/errno.h>
@ -14,6 +15,8 @@
#include <asm/arch/clock.h>
#include <asm/mach-imx/spi.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
* datasheet, the correct one is in the Freescale's Linux driver */
@ -22,10 +25,6 @@
"See linux mxc_spi driver from Freescale for details."
#endif
static unsigned long spi_bases[] = {
MXC_SPI_BASE_ADDRESSES
};
__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return -1;
@ -51,6 +50,7 @@ struct mxc_spi_slave {
int ss_pol;
unsigned int max_hz;
unsigned int mode;
struct gpio_desc ss;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@ -58,19 +58,24 @@ static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
return container_of(slave, struct mxc_spi_slave, slave);
}
void spi_cs_activate(struct spi_slave *slave)
static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio, mxcs->ss_pol);
if (CONFIG_IS_ENABLED(DM_SPI)) {
dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol);
} else {
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio, mxcs->ss_pol);
}
}
void spi_cs_deactivate(struct spi_slave *slave)
static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio,
!(mxcs->ss_pol));
if (CONFIG_IS_ENABLED(DM_SPI)) {
dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol));
} else {
if (mxcs->gpio > 0)
gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
}
}
u32 get_cspi_div(u32 div)
@ -211,10 +216,9 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
}
#endif
int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
const u8 *dout, u8 *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
int nbytes = DIV_ROUND_UP(bitlen, 8);
u32 data, cnt, i;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
@ -327,8 +331,9 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
int n_bytes = DIV_ROUND_UP(bitlen, 8);
int n_bits;
@ -337,11 +342,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
u8 *p_outbuf = (u8 *)dout;
u8 *p_inbuf = (u8 *)din;
if (!slave)
return -1;
if (!mxcs)
return -EINVAL;
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
mxc_spi_cs_activate(mxcs);
while (n_bytes > 0) {
if (n_bytes < MAX_SPI_BYTES)
@ -351,7 +356,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
n_bits = blk_size * 8;
ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
if (ret)
return ret;
@ -363,12 +368,39 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
}
if (flags & SPI_XFER_END) {
spi_cs_deactivate(slave);
mxc_spi_cs_deactivate(mxcs);
}
return 0;
}
static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
{
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
int ret;
reg_write(&regs->rxdata, 1);
udelay(1);
ret = spi_cfg_mxc(mxcs, cs);
if (ret) {
printf("mxc_spi: cannot setup SPI controller\n");
return ret;
}
reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
reg_write(&regs->intr, 0);
return 0;
}
#ifndef CONFIG_DM_SPI
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}
void spi_init(void)
{
}
@ -390,6 +422,7 @@ static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
if (mxcs->gpio == -1)
return 0;
gpio_request(mxcs->gpio, "spi-cs");
ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
if (ret) {
printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
@ -399,6 +432,10 @@ static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
return 0;
}
static unsigned long spi_bases[] = {
MXC_SPI_BASE_ADDRESSES
};
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
@ -443,24 +480,104 @@ void spi_free_slave(struct spi_slave *slave)
int spi_claim_bus(struct spi_slave *slave)
{
int ret;
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
reg_write(&regs->rxdata, 1);
udelay(1);
ret = spi_cfg_mxc(mxcs, slave->cs);
return mxc_spi_claim_bus_internal(mxcs, slave->cs);
}
void spi_release_bus(struct spi_slave *slave)
{
/* TODO: Shut the controller down */
}
#else
static int mxc_spi_probe(struct udevice *bus)
{
struct mxc_spi_slave *plat = bus->platdata;
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
int ret;
if (gpio_request_by_name(bus, "cs-gpios", 0, &plat->ss,
GPIOD_IS_OUT)) {
dev_err(bus, "No cs-gpios property\n");
return -EINVAL;
}
plat->base = dev_get_addr(bus);
if (plat->base == FDT_ADDR_T_NONE)
return -ENODEV;
ret = dm_gpio_set_value(&plat->ss, !(mxcs->ss_pol));
if (ret) {
printf("mxc_spi: cannot setup SPI controller\n");
dev_err(bus, "Setting cs error\n");
return ret;
}
reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
reg_write(&regs->intr, 0);
mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
20000000);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
/* TODO: Shut the controller down */
struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
}
static int mxc_spi_claim_bus(struct udevice *dev)
{
struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
}
static int mxc_spi_release_bus(struct udevice *dev)
{
return 0;
}
static int mxc_spi_set_speed(struct udevice *bus, uint speed)
{
/* Nothing to do */
return 0;
}
static int mxc_spi_set_mode(struct udevice *bus, uint mode)
{
struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
mxcs->mode = mode;
mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
return 0;
}
static const struct dm_spi_ops mxc_spi_ops = {
.claim_bus = mxc_spi_claim_bus,
.release_bus = mxc_spi_release_bus,
.xfer = mxc_spi_xfer,
.set_speed = mxc_spi_set_speed,
.set_mode = mxc_spi_set_mode,
};
static const struct udevice_id mxc_spi_ids[] = {
{ .compatible = "fsl,imx51-ecspi" },
{ }
};
U_BOOT_DRIVER(mxc_spi) = {
.name = "mxc_spi",
.id = UCLASS_SPI,
.of_match = mxc_spi_ids,
.ops = &mxc_spi_ops,
.platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
.probe = mxc_spi_probe,
};
#endif

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