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@ -17,8 +17,10 @@ |
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#include <generic-phy.h> |
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#ifdef CONFIG_SUNXI_GEN_SUN4I |
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#define BASE_DIST 0x8000 |
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#define AHB_CLK_DIST 2 |
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#else |
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#define BASE_DIST 0x1000 |
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#define AHB_CLK_DIST 1 |
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#endif |
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@ -33,9 +35,9 @@ struct ohci_sunxi_cfg { |
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}; |
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struct ohci_sunxi_priv { |
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ohci_t ohci; |
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struct sunxi_ccm_reg *ccm; |
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u32 *reset0_cfg; |
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ohci_t ohci; |
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ |
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int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */ |
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struct phy phy; |
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@ -48,6 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) |
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struct ohci_sunxi_priv *priv = dev_get_priv(dev); |
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struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); |
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int extra_ahb_gate_mask = 0; |
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u8 reg_mask = 0; |
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int phys, ret; |
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priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev); |
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@ -89,12 +92,13 @@ no_phy: |
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* This should go away once we've moved to the driver model for |
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* clocks resp. phys. |
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*/ |
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reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; |
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priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; |
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extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; |
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priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; |
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priv->ahb_gate_mask <<= phys * AHB_CLK_DIST; |
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extra_ahb_gate_mask <<= phys * AHB_CLK_DIST; |
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priv->usb_gate_mask <<= phys; |
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priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; |
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extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; |
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priv->usb_gate_mask <<= reg_mask; |
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setbits_le32(&priv->ccm->ahb_gate0, |
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priv->ahb_gate_mask | extra_ahb_gate_mask); |
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