The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>master
SRICHARAN R
12 years ago
committed by
Tom Rini
parent
ee9447bfe3
commit
3fcdd4a5f8
@ -1,123 +0,0 @@ |
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/*
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* |
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* Clock initialization for OMAP4 |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* |
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* Based on previous work by: |
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* Santosh Shilimkar <santosh.shilimkar@ti.com> |
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* Rajendra Nayak <rnayak@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/omap_common.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/clocks.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/utils.h> |
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#include <asm/omap_gpio.h> |
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|
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#ifndef CONFIG_SPL_BUILD |
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/*
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* printing to console doesn't work unless |
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* this code is executed from SPL |
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*/ |
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#define printf(fmt, args...) |
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#define puts(s) |
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#endif /* !CONFIG_SPL_BUILD */ |
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|
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
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* We set the maximum voltages allowed here because Smart-Reflex is not |
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* enabled in bootloader. Voltage initialization in the kernel will set |
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* these to the nominal values after enabling Smart-Reflex |
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*/ |
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void scale_vcores(void) |
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{ |
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u32 volt, omap_rev; |
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); |
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omap_rev = omap_revision(); |
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/*
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* Scale Voltage rails: |
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* 1. VDD_CORE |
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* 3. VDD_MPU |
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* 3. VDD_IVA |
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*/ |
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if (omap_rev < OMAP4460_ES1_0) { |
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/*
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* OMAP4430: |
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* VDD_CORE = TWL6030 VCORE3 |
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* VDD_MPU = TWL6030 VCORE1 |
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* VDD_IVA = TWL6030 VCORE2 |
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*/ |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); |
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|
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/*
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* note on VDD_MPU: |
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* Setting a high voltage for Nitro mode as smart reflex is not |
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* enabled. We use the maximum possible value in the AVS range |
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* because the next higher voltage in the discrete range |
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* (code >= 0b111010) is way too high. |
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*/ |
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volt = 1325; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
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} else { |
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/*
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* OMAP4460: |
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* VDD_CORE = TWL6030 VCORE1 |
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* VDD_MPU = TPS62361 |
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* VDD_IVA = TWL6030 VCORE2 |
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*/ |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); |
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/* TPS62361 */ |
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volt = 1203; |
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do_scale_tps62361(TPS62361_VSEL0_GPIO, |
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TPS62361_REG_ADDR_SET1, volt); |
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/* VCORE 2 - supplies vdd_iva */ |
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volt = 1200; |
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do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); |
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} |
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} |
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|
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u32 get_offset_code(u32 offset) |
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{ |
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u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ |
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if (omap_revision() == OMAP4430_ES1_0) |
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offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; |
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else |
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offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; |
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offset_code = (offset + step - 1) / step; |
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/* The code starts at 1 not 0 */ |
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return ++offset_code; |
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} |
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@ -1,98 +0,0 @@ |
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/*
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* |
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* Clock initialization for OMAP5 |
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* |
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* (C) Copyright 2010 |
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* Texas Instruments, <www.ti.com> |
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* |
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* Aneesh V <aneesh@ti.com> |
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* Sricharan R <r.sricharan@ti.com> |
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* |
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* Based on previous work by: |
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* Santosh Shilimkar <santosh.shilimkar@ti.com> |
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* Rajendra Nayak <rnayak@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/omap_common.h> |
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#include <asm/arch/clocks.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/utils.h> |
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#include <asm/omap_gpio.h> |
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#include <asm/emif.h> |
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|
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#ifndef CONFIG_SPL_BUILD |
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/*
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* printing to console doesn't work unless |
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* this code is executed from SPL |
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*/ |
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#define printf(fmt, args...) |
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#define puts(s) |
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#endif |
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|
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/*
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* Setup the voltages for vdd_mpu, vdd_core, and vdd_iva |
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* We set the maximum voltages allowed here because Smart-Reflex is not |
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* enabled in bootloader. Voltage initialization in the kernel will set |
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* these to the nominal values after enabling Smart-Reflex |
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*/ |
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void scale_vcores(void) |
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{ |
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u32 volt_core, volt_mpu, volt_mm; |
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omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); |
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/* Palmas settings */ |
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if (omap_revision() != OMAP5432_ES1_0) { |
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volt_core = VDD_CORE; |
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volt_mpu = VDD_MPU; |
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volt_mm = VDD_MM; |
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} else { |
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volt_core = VDD_CORE_5432; |
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volt_mpu = VDD_MPU_5432; |
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volt_mm = VDD_MM_5432; |
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} |
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do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); |
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do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); |
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do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); |
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if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { |
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/* Configure LDO SRAM "magic" bits */ |
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writel(2, (*prcm)->prm_sldo_core_setup); |
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writel(2, (*prcm)->prm_sldo_mpu_setup); |
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writel(2, (*prcm)->prm_sldo_mm_setup); |
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} |
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} |
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u32 get_offset_code(u32 volt_offset) |
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{ |
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u32 offset_code, step = 10000; /* 10 mV represented in uV */ |
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volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; |
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offset_code = (volt_offset + step - 1) / step; |
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/*
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* Offset codes 1-6 all give the base voltage in Palmas |
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* Offset code 0 switches OFF the SMPS |
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*/ |
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return offset_code + 6; |
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} |
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