Add KB9202 NAND driver Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: Scott Wood <scottwood@freescale.com>master
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/*
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* (C) Copyright 2006 |
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* KwikByte <kb9200_dev@kwikbyte.com> |
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* |
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* (C) Copyright 2009 |
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* Matthias Kaehlcke <matthias@kaehlcke.net> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/AT91RM9200.h> |
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#include <asm/arch/hardware.h> |
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#include <nand.h> |
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/*
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* hardware specific access to control-lines |
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*/ |
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#define MASK_ALE (1 << 22) /* our ALE is A22 */ |
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#define MASK_CLE (1 << 21) /* our CLE is A21 */ |
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#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ |
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#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ |
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#define KB9202_SMC2_NWS (1 << 2) |
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#define KB9202_SMC2_TDF (1 << 8) |
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#define KB9202_SMC2_RWSETUP (1 << 24) |
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#define KB9202_SMC2_RWHOLD (1 << 29) |
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/*
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* Board-specific function to access device control signals |
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*/ |
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static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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{ |
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struct nand_chip *this = mtd->priv; |
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if (ctrl & NAND_CTRL_CHANGE) { |
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
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/* clear ALE and CLE bits */ |
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IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); |
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if (ctrl & NAND_CLE) |
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IO_ADDR_W |= MASK_CLE; |
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if (ctrl & NAND_ALE) |
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IO_ADDR_W |= MASK_ALE; |
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this->IO_ADDR_W = (void *) IO_ADDR_W; |
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if (ctrl & NAND_NCE) |
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writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); |
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else |
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writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); |
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} |
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if (cmd != NAND_CMD_NONE) |
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writeb(cmd, this->IO_ADDR_W); |
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} |
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/*
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* Board-specific function to access the device ready signal. |
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*/ |
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static int kb9202_nand_ready(struct mtd_info *mtd) |
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{ |
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return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; |
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} |
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/*
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* Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. |
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* |
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* struct nand_chip - NAND Private Flash Chip Data |
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device |
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device |
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* @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines |
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line |
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* If set to NULL no access to ready/busy is available and the ready/busy information |
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* is read from the chip status register |
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* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only |
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* be provided if a hardware ECC is available |
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* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines |
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) |
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* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about |
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* special functionality. See the defines for further explanation |
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*/ |
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/*
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* This routine initializes controller and GPIOs. |
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*/ |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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unsigned int value; |
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nand->ecc.mode = NAND_ECC_SOFT; |
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nand->cmd_ctrl = kb9202_nand_hwcontrol; |
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nand->dev_ready = kb9202_nand_ready; |
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/* in case running outside of bootloader */ |
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writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); |
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/* setup nand flash access (allow ample margin) */ |
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/* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ |
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writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | |
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AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, |
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AT91C_SMC_CSR3); |
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/* enable internal NAND controller */ |
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value = readl(AT91C_EBI_CSA); |
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value |= AT91C_EBI_CS3A_SMC_SmartMedia; |
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writel(value, AT91C_EBI_CSA); |
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/* enable SMOE/SMWE */ |
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writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); |
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writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); |
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writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); |
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/* set NCE to high */ |
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writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); |
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/* disable output on pin connected to the busy line of the NAND */ |
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writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); |
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/* enable the PIO to control NCE and BUSY */ |
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writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); |
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/* enable output for NCE */ |
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writel(KB9202_NAND_NCE, AT91C_PIOC_OER); |
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return (0); |
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} |
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