Tom Rini
6 years ago
commit
40df6b3e18
@ -0,0 +1,381 @@ |
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/* |
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* Copyright (C) 2018 Intel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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/dts-v1/; |
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#include <dt-bindings/reset/altr,rst-mgr-s10.h> |
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#include <dt-bindings/gpio/gpio.h> |
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|
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/ { |
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compatible = "altr,socfpga-stratix10"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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|
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x0>; |
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}; |
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|
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x1>; |
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}; |
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|
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x2>; |
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}; |
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|
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x3>; |
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}; |
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}; |
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|
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <0 120 8>, |
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<0 121 8>, |
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<0 122 8>, |
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<0 123 8>; |
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interrupt-affinity = <&cpu0>, |
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<&cpu1>, |
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<&cpu2>, |
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<&cpu3>; |
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interrupt-parent = <&intc>; |
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}; |
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|
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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|
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intc: intc@fffc1000 { |
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compatible = "arm,gic-400", "arm,cortex-a15-gic"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x0 0xfffc1000 0x0 0x1000>, |
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<0x0 0xfffc2000 0x0 0x2000>, |
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<0x0 0xfffc4000 0x0 0x2000>, |
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<0x0 0xfffc6000 0x0 0x2000>; |
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}; |
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|
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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device_type = "soc"; |
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interrupt-parent = <&intc>; |
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ranges = <0 0 0 0xffffffff>; |
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|
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clkmgr@ffd1000 { |
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compatible = "altr,clk-mgr"; |
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reg = <0xffd10000 0x1000>; |
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}; |
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|
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gmac0: ethernet@ff800000 { |
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
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reg = <0xff800000 0x2000>; |
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interrupts = <0 90 4>; |
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interrupt-names = "macirq"; |
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mac-address = [00 00 00 00 00 00]; |
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resets = <&rst EMAC0_RESET>; |
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reset-names = "stmmaceth"; |
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status = "disabled"; |
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}; |
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|
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gmac1: ethernet@ff802000 { |
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
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reg = <0xff802000 0x2000>; |
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interrupts = <0 91 4>; |
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interrupt-names = "macirq"; |
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mac-address = [00 00 00 00 00 00]; |
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resets = <&rst EMAC1_RESET>; |
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reset-names = "stmmaceth"; |
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status = "disabled"; |
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}; |
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|
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gmac2: ethernet@ff804000 { |
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; |
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reg = <0xff804000 0x2000>; |
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interrupts = <0 92 4>; |
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interrupt-names = "macirq"; |
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mac-address = [00 00 00 00 00 00]; |
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resets = <&rst EMAC2_RESET>; |
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reset-names = "stmmaceth"; |
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status = "disabled"; |
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}; |
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|
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gpio0: gpio@ffc03200 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0xffc03200 0x100>; |
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resets = <&rst GPIO0_RESET>; |
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status = "disabled"; |
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porta: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <24>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <0 110 4>; |
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}; |
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}; |
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gpio1: gpio@ffc03300 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0xffc03300 0x100>; |
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resets = <&rst GPIO1_RESET>; |
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status = "disabled"; |
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portb: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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snps,nr-gpios = <24>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <0 111 4>; |
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}; |
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}; |
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i2c0: i2c@ffc02800 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xffc02800 0x100>; |
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interrupts = <0 103 4>; |
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resets = <&rst I2C0_RESET>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@ffc02900 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xffc02900 0x100>; |
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interrupts = <0 104 4>; |
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resets = <&rst I2C1_RESET>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@ffc02a00 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xffc02a00 0x100>; |
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interrupts = <0 105 4>; |
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resets = <&rst I2C2_RESET>; |
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status = "disabled"; |
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}; |
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i2c3: i2c@ffc02b00 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xffc02b00 0x100>; |
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interrupts = <0 106 4>; |
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resets = <&rst I2C3_RESET>; |
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status = "disabled"; |
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}; |
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i2c4: i2c@ffc02c00 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,designware-i2c"; |
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reg = <0xffc02c00 0x100>; |
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interrupts = <0 107 4>; |
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resets = <&rst I2C4_RESET>; |
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status = "disabled"; |
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}; |
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mmc: dwmmc0@ff808000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "altr,socfpga-dw-mshc"; |
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reg = <0xff808000 0x1000>; |
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interrupts = <0 96 4>; |
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fifo-depth = <0x400>; |
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resets = <&rst SDMMC_RESET>; |
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reset-names = "reset"; |
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status = "disabled"; |
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}; |
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ocram: sram@ffe00000 { |
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compatible = "mmio-sram"; |
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reg = <0xffe00000 0x100000>; |
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}; |
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rst: rstmgr@ffd11000 { |
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#reset-cells = <1>; |
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compatible = "altr,rst-mgr"; |
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reg = <0xffd11000 0x1000>; |
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altr,modrst-offset = <0x20>; |
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}; |
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spi0: spi@ffda4000 { |
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compatible = "snps,dw-apb-ssi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xffda4000 0x1000>; |
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interrupts = <0 99 4>; |
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resets = <&rst SPIM0_RESET>; |
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reg-io-width = <4>; |
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num-chipselect = <4>; |
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bus-num = <0>; |
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status = "disabled"; |
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}; |
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spi1: spi@ffda5000 { |
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compatible = "snps,dw-apb-ssi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xffda5000 0x1000>; |
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interrupts = <0 100 4>; |
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resets = <&rst SPIM1_RESET>; |
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reg-io-width = <4>; |
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num-chipselect = <4>; |
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bus-num = <0>; |
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status = "disabled"; |
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}; |
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sysmgr: sysmgr@ffd12000 { |
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compatible = "altr,sys-mgr", "syscon"; |
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reg = <0xffd12000 0x1000>; |
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}; |
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/* Local timer */ |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 0xf08>, |
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<1 14 0xf08>, |
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<1 11 0xf08>, |
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<1 10 0xf08>; |
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}; |
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timer0: timer0@ffc03000 { |
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compatible = "snps,dw-apb-timer"; |
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interrupts = <0 113 4>; |
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reg = <0xffc03000 0x100>; |
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}; |
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timer1: timer1@ffc03100 { |
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compatible = "snps,dw-apb-timer"; |
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interrupts = <0 114 4>; |
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reg = <0xffc03100 0x100>; |
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}; |
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timer2: timer2@ffd00000 { |
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compatible = "snps,dw-apb-timer"; |
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interrupts = <0 115 4>; |
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reg = <0xffd00000 0x100>; |
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}; |
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timer3: timer3@ffd00100 { |
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compatible = "snps,dw-apb-timer"; |
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interrupts = <0 116 4>; |
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reg = <0xffd00100 0x100>; |
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}; |
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uart0: serial0@ffc02000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xffc02000 0x100>; |
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interrupts = <0 108 4>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst UART0_RESET>; |
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status = "disabled"; |
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}; |
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uart1: serial1@ffc02100 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0xffc02100 0x100>; |
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interrupts = <0 109 4>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst UART1_RESET>; |
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status = "disabled"; |
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}; |
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usbphy0: usbphy@0 { |
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#phy-cells = <0>; |
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compatible = "usb-nop-xceiv"; |
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status = "okay"; |
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}; |
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usb0: usb@ffb00000 { |
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compatible = "snps,dwc2"; |
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reg = <0xffb00000 0x40000>; |
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interrupts = <0 93 4>; |
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phys = <&usbphy0>; |
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phy-names = "usb2-phy"; |
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resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; |
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reset-names = "dwc2", "dwc2-ecc"; |
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status = "disabled"; |
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}; |
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usb1: usb@ffb40000 { |
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compatible = "snps,dwc2"; |
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reg = <0xffb40000 0x40000>; |
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interrupts = <0 94 4>; |
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phys = <&usbphy0>; |
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phy-names = "usb2-phy"; |
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resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; |
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reset-names = "dwc2", "dwc2-ecc"; |
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status = "disabled"; |
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}; |
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watchdog0: watchdog@ffd00200 { |
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compatible = "snps,dw-wdt"; |
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reg = <0xffd00200 0x100>; |
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interrupts = <0 117 4>; |
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resets = <&rst WATCHDOG0_RESET>; |
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status = "disabled"; |
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}; |
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watchdog1: watchdog@ffd00300 { |
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compatible = "snps,dw-wdt"; |
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reg = <0xffd00300 0x100>; |
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interrupts = <0 118 4>; |
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resets = <&rst WATCHDOG1_RESET>; |
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status = "disabled"; |
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}; |
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watchdog2: watchdog@ffd00400 { |
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compatible = "snps,dw-wdt"; |
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reg = <0xffd00400 0x100>; |
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interrupts = <0 125 4>; |
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resets = <&rst WATCHDOG2_RESET>; |
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status = "disabled"; |
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}; |
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watchdog3: watchdog@ffd00500 { |
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compatible = "snps,dw-wdt"; |
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reg = <0xffd00500 0x100>; |
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interrupts = <0 126 4>; |
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resets = <&rst WATCHDOG3_RESET>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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@ -0,0 +1,92 @@ |
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/* |
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* Copyright (C) 2018 Intel Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include "socfpga_stratix10.dtsi" |
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/ { |
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model = "SoCFPGA Stratix 10 SoCDK"; |
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aliases { |
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serial0 = &uart0; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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leds { |
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compatible = "gpio-leds"; |
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hps0 { |
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label = "hps_led0"; |
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gpios = <&portb 20 GPIO_ACTIVE_HIGH>; |
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}; |
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hps1 { |
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label = "hps_led1"; |
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gpios = <&portb 19 GPIO_ACTIVE_HIGH>; |
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}; |
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hps2 { |
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label = "hps_led2"; |
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gpios = <&portb 21 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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memory { |
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device_type = "memory"; |
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/* We expect the bootloader to fill in the reg */ |
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reg = <0 0 0 0>; |
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}; |
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}; |
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&gpio1 { |
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status = "okay"; |
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}; |
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|
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&gmac0 { |
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status = "okay"; |
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phy-mode = "rgmii"; |
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phy-handle = <&phy0>; |
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|
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max-frame-size = <3800>; |
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mdio0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dwmac-mdio"; |
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phy0: ethernet-phy@0 { |
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reg = <4>; |
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|
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txd0-skew-ps = <0>; /* -420ps */ |
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txd1-skew-ps = <0>; /* -420ps */ |
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txd2-skew-ps = <0>; /* -420ps */ |
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txd3-skew-ps = <0>; /* -420ps */ |
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rxd0-skew-ps = <420>; /* 0ps */ |
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rxd1-skew-ps = <420>; /* 0ps */ |
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rxd2-skew-ps = <420>; /* 0ps */ |
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rxd3-skew-ps = <420>; /* 0ps */ |
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txen-skew-ps = <0>; /* -420ps */ |
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txc-skew-ps = <1860>; /* 960ps */ |
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rxdv-skew-ps = <420>; /* 0ps */ |
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rxc-skew-ps = <1680>; /* 780ps */ |
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}; |
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}; |
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}; |
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&mmc { |
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status = "okay"; |
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cap-sd-highspeed; |
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broken-cd; |
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bus-width = <4>; |
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}; |
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|
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&uart0 { |
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status = "okay"; |
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}; |
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|
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&usb0 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,33 @@ |
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/*
|
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* Copyright (C) 2016-2017 Intel Corporation <www.intel.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_ |
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#define _SOCFPGA_S10_BASE_HARDWARE_H_ |
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|
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#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 |
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#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 |
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#define SOCFPGA_SDR_ADDRESS 0xf8011000 |
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#define SOCFPGA_SMMU_ADDRESS 0xfa000000 |
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#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 |
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#define SOCFPGA_UART0_ADDRESS 0xffc02000 |
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#define SOCFPGA_UART1_ADDRESS 0xffc02100 |
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#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000 |
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#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100 |
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#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000 |
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#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100 |
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#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000 |
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#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000 |
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#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000 |
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000 |
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#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000 |
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#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000 |
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#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 |
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#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 |
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#define SOCFPGA_OCRAM_ADDRESS 0xffe00000 |
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#define GICD_BASE 0xfffc1000 |
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#define GICC_BASE 0xfffc2000 |
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|
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#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */ |
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@ -0,0 +1,105 @@ |
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/*
|
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* Socfpga Reset Controller Driver |
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* |
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* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> |
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* |
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* based on |
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* Allwinner SoCs Reset Controller driver |
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* |
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* Copyright 2013 Maxime Ripard |
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* |
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* Maxime Ripard <maxime.ripard@free-electrons.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <dm/of_access.h> |
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#include <reset-uclass.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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|
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#define BANK_INCREMENT 4 |
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#define NR_BANKS 8 |
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|
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struct socfpga_reset_data { |
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void __iomem *membase; |
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}; |
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|
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static int socfpga_reset_assert(struct reset_ctl *reset_ctl) |
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{ |
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struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
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int id = reset_ctl->id; |
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int reg_width = sizeof(u32); |
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int bank = id / (reg_width * BITS_PER_BYTE); |
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int offset = id % (reg_width * BITS_PER_BYTE); |
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|
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setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); |
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return 0; |
||||
} |
||||
|
||||
static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) |
||||
{ |
||||
struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
||||
int id = reset_ctl->id; |
||||
int reg_width = sizeof(u32); |
||||
int bank = id / (reg_width * BITS_PER_BYTE); |
||||
int offset = id % (reg_width * BITS_PER_BYTE); |
||||
|
||||
clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset)); |
||||
return 0; |
||||
} |
||||
|
||||
static int socfpga_reset_request(struct reset_ctl *reset_ctl) |
||||
{ |
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, |
||||
reset_ctl, reset_ctl->dev, reset_ctl->id); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int socfpga_reset_free(struct reset_ctl *reset_ctl) |
||||
{ |
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, |
||||
reset_ctl->dev, reset_ctl->id); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct reset_ops socfpga_reset_ops = { |
||||
.request = socfpga_reset_request, |
||||
.free = socfpga_reset_free, |
||||
.rst_assert = socfpga_reset_assert, |
||||
.rst_deassert = socfpga_reset_deassert, |
||||
}; |
||||
|
||||
static int socfpga_reset_probe(struct udevice *dev) |
||||
{ |
||||
struct socfpga_reset_data *data = dev_get_priv(dev); |
||||
const void *blob = gd->fdt_blob; |
||||
int node = dev_of_offset(dev); |
||||
u32 modrst_offset; |
||||
|
||||
data->membase = devfdt_get_addr_ptr(dev); |
||||
|
||||
modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10); |
||||
data->membase += modrst_offset; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id socfpga_reset_match[] = { |
||||
{ .compatible = "altr,rst-mgr" }, |
||||
{ /* sentinel */ }, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(socfpga_reset) = { |
||||
.name = "socfpga-reset", |
||||
.id = UCLASS_RESET, |
||||
.of_match = socfpga_reset_match, |
||||
.probe = socfpga_reset_probe, |
||||
.priv_auto_alloc_size = sizeof(struct socfpga_reset_data), |
||||
.ops = &socfpga_reset_ops, |
||||
}; |
||||
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation. All rights reserved |
||||
* Copyright (C) 2016 Altera Corporation. All rights reserved |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
* derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H |
||||
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H |
||||
|
||||
/* MPUMODRST */ |
||||
#define CPU0_RESET 0 |
||||
#define CPU1_RESET 1 |
||||
#define CPU2_RESET 2 |
||||
#define CPU3_RESET 3 |
||||
|
||||
/* PER0MODRST */ |
||||
#define EMAC0_RESET 32 |
||||
#define EMAC1_RESET 33 |
||||
#define EMAC2_RESET 34 |
||||
#define USB0_RESET 35 |
||||
#define USB1_RESET 36 |
||||
#define NAND_RESET 37 |
||||
/* 38 is empty */ |
||||
#define SDMMC_RESET 39 |
||||
#define EMAC0_OCP_RESET 40 |
||||
#define EMAC1_OCP_RESET 41 |
||||
#define EMAC2_OCP_RESET 42 |
||||
#define USB0_OCP_RESET 43 |
||||
#define USB1_OCP_RESET 44 |
||||
#define NAND_OCP_RESET 45 |
||||
/* 46 is empty */ |
||||
#define SDMMC_OCP_RESET 47 |
||||
#define DMA_RESET 48 |
||||
#define SPIM0_RESET 49 |
||||
#define SPIM1_RESET 50 |
||||
#define SPIS0_RESET 51 |
||||
#define SPIS1_RESET 52 |
||||
#define DMA_OCP_RESET 53 |
||||
#define EMAC_PTP_RESET 54 |
||||
/* 55 is empty*/ |
||||
#define DMAIF0_RESET 56 |
||||
#define DMAIF1_RESET 57 |
||||
#define DMAIF2_RESET 58 |
||||
#define DMAIF3_RESET 59 |
||||
#define DMAIF4_RESET 60 |
||||
#define DMAIF5_RESET 61 |
||||
#define DMAIF6_RESET 62 |
||||
#define DMAIF7_RESET 63 |
||||
|
||||
/* PER1MODRST */ |
||||
#define WATCHDOG0_RESET 64 |
||||
#define WATCHDOG1_RESET 65 |
||||
#define WATCHDOG2_RESET 66 |
||||
#define WATCHDOG3_RESET 67 |
||||
#define L4SYSTIMER0_RESET 68 |
||||
#define L4SYSTIMER1_RESET 69 |
||||
#define SPTIMER0_RESET 70 |
||||
#define SPTIMER1_RESET 71 |
||||
#define I2C0_RESET 72 |
||||
#define I2C1_RESET 73 |
||||
#define I2C2_RESET 74 |
||||
#define I2C3_RESET 75 |
||||
#define I2C4_RESET 76 |
||||
/* 77-79 is empty */ |
||||
#define UART0_RESET 80 |
||||
#define UART1_RESET 81 |
||||
/* 82-87 is empty */ |
||||
#define GPIO0_RESET 88 |
||||
#define GPIO1_RESET 89 |
||||
|
||||
/* BRGMODRST */ |
||||
#define SOC2FPGA_RESET 96 |
||||
#define LWHPS2FPGA_RESET 97 |
||||
#define FPGA2SOC_RESET 98 |
||||
#define F2SSDRAM0_RESET 99 |
||||
#define F2SSDRAM1_RESET 100 |
||||
#define F2SSDRAM2_RESET 101 |
||||
#define DDRSCH_RESET 102 |
||||
|
||||
/* COLDMODRST */ |
||||
#define CPUPO0_RESET 160 |
||||
#define CPUPO1_RESET 161 |
||||
#define CPUPO2_RESET 162 |
||||
#define CPUPO3_RESET 163 |
||||
/* 164-167 is empty */ |
||||
#define L2_RESET 168 |
||||
|
||||
/* DBGMODRST */ |
||||
#define DBG_RESET 224 |
||||
#define CSDAP_RESET 225 |
||||
|
||||
/* TAPMODRST */ |
||||
#define TAP_RESET 256 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue