Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>master
York Sun
10 years ago
parent
f43b4356a7
commit
40f8dec54d
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include "mp.h" |
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#ifdef CONFIG_MP |
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void ft_fixup_cpu(void *blob) |
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{ |
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int off; |
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__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr(); |
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fdt32_t *reg; |
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int addr_cells; |
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u64 val; |
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size_t *boot_code_size = &(__secondary_boot_code_size); |
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off = fdt_path_offset(blob, "/cpus"); |
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if (off < 0) { |
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puts("couldn't find /cpus node\n"); |
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return; |
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} |
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of_bus_default_count_cells(blob, off, &addr_cells, NULL); |
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); |
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while (off != -FDT_ERR_NOTFOUND) { |
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reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0); |
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if (reg) { |
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val = spin_tbl_addr; |
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val += id_to_core(of_read_number(reg, addr_cells)) |
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* SPIN_TABLE_ELEM_SIZE; |
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val = cpu_to_fdt64(val); |
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fdt_setprop_string(blob, off, "enable-method", |
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"spin-table"); |
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fdt_setprop(blob, off, "cpu-release-addr", |
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&val, sizeof(val)); |
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} else { |
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puts("Warning: found cpu node without reg property\n"); |
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} |
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off = fdt_node_offset_by_prop_value(blob, off, "device_type", |
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"cpu", 4); |
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} |
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fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code, |
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*boot_code_size); |
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} |
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#endif |
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void ft_cpu_setup(void *blob, bd_t *bd) |
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{ |
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#ifdef CONFIG_MP |
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ft_fixup_cpu(blob); |
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#endif |
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} |
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@ -0,0 +1,168 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/system.h> |
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#include <asm/io.h> |
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#include <asm/arch-fsl-lsch3/immap_lsch3.h> |
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#include "mp.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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void *get_spin_tbl_addr(void) |
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{ |
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return &__spin_table; |
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} |
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phys_addr_t determine_mp_bootpg(void) |
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{ |
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return (phys_addr_t)&secondary_boot_code; |
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} |
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int fsl_lsch3_wake_seconday_cores(void) |
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{ |
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
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struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); |
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u32 cores, cpu_up_mask = 1; |
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int i, timeout = 10; |
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u64 *table = get_spin_tbl_addr(); |
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cores = cpu_mask(); |
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/* Clear spin table so that secondary processors
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* observe the correct value after waking up from wfe. |
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*/ |
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memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); |
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flush_dcache_range((unsigned long)table, |
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(unsigned long)table + |
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(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); |
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printf("Waking secondary cores to start from %lx\n", gd->relocaddr); |
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out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); |
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out_le32(&gur->bootlocptrl, (u32)gd->relocaddr); |
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out_le32(&gur->scratchrw[6], 1); |
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asm volatile("dsb st" : : : "memory"); |
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rst->brrl = cores; |
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asm volatile("dsb st" : : : "memory"); |
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/* This is needed as a precautionary measure.
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* If some code before this has accidentally released the secondary |
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* cores then the pre-bootloader code will trap them in a "wfe" unless |
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* the scratchrw[6] is set. In this case we need a sev here to get these |
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* cores moving again. |
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*/ |
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asm volatile("sev"); |
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while (timeout--) { |
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flush_dcache_range((unsigned long)table, (unsigned long)table + |
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CONFIG_MAX_CPUS * 64); |
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for (i = 1; i < CONFIG_MAX_CPUS; i++) { |
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if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + |
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SPIN_TABLE_ELEM_STATUS_IDX]) |
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cpu_up_mask |= 1 << i; |
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} |
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if (hweight32(cpu_up_mask) == hweight32(cores)) |
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break; |
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udelay(10); |
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} |
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if (timeout <= 0) { |
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printf("Not all cores (0x%x) are up (0x%x)\n", |
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cores, cpu_up_mask); |
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return 1; |
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} |
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printf("All (%d) cores are up.\n", hweight32(cores)); |
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return 0; |
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} |
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int is_core_valid(unsigned int core) |
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{ |
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return !!((1 << core) & cpu_mask()); |
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} |
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int cpu_reset(int nr) |
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{ |
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puts("Feature is not implemented.\n"); |
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return 0; |
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} |
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int cpu_disable(int nr) |
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{ |
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puts("Feature is not implemented.\n"); |
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return 0; |
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} |
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int core_to_pos(int nr) |
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{ |
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u32 cores = cpu_mask(); |
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int i, count = 0; |
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if (nr == 0) { |
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return 0; |
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} else if (nr >= hweight32(cores)) { |
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puts("Not a valid core number.\n"); |
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return -1; |
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} |
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for (i = 1; i < 32; i++) { |
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if (is_core_valid(i)) { |
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count++; |
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if (count == nr) |
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break; |
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} |
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} |
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return count; |
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} |
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int cpu_status(int nr) |
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{ |
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u64 *table; |
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int pos; |
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if (nr == 0) { |
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table = (u64 *)get_spin_tbl_addr(); |
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printf("table base @ 0x%p\n", table); |
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} else { |
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pos = core_to_pos(nr); |
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if (pos < 0) |
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return -1; |
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table = (u64 *)get_spin_tbl_addr() + pos * |
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WORDS_PER_SPIN_TABLE_ENTRY; |
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printf("table @ 0x%p\n", table); |
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printf(" addr - 0x%016llx\n", |
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]); |
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printf(" status - 0x%016llx\n", |
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table[SPIN_TABLE_ELEM_STATUS_IDX]); |
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printf(" lpid - 0x%016llx\n", |
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table[SPIN_TABLE_ELEM_LPID_IDX]); |
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} |
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return 0; |
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} |
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int cpu_release(int nr, int argc, char * const argv[]) |
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{ |
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u64 boot_addr; |
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u64 *table = (u64 *)get_spin_tbl_addr(); |
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int pos; |
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pos = core_to_pos(nr); |
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if (pos <= 0) |
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return -1; |
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table += pos * WORDS_PER_SPIN_TABLE_ENTRY; |
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boot_addr = simple_strtoull(argv[0], NULL, 16); |
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; |
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flush_dcache_range((unsigned long)table, |
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(unsigned long)table + SPIN_TABLE_ELEM_SIZE); |
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asm volatile("dsb st"); |
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smp_kick_all_cpus(); /* only those with entry addr set will run */ |
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return 0; |
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} |
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@ -0,0 +1,36 @@ |
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/*
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* Copyright 2014, Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _FSL_CH3_MP_H |
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#define _FSL_CH3_MP_H |
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/*
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* Each spin table element is defined as |
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* struct { |
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* uint64_t entry_addr; |
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* uint64_t status; |
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* uint64_t lpid; |
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* }; |
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* we pad this struct to 64 bytes so each entry is in its own cacheline |
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* the actual spin table is an array of these structures |
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*/ |
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#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 |
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#define SPIN_TABLE_ELEM_STATUS_IDX 1 |
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#define SPIN_TABLE_ELEM_LPID_IDX 2 |
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#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ |
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#define SPIN_TABLE_ELEM_SIZE 64 |
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#define id_to_core(x) ((x & 3) | (x >> 6)) |
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#ifndef __ASSEMBLY__ |
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extern u64 __spin_table[]; |
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extern u64 *secondary_boot_code; |
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extern size_t __secondary_boot_code_size; |
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int fsl_lsch3_wake_seconday_cores(void); |
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void *get_spin_tbl_addr(void); |
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phys_addr_t determine_mp_bootpg(void); |
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void secondary_boot_func(void); |
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#endif |
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#endif /* _FSL_CH3_MP_H */ |
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