Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6, commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3 and H3 ULCB and Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Marek Vasut
7 years ago
committed by
Nobuhiro Iwamatsu
parent
48aa812676
commit
4157c472c3
@ -0,0 +1,376 @@ |
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/* |
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* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board |
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* |
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* Copyright (C) 2016 Renesas Electronics Corp. |
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* Copyright (C) 2016 Cogent Embedded, Inc. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/dts-v1/; |
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#include "r8a7795.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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|
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/ { |
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model = "Renesas H3ULCB board based on r8a7795"; |
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compatible = "renesas,h3ulcb", "renesas,r8a7795"; |
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|
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aliases { |
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serial0 = &scif2; |
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ethernet0 = &avb; |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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|
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memory@500000000 { |
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device_type = "memory"; |
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reg = <0x5 0x00000000 0x0 0x40000000>; |
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}; |
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|
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memory@600000000 { |
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device_type = "memory"; |
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reg = <0x6 0x00000000 0x0 0x40000000>; |
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}; |
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|
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memory@700000000 { |
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device_type = "memory"; |
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reg = <0x7 0x00000000 0x0 0x40000000>; |
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}; |
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|
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leds { |
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compatible = "gpio-leds"; |
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|
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led5 { |
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gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; |
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}; |
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led6 { |
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gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
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}; |
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}; |
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|
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keyboard { |
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compatible = "gpio-keys"; |
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|
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key-1 { |
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linux,code = <KEY_1>; |
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label = "SW3"; |
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wakeup-source; |
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debounce-interval = <20>; |
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gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
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}; |
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}; |
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|
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x12_clk: x12 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24576000>; |
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}; |
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|
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reg_1p8v: regulator0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-1.8V"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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reg_3p3v: regulator1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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|
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vcc_sdhi0: regulator-vcc-sdhi0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "SDHI0 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi0: regulator-vccq-sdhi0 { |
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compatible = "regulator-gpio"; |
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regulator-name = "SDHI0 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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audio_clkout: audio-clkout { |
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/* |
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* This is same as <&rcar_sound 0> |
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* but needed to avoid cs2000/rcar_sound probe dead-lock |
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*/ |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <11289600>; |
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}; |
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|
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rsnd_ak4613: sound { |
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compatible = "simple-audio-card"; |
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simple-audio-card,format = "left_j"; |
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simple-audio-card,bitclock-master = <&sndcpu>; |
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simple-audio-card,frame-master = <&sndcpu>; |
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sndcpu: simple-audio-card,cpu { |
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sound-dai = <&rcar_sound>; |
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}; |
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sndcodec: simple-audio-card,codec { |
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sound-dai = <&ak4613>; |
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}; |
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}; |
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}; |
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&extal_clk { |
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clock-frequency = <16666666>; |
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}; |
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&extalr_clk { |
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clock-frequency = <32768>; |
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}; |
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&pfc { |
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pinctrl-0 = <&scif_clk_pins>; |
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pinctrl-names = "default"; |
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scif2_pins: scif2 { |
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groups = "scif2_data_a"; |
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function = "scif2"; |
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}; |
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scif_clk_pins: scif_clk { |
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groups = "scif_clk_a"; |
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function = "scif_clk"; |
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}; |
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i2c2_pins: i2c2 { |
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groups = "i2c2_a"; |
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function = "i2c2"; |
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}; |
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avb_pins: avb { |
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groups = "avb_mdc"; |
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function = "avb"; |
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}; |
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sdhi0_pins: sd0 { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <3300>; |
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}; |
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sdhi0_pins_uhs: sd0_uhs { |
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groups = "sdhi0_data4", "sdhi0_ctrl"; |
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function = "sdhi0"; |
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power-source = <1800>; |
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}; |
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sdhi2_pins: sd2 { |
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groups = "sdhi2_data8", "sdhi2_ctrl"; |
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function = "sdhi2"; |
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power-source = <3300>; |
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}; |
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sdhi2_pins_uhs: sd2_uhs { |
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groups = "sdhi2_data8", "sdhi2_ctrl"; |
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function = "sdhi2"; |
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power-source = <1800>; |
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}; |
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sound_pins: sound { |
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groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; |
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function = "ssi"; |
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}; |
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sound_clk_pins: sound-clk { |
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groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", |
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"audio_clkout_a", "audio_clkout3_a"; |
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function = "audio_clk"; |
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}; |
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usb1_pins: usb1 { |
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groups = "usb1"; |
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function = "usb1"; |
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}; |
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}; |
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&scif2 { |
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pinctrl-0 = <&scif2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&scif_clk { |
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clock-frequency = <14745600>; |
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}; |
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&i2c2 { |
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pinctrl-0 = <&i2c2_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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clock-frequency = <100000>; |
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ak4613: codec@10 { |
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compatible = "asahi-kasei,ak4613"; |
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#sound-dai-cells = <0>; |
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reg = <0x10>; |
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clocks = <&rcar_sound 3>; |
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asahi-kasei,in1-single-end; |
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asahi-kasei,in2-single-end; |
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asahi-kasei,out1-single-end; |
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asahi-kasei,out2-single-end; |
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asahi-kasei,out3-single-end; |
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asahi-kasei,out4-single-end; |
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asahi-kasei,out5-single-end; |
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asahi-kasei,out6-single-end; |
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}; |
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cs2000: clk-multiplier@4f { |
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#clock-cells = <0>; |
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compatible = "cirrus,cs2000-cp"; |
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reg = <0x4f>; |
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clocks = <&audio_clkout>, <&x12_clk>; |
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clock-names = "clk_in", "ref_clk"; |
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assigned-clocks = <&cs2000>; |
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assigned-clock-rates = <24576000>; /* 1/1 divide */ |
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}; |
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}; |
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&rcar_sound { |
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pinctrl-0 = <&sound_pins &sound_clk_pins>; |
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pinctrl-names = "default"; |
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/* Single DAI */ |
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#sound-dai-cells = <0>; |
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/* audio_clkout0/1/2/3 */ |
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#clock-cells = <1>; |
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clock-frequency = <11289600>; |
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status = "okay"; |
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/* update <audio_clk_b> to <cs2000> */ |
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clocks = <&cpg CPG_MOD 1005>, |
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<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, |
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<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, |
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<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, |
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<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, |
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<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, |
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<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
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<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, |
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<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
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<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
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<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
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<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
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<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
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<&audio_clk_a>, <&cs2000>, |
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<&audio_clk_c>, |
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<&cpg CPG_CORE R8A7795_CLK_S0D4>; |
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rcar_sound,dai { |
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dai0 { |
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playback = <&ssi0 &src0 &dvc0>; |
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capture = <&ssi1 &src1 &dvc1>; |
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}; |
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}; |
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}; |
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&sdhi0 { |
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pinctrl-0 = <&sdhi0_pins>; |
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pinctrl-1 = <&sdhi0_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <&vcc_sdhi0>; |
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vqmmc-supply = <&vccq_sdhi0>; |
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cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
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bus-width = <4>; |
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sd-uhs-sdr50; |
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status = "okay"; |
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}; |
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&sdhi2 { |
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/* used for on-board 8bit eMMC */ |
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pinctrl-0 = <&sdhi2_pins>; |
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pinctrl-1 = <&sdhi2_pins_uhs>; |
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pinctrl-names = "default", "state_uhs"; |
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vmmc-supply = <®_3p3v>; |
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vqmmc-supply = <®_1p8v>; |
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bus-width = <8>; |
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non-removable; |
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status = "okay"; |
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}; |
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&ssi1 { |
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shared-pin; |
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}; |
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&wdt0 { |
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timeout-sec = <60>; |
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status = "okay"; |
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}; |
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&audio_clk_a { |
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clock-frequency = <22579200>; |
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}; |
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&avb { |
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pinctrl-0 = <&avb_pins>; |
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pinctrl-names = "default"; |
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renesas,no-ether-link; |
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phy-handle = <&phy0>; |
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status = "okay"; |
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phy0: ethernet-phy@0 { |
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rxc-skew-ps = <1500>; |
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reg = <0>; |
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interrupt-parent = <&gpio2>; |
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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}; |
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&usb2_phy1 { |
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pinctrl-0 = <&usb1_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&ehci1 { |
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status = "okay"; |
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}; |
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&ohci1 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,584 @@ |
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/* |
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* Device Tree Source for the Salvator-X board |
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* |
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* Copyright (C) 2015 Renesas Electronics Corp. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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|
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/* |
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* SSI-AK4613 |
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* |
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* This command is required when Playback/Capture |
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* |
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* amixer set "DVC Out" 100% |
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* amixer set "DVC In" 100% |
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* |
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* You can use Mute |
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* |
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* amixer set "DVC Out Mute" on |
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* amixer set "DVC In Mute" on |
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* |
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* You can use Volume Ramp |
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* |
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* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" |
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* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" |
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* amixer set "DVC Out Ramp" on |
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* aplay xxx.wav & |
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* amixer set "DVC Out" 80% // Volume Down |
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* amixer set "DVC Out" 100% // Volume Up |
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*/ |
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/dts-v1/; |
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#include "r8a7795.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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/ { |
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model = "Renesas Salvator-X board based on r8a7795"; |
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compatible = "renesas,salvator-x", "renesas,r8a7795"; |
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aliases { |
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serial0 = &scif2; |
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serial1 = &scif1; |
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ethernet0 = &avb; |
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}; |
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chosen { |
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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x12_clk: x12 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24576000>; |
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}; |
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reg_1p8v: regulator0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-1.8V"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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reg_3p3v: regulator1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "fixed-3.3V"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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vcc_sdhi0: regulator-vcc-sdhi0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "SDHI0 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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vccq_sdhi0: regulator-vccq-sdhi0 { |
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compatible = "regulator-gpio"; |
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|
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regulator-name = "SDHI0 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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|
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vcc_sdhi3: regulator-vcc-sdhi3 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "SDHI3 Vcc"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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vccq_sdhi3: regulator-vccq-sdhi3 { |
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compatible = "regulator-gpio"; |
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|
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regulator-name = "SDHI3 VccQ"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <3300000>; |
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|
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gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; |
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gpios-states = <1>; |
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states = <3300000 1 |
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1800000 0>; |
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}; |
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|
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vbus0_usb2: regulator-vbus0-usb2 { |
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compatible = "regulator-fixed"; |
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|
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regulator-name = "USB20_VBUS0"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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|
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gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; |
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enable-active-high; |
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}; |
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|
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audio_clkout: audio_clkout { |
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/* |
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* This is same as <&rcar_sound 0> |
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* but needed to avoid cs2000/rcar_sound probe dead-lock |
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*/ |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <11289600>; |
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}; |
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|
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rsnd_ak4613: sound { |
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compatible = "simple-audio-card"; |
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|
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simple-audio-card,format = "left_j"; |
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simple-audio-card,bitclock-master = <&sndcpu>; |
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simple-audio-card,frame-master = <&sndcpu>; |
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|
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sndcpu: simple-audio-card,cpu { |
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sound-dai = <&rcar_sound>; |
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}; |
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|
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sndcodec: simple-audio-card,codec { |
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sound-dai = <&ak4613>; |
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}; |
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}; |
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|
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vga-encoder { |
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compatible = "adi,adv7123"; |
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|
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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port@0 { |
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reg = <0>; |
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adv7123_in: endpoint { |
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remote-endpoint = <&du_out_rgb>; |
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}; |
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}; |
||||
port@1 { |
||||
reg = <1>; |
||||
adv7123_out: endpoint { |
||||
remote-endpoint = <&vga_in>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
vga { |
||||
compatible = "vga-connector"; |
||||
|
||||
port { |
||||
vga_in: endpoint { |
||||
remote-endpoint = <&adv7123_out>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&du { |
||||
pinctrl-0 = <&du_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
|
||||
ports { |
||||
port@0 { |
||||
endpoint { |
||||
remote-endpoint = <&adv7123_in>; |
||||
}; |
||||
}; |
||||
port@3 { |
||||
lvds_connector: endpoint { |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
scif1_pins: scif1 { |
||||
groups = "scif1_data_a", "scif1_ctrl"; |
||||
function = "scif1"; |
||||
}; |
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
i2c2_pins: i2c2 { |
||||
groups = "i2c2_a"; |
||||
function = "i2c2"; |
||||
}; |
||||
|
||||
avb_pins: avb { |
||||
mux { |
||||
groups = "avb_link", "avb_phy_int", "avb_mdc", |
||||
"avb_mii"; |
||||
function = "avb"; |
||||
}; |
||||
|
||||
pins_mdc { |
||||
groups = "avb_mdc"; |
||||
drive-strength = <24>; |
||||
}; |
||||
|
||||
pins_mii_tx { |
||||
pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", |
||||
"PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; |
||||
drive-strength = <12>; |
||||
}; |
||||
}; |
||||
|
||||
du_pins: du { |
||||
groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; |
||||
function = "du"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi3_pins: sd3 { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi3_pins_uhs: sd3_uhs { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sound_pins: sound { |
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; |
||||
function = "ssi"; |
||||
}; |
||||
|
||||
sound_clk_pins: sound_clk { |
||||
groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", |
||||
"audio_clkout_a", "audio_clkout3_a"; |
||||
function = "audio_clk"; |
||||
}; |
||||
|
||||
usb0_pins: usb0 { |
||||
groups = "usb0"; |
||||
function = "usb0"; |
||||
}; |
||||
|
||||
usb1_pins: usb1 { |
||||
mux { |
||||
groups = "usb1"; |
||||
function = "usb1"; |
||||
}; |
||||
|
||||
ovc { |
||||
pins = "GP_6_27"; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
pwen { |
||||
pins = "GP_6_26"; |
||||
bias-pull-down; |
||||
}; |
||||
}; |
||||
|
||||
usb2_pins: usb2 { |
||||
groups = "usb2"; |
||||
function = "usb2"; |
||||
}; |
||||
}; |
||||
|
||||
&scif1 { |
||||
pinctrl-0 = <&scif1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
uart-has-rtscts; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
pinctrl-0 = <&i2c2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
|
||||
clock-frequency = <100000>; |
||||
|
||||
ak4613: codec@10 { |
||||
compatible = "asahi-kasei,ak4613"; |
||||
#sound-dai-cells = <0>; |
||||
reg = <0x10>; |
||||
clocks = <&rcar_sound 3>; |
||||
|
||||
asahi-kasei,in1-single-end; |
||||
asahi-kasei,in2-single-end; |
||||
asahi-kasei,out1-single-end; |
||||
asahi-kasei,out2-single-end; |
||||
asahi-kasei,out3-single-end; |
||||
asahi-kasei,out4-single-end; |
||||
asahi-kasei,out5-single-end; |
||||
asahi-kasei,out6-single-end; |
||||
}; |
||||
|
||||
cs2000: clk_multiplier@4f { |
||||
#clock-cells = <0>; |
||||
compatible = "cirrus,cs2000-cp"; |
||||
reg = <0x4f>; |
||||
clocks = <&audio_clkout>, <&x12_clk>; |
||||
clock-names = "clk_in", "ref_clk"; |
||||
|
||||
assigned-clocks = <&cs2000>; |
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */ |
||||
}; |
||||
}; |
||||
|
||||
&rcar_sound { |
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
/* Single DAI */ |
||||
#sound-dai-cells = <0>; |
||||
|
||||
/* audio_clkout0/1/2/3 */ |
||||
#clock-cells = <1>; |
||||
clock-frequency = <11289600>; |
||||
|
||||
status = "okay"; |
||||
|
||||
/* update <audio_clk_b> to <cs2000> */ |
||||
clocks = <&cpg CPG_MOD 1005>, |
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, |
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, |
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, |
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, |
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, |
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, |
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
||||
<&audio_clk_a>, <&cs2000>, |
||||
<&audio_clk_c>, |
||||
<&cpg CPG_CORE R8A7795_CLK_S0D4>; |
||||
|
||||
rcar_sound,dai { |
||||
dai0 { |
||||
playback = <&ssi0 &src0 &dvc0>; |
||||
capture = <&ssi1 &src1 &dvc1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&sata { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi3 { |
||||
pinctrl-0 = <&sdhi3_pins>; |
||||
pinctrl-1 = <&sdhi3_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi3>; |
||||
vqmmc-supply = <&vccq_sdhi3>; |
||||
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ssi1 { |
||||
shared-pin; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&audio_clk_a { |
||||
clock-frequency = <22579200>; |
||||
}; |
||||
|
||||
&i2c_dvfs { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&avb { |
||||
pinctrl-0 = <&avb_pins>; |
||||
pinctrl-names = "default"; |
||||
renesas,no-ether-link; |
||||
phy-handle = <&phy0>; |
||||
status = "okay"; |
||||
|
||||
phy0: ethernet-phy@0 { |
||||
rxc-skew-ps = <1500>; |
||||
reg = <0>; |
||||
interrupt-parent = <&gpio2>; |
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
&xhci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy0 { |
||||
pinctrl-0 = <&usb0_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
vbus-supply = <&vbus0_usb2>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy1 { |
||||
pinctrl-0 = <&usb1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb2_phy2 { |
||||
pinctrl-0 = <&usb2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ehci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci1 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&ohci2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&hsusb { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pcie_bus_clk { |
||||
clock-frequency = <100000000>; |
||||
}; |
||||
|
||||
&pciec0 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&pciec1 { |
||||
status = "okay"; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,188 @@ |
||||
/* |
||||
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board |
||||
* |
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* Copyright (C) 2016 Cogent Embedded, Inc. |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public License |
||||
* version 2. This program is licensed "as is" without any warranty of any |
||||
* kind, whether express or implied. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "r8a7796.dtsi" |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/input/input.h> |
||||
|
||||
/ { |
||||
model = "Renesas M3ULCB board based on r8a7796"; |
||||
compatible = "renesas,m3ulcb", "renesas,r8a7796"; |
||||
|
||||
aliases { |
||||
serial0 = &scif2; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory@48000000 { |
||||
device_type = "memory"; |
||||
/* first 128MB is reserved for secure area. */ |
||||
reg = <0x0 0x48000000 0x0 0x38000000>; |
||||
}; |
||||
|
||||
leds { |
||||
compatible = "gpio-leds"; |
||||
|
||||
led5 { |
||||
gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
led6 { |
||||
gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; |
||||
}; |
||||
}; |
||||
|
||||
keyboard { |
||||
compatible = "gpio-keys"; |
||||
|
||||
key-1 { |
||||
linux,code = <KEY_1>; |
||||
label = "SW3"; |
||||
wakeup-source; |
||||
debounce-interval = <20>; |
||||
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
reg_1p8v: regulator0 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
reg_3p3v: regulator1 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-3.3V"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI0 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI0 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
|
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,269 @@ |
||||
/* |
||||
* Device Tree Source for the Salvator-X board |
||||
* |
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public License |
||||
* version 2. This program is licensed "as is" without any warranty of any |
||||
* kind, whether express or implied. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "r8a7796.dtsi" |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
|
||||
/ { |
||||
model = "Renesas Salvator-X board based on r8a7796"; |
||||
compatible = "renesas,salvator-x", "renesas,r8a7796"; |
||||
|
||||
aliases { |
||||
serial0 = &scif2; |
||||
serial1 = &scif1; |
||||
ethernet0 = &avb; |
||||
}; |
||||
|
||||
chosen { |
||||
bootargs = "ignore_loglevel"; |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
|
||||
memory@48000000 { |
||||
device_type = "memory"; |
||||
/* first 128MB is reserved for secure area. */ |
||||
reg = <0x0 0x48000000 0x0 0x78000000>; |
||||
}; |
||||
|
||||
memory@600000000 { |
||||
device_type = "memory"; |
||||
reg = <0x6 0x00000000 0x0 0x80000000>; |
||||
}; |
||||
|
||||
reg_1p8v: regulator0 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
reg_3p3v: regulator1 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "fixed-3.3V"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI0 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI0 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
|
||||
vcc_sdhi3: regulator-vcc-sdhi3 { |
||||
compatible = "regulator-fixed"; |
||||
|
||||
regulator-name = "SDHI3 Vcc"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
vccq_sdhi3: regulator-vccq-sdhi3 { |
||||
compatible = "regulator-gpio"; |
||||
|
||||
regulator-name = "SDHI3 VccQ"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
|
||||
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; |
||||
gpios-states = <1>; |
||||
states = <3300000 1 |
||||
1800000 0>; |
||||
}; |
||||
}; |
||||
|
||||
&pfc { |
||||
pinctrl-0 = <&scif_clk_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
avb_pins: avb { |
||||
groups = "avb_mdc"; |
||||
function = "avb"; |
||||
}; |
||||
|
||||
scif1_pins: scif1 { |
||||
groups = "scif1_data_a", "scif1_ctrl"; |
||||
function = "scif1"; |
||||
}; |
||||
|
||||
scif2_pins: scif2 { |
||||
groups = "scif2_data_a"; |
||||
function = "scif2"; |
||||
}; |
||||
scif_clk_pins: scif_clk { |
||||
groups = "scif_clk_a"; |
||||
function = "scif_clk"; |
||||
}; |
||||
|
||||
i2c2_pins: i2c2 { |
||||
groups = "i2c2_a"; |
||||
function = "i2c2"; |
||||
}; |
||||
|
||||
sdhi0_pins: sd0 { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi0_pins_uhs: sd0_uhs { |
||||
groups = "sdhi0_data4", "sdhi0_ctrl"; |
||||
function = "sdhi0"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi2_pins: sd2 { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi2_pins_uhs: sd2_uhs { |
||||
groups = "sdhi2_data8", "sdhi2_ctrl"; |
||||
function = "sdhi2"; |
||||
power-source = <1800>; |
||||
}; |
||||
|
||||
sdhi3_pins: sd3 { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <3300>; |
||||
}; |
||||
|
||||
sdhi3_pins_uhs: sd3_uhs { |
||||
groups = "sdhi3_data4", "sdhi3_ctrl"; |
||||
function = "sdhi3"; |
||||
power-source = <1800>; |
||||
}; |
||||
}; |
||||
|
||||
&avb { |
||||
pinctrl-0 = <&avb_pins>; |
||||
pinctrl-names = "default"; |
||||
renesas,no-ether-link; |
||||
phy-handle = <&phy0>; |
||||
status = "okay"; |
||||
|
||||
phy0: ethernet-phy@0 { |
||||
rxc-skew-ps = <1500>; |
||||
reg = <0>; |
||||
interrupt-parent = <&gpio2>; |
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
&extal_clk { |
||||
clock-frequency = <16666666>; |
||||
}; |
||||
|
||||
&extalr_clk { |
||||
clock-frequency = <32768>; |
||||
}; |
||||
|
||||
&sdhi0 { |
||||
pinctrl-0 = <&sdhi0_pins>; |
||||
pinctrl-1 = <&sdhi0_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi0>; |
||||
vqmmc-supply = <&vccq_sdhi0>; |
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi2 { |
||||
/* used for on-board 8bit eMMC */ |
||||
pinctrl-0 = <&sdhi2_pins>; |
||||
pinctrl-1 = <&sdhi2_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <®_3p3v>; |
||||
vqmmc-supply = <®_1p8v>; |
||||
bus-width = <8>; |
||||
non-removable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sdhi3 { |
||||
pinctrl-0 = <&sdhi3_pins>; |
||||
pinctrl-1 = <&sdhi3_pins_uhs>; |
||||
pinctrl-names = "default", "state_uhs"; |
||||
|
||||
vmmc-supply = <&vcc_sdhi3>; |
||||
vqmmc-supply = <&vccq_sdhi3>; |
||||
cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; |
||||
bus-width = <4>; |
||||
sd-uhs-sdr50; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif1 { |
||||
pinctrl-0 = <&scif1_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
uart-has-rtscts; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif2 { |
||||
pinctrl-0 = <&scif2_pins>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&scif_clk { |
||||
clock-frequency = <14745600>; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
pinctrl-0 = <&i2c2_pins>; |
||||
pinctrl-names = "default"; |
||||
|
||||
status = "okay"; |
||||
}; |
||||
|
||||
&wdt0 { |
||||
timeout-sec = <60>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c_dvfs { |
||||
status = "okay"; |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,70 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a7795 CPG Core Clocks */ |
||||
#define R8A7795_CLK_Z 0 |
||||
#define R8A7795_CLK_Z2 1 |
||||
#define R8A7795_CLK_ZR 2 |
||||
#define R8A7795_CLK_ZG 3 |
||||
#define R8A7795_CLK_ZTR 4 |
||||
#define R8A7795_CLK_ZTRD2 5 |
||||
#define R8A7795_CLK_ZT 6 |
||||
#define R8A7795_CLK_ZX 7 |
||||
#define R8A7795_CLK_S0D1 8 |
||||
#define R8A7795_CLK_S0D4 9 |
||||
#define R8A7795_CLK_S1D1 10 |
||||
#define R8A7795_CLK_S1D2 11 |
||||
#define R8A7795_CLK_S1D4 12 |
||||
#define R8A7795_CLK_S2D1 13 |
||||
#define R8A7795_CLK_S2D2 14 |
||||
#define R8A7795_CLK_S2D4 15 |
||||
#define R8A7795_CLK_S3D1 16 |
||||
#define R8A7795_CLK_S3D2 17 |
||||
#define R8A7795_CLK_S3D4 18 |
||||
#define R8A7795_CLK_LB 19 |
||||
#define R8A7795_CLK_CL 20 |
||||
#define R8A7795_CLK_ZB3 21 |
||||
#define R8A7795_CLK_ZB3D2 22 |
||||
#define R8A7795_CLK_CR 23 |
||||
#define R8A7795_CLK_CRD2 24 |
||||
#define R8A7795_CLK_SD0H 25 |
||||
#define R8A7795_CLK_SD0 26 |
||||
#define R8A7795_CLK_SD1H 27 |
||||
#define R8A7795_CLK_SD1 28 |
||||
#define R8A7795_CLK_SD2H 29 |
||||
#define R8A7795_CLK_SD2 30 |
||||
#define R8A7795_CLK_SD3H 31 |
||||
#define R8A7795_CLK_SD3 32 |
||||
#define R8A7795_CLK_SSP2 33 |
||||
#define R8A7795_CLK_SSP1 34 |
||||
#define R8A7795_CLK_SSPRS 35 |
||||
#define R8A7795_CLK_RPC 36 |
||||
#define R8A7795_CLK_RPCD2 37 |
||||
#define R8A7795_CLK_MSO 38 |
||||
#define R8A7795_CLK_CANFD 39 |
||||
#define R8A7795_CLK_HDMI 40 |
||||
#define R8A7795_CLK_CSI0 41 |
||||
#define R8A7795_CLK_CSIREF 42 |
||||
#define R8A7795_CLK_CP 43 |
||||
#define R8A7795_CLK_CPEX 44 |
||||
#define R8A7795_CLK_R 45 |
||||
#define R8A7795_CLK_OSC 46 |
||||
|
||||
/* r8a7795 ES2.0 CPG Core Clocks */ |
||||
#define R8A7795_CLK_S0D2 47 |
||||
#define R8A7795_CLK_S0D3 48 |
||||
#define R8A7795_CLK_S0D6 49 |
||||
#define R8A7795_CLK_S0D8 50 |
||||
#define R8A7795_CLK_S0D12 51 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,69 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a7796 CPG Core Clocks */ |
||||
#define R8A7796_CLK_Z 0 |
||||
#define R8A7796_CLK_Z2 1 |
||||
#define R8A7796_CLK_ZR 2 |
||||
#define R8A7796_CLK_ZG 3 |
||||
#define R8A7796_CLK_ZTR 4 |
||||
#define R8A7796_CLK_ZTRD2 5 |
||||
#define R8A7796_CLK_ZT 6 |
||||
#define R8A7796_CLK_ZX 7 |
||||
#define R8A7796_CLK_S0D1 8 |
||||
#define R8A7796_CLK_S0D2 9 |
||||
#define R8A7796_CLK_S0D3 10 |
||||
#define R8A7796_CLK_S0D4 11 |
||||
#define R8A7796_CLK_S0D6 12 |
||||
#define R8A7796_CLK_S0D8 13 |
||||
#define R8A7796_CLK_S0D12 14 |
||||
#define R8A7796_CLK_S1D1 15 |
||||
#define R8A7796_CLK_S1D2 16 |
||||
#define R8A7796_CLK_S1D4 17 |
||||
#define R8A7796_CLK_S2D1 18 |
||||
#define R8A7796_CLK_S2D2 19 |
||||
#define R8A7796_CLK_S2D4 20 |
||||
#define R8A7796_CLK_S3D1 21 |
||||
#define R8A7796_CLK_S3D2 22 |
||||
#define R8A7796_CLK_S3D4 23 |
||||
#define R8A7796_CLK_LB 24 |
||||
#define R8A7796_CLK_CL 25 |
||||
#define R8A7796_CLK_ZB3 26 |
||||
#define R8A7796_CLK_ZB3D2 27 |
||||
#define R8A7796_CLK_ZB3D4 28 |
||||
#define R8A7796_CLK_CR 29 |
||||
#define R8A7796_CLK_CRD2 30 |
||||
#define R8A7796_CLK_SD0H 31 |
||||
#define R8A7796_CLK_SD0 32 |
||||
#define R8A7796_CLK_SD1H 33 |
||||
#define R8A7796_CLK_SD1 34 |
||||
#define R8A7796_CLK_SD2H 35 |
||||
#define R8A7796_CLK_SD2 36 |
||||
#define R8A7796_CLK_SD3H 37 |
||||
#define R8A7796_CLK_SD3 38 |
||||
#define R8A7796_CLK_SSP2 39 |
||||
#define R8A7796_CLK_SSP1 40 |
||||
#define R8A7796_CLK_SSPRS 41 |
||||
#define R8A7796_CLK_RPC 42 |
||||
#define R8A7796_CLK_RPCD2 43 |
||||
#define R8A7796_CLK_MSO 44 |
||||
#define R8A7796_CLK_CANFD 45 |
||||
#define R8A7796_CLK_HDMI 46 |
||||
#define R8A7796_CLK_CSI0 47 |
||||
#define R8A7796_CLK_CSIREF 48 |
||||
#define R8A7796_CLK_CP 49 |
||||
#define R8A7796_CLK_CPEX 50 |
||||
#define R8A7796_CLK_R 51 |
||||
#define R8A7796_CLK_OSC 52 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,15 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ |
||||
|
||||
#define CPG_CORE 0 /* Core Clock */ |
||||
#define CPG_MOD 1 /* Module Clock */ |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; version 2 of the License. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ |
||||
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ |
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits |
||||
* representing the power areas in the various Interrupt Registers |
||||
* (e.g. SYSCISR, Interrupt Status Register) |
||||
*/ |
||||
|
||||
#define R8A7795_PD_CA57_CPU0 0 |
||||
#define R8A7795_PD_CA57_CPU1 1 |
||||
#define R8A7795_PD_CA57_CPU2 2 |
||||
#define R8A7795_PD_CA57_CPU3 3 |
||||
#define R8A7795_PD_CA53_CPU0 5 |
||||
#define R8A7795_PD_CA53_CPU1 6 |
||||
#define R8A7795_PD_CA53_CPU2 7 |
||||
#define R8A7795_PD_CA53_CPU3 8 |
||||
#define R8A7795_PD_A3VP 9 |
||||
#define R8A7795_PD_CA57_SCU 12 |
||||
#define R8A7795_PD_CR7 13 |
||||
#define R8A7795_PD_A3VC 14 |
||||
#define R8A7795_PD_3DG_A 17 |
||||
#define R8A7795_PD_3DG_B 18 |
||||
#define R8A7795_PD_3DG_C 19 |
||||
#define R8A7795_PD_3DG_D 20 |
||||
#define R8A7795_PD_CA53_SCU 21 |
||||
#define R8A7795_PD_3DG_E 22 |
||||
#define R8A7795_PD_A3IR 24 |
||||
#define R8A7795_PD_A2VC0 25 /* ES1.x only */ |
||||
#define R8A7795_PD_A2VC1 26 |
||||
|
||||
/* Always-on power area */ |
||||
#define R8A7795_PD_ALWAYS_ON 32 |
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ |
||||
@ -0,0 +1,36 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Glider bvba |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; version 2 of the License. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ |
||||
#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ |
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits |
||||
* representing the power areas in the various Interrupt Registers |
||||
* (e.g. SYSCISR, Interrupt Status Register) |
||||
*/ |
||||
|
||||
#define R8A7796_PD_CA57_CPU0 0 |
||||
#define R8A7796_PD_CA57_CPU1 1 |
||||
#define R8A7796_PD_CA53_CPU0 5 |
||||
#define R8A7796_PD_CA53_CPU1 6 |
||||
#define R8A7796_PD_CA53_CPU2 7 |
||||
#define R8A7796_PD_CA53_CPU3 8 |
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#define R8A7796_PD_CA57_SCU 12 |
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#define R8A7796_PD_CR7 13 |
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#define R8A7796_PD_A3VC 14 |
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#define R8A7796_PD_3DG_A 17 |
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#define R8A7796_PD_3DG_B 18 |
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#define R8A7796_PD_CA53_SCU 21 |
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#define R8A7796_PD_A3IR 24 |
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#define R8A7796_PD_A2VC0 25 |
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#define R8A7796_PD_A2VC1 26 |
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|
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/* Always-on power area */ |
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#define R8A7796_PD_ALWAYS_ON 32 |
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|
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#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */ |
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Reference in new issue