Tom Rini
8 years ago
commit
423620b9d4
@ -0,0 +1,45 @@ |
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/* |
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* MIPS Coherence Manager (CM) Initialisation |
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* |
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* Copyright (c) 2016 Imagination Technologies Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <asm/addrspace.h> |
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#include <asm/asm.h> |
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#include <asm/cm.h> |
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#include <asm/mipsregs.h> |
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#include <asm/regdef.h> |
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|
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LEAF(mips_cm_map) |
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/* Config3 must exist for a CM to be present */ |
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mfc0 t0, CP0_CONFIG, 1 |
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bgez t0, 2f |
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mfc0 t0, CP0_CONFIG, 2 |
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bgez t0, 2f |
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|
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/* Check Config3.CMGCR to determine CM presence */ |
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mfc0 t0, CP0_CONFIG, 3 |
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and t0, t0, MIPS_CONF3_CMGCR |
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beqz t0, 2f |
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|
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/* Find the current physical GCR base address */ |
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1: MFC0 t0, CP0_CMGCRBASE |
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PTR_SLL t0, t0, 4 |
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|
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/* If the GCRs are where we want, we're done */ |
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PTR_LI t1, CONFIG_MIPS_CM_BASE |
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beq t0, t1, 2f |
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|
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/* Move the GCRs to our configured base address */ |
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PTR_LI t2, CKSEG1 |
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PTR_ADDU t0, t0, t2 |
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sw zero, GCR_BASE_UPPER(t0) |
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sw t1, GCR_BASE(t0) |
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|
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/* Re-check the GCR base */ |
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b 1b |
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|
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2: jr ra |
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END(mips_cm_map) |
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@ -0,0 +1,222 @@ |
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/dts-v1/; |
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|
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#include <dt-bindings/clock/boston-clock.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/mips-gic.h> |
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|
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "img,boston"; |
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|
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chosen { |
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stdout-path = &uart0; |
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}; |
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|
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "img,mips"; |
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reg = <0>; |
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clocks = <&clk_boston BOSTON_CLK_CPU>; |
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}; |
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}; |
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|
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memory@0 { |
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device_type = "memory"; |
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reg = <0x00000000 0x10000000>; |
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}; |
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|
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gic: interrupt-controller { |
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compatible = "mti,gic"; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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|
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timer { |
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compatible = "mti,gic-timer"; |
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
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clocks = <&clk_boston BOSTON_CLK_CPU>; |
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}; |
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}; |
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|
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pci0: pci@10000000 { |
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status = "disabled"; |
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compatible = "xlnx,axi-pcie-host-1.00.a"; |
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device_type = "pci"; |
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reg = <0x10000000 0x2000000>; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; |
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ranges = <0x02000000 0 0x40000000 |
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0x40000000 0 0x40000000>; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0 0 0 1 &pci0_intc 0>, |
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<0 0 0 2 &pci0_intc 1>, |
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<0 0 0 3 &pci0_intc 2>, |
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<0 0 0 4 &pci0_intc 3>; |
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|
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pci0_intc: interrupt-controller { |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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}; |
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}; |
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|
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pci1: pci@12000000 { |
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status = "disabled"; |
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compatible = "xlnx,axi-pcie-host-1.00.a"; |
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device_type = "pci"; |
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reg = <0x12000000 0x2000000>; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>; |
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ranges = <0x02000000 0 0x20000000 |
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0x20000000 0 0x20000000>; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0 0 0 1 &pci1_intc 0>, |
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<0 0 0 2 &pci1_intc 1>, |
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<0 0 0 3 &pci1_intc 2>, |
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<0 0 0 4 &pci1_intc 3>; |
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pci1_intc: interrupt-controller { |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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}; |
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}; |
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pci2: pci@14000000 { |
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compatible = "xlnx,axi-pcie-host-1.00.a"; |
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device_type = "pci"; |
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reg = <0x14000000 0x2000000>; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; |
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ranges = <0x02000000 0 0x16000000 |
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0x16000000 0 0x100000>; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0 0 0 1 &pci2_intc 0>, |
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<0 0 0 2 &pci2_intc 1>, |
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<0 0 0 3 &pci2_intc 2>, |
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<0 0 0 4 &pci2_intc 3>; |
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pci2_intc: interrupt-controller { |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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}; |
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pci2_root@0,0,0 { |
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compatible = "pci10ee,7021"; |
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reg = <0x00000000 0 0 0 0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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eg20t_bridge@1,0,0 { |
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compatible = "pci8086,8800"; |
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reg = <0x00010000 0 0 0 0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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eg20t_mac@2,0,1 { |
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compatible = "pci8086,8802"; |
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reg = <0x00020100 0 0 0 0>; |
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phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; |
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}; |
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eg20t_gpio: eg20t_gpio@2,0,2 { |
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compatible = "pci8086,8803"; |
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reg = <0x00020200 0 0 0 0>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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}; |
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eg20t_i2c@2,12,2 { |
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compatible = "pci8086,8817"; |
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reg = <0x00026200 0 0 0 0>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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rtc@0x68 { |
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compatible = "st,m41t81s"; |
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reg = <0x68>; |
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}; |
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}; |
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}; |
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}; |
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}; |
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plat_regs: system-controller@17ffd000 { |
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compatible = "img,boston-platform-regs", "syscon"; |
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reg = <0x17ffd000 0x1000>; |
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u-boot,dm-pre-reloc; |
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}; |
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clk_boston: clock { |
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compatible = "img,boston-clock"; |
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#clock-cells = <1>; |
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regmap = <&plat_regs>; |
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u-boot,dm-pre-reloc; |
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}; |
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reboot: syscon-reboot { |
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compatible = "syscon-reboot"; |
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regmap = <&plat_regs>; |
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offset = <0x10>; |
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mask = <0x10>; |
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}; |
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uart0: uart@17ffe000 { |
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compatible = "ns16550a"; |
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reg = <0x17ffe000 0x1000>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk_boston BOSTON_CLK_SYS>; |
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u-boot,dm-pre-reloc; |
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}; |
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lcd: lcd@17fff000 { |
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compatible = "img,boston-lcd"; |
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reg = <0x17fff000 0x8>; |
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}; |
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flash@18000000 { |
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compatible = "cfi-flash"; |
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reg = <0x18000000 0x8000000>; |
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bank-width = <2>; |
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}; |
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}; |
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@ -0,0 +1,21 @@ |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "img,xilfpga"; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "mips,m14Kc"; |
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clocks = <&ext>; |
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reg = <0>; |
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}; |
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}; |
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ext: ext { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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}; |
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}; |
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@ -0,0 +1,62 @@ |
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/dts-v1/; |
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#include "microAptiv.dtsi" |
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/ { |
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compatible = "digilent,nexys4ddr"; |
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memory { |
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device_type = "memory"; |
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reg = <0x0 0x08000000>; |
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}; |
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cpuintc: interrupt-controller@0 { |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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interrupt-controller; |
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compatible = "mti,cpu-interrupt-controller"; |
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}; |
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aliases { |
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console = &axi_uart16550; |
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}; |
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axi_ethernetlite: ethernet@10e00000 { |
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compatible = "xlnx,xps-ethernetlite-1.00.a"; |
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device_type = "network"; |
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local-mac-address = [08 86 4C 0D F7 09]; |
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phy-handle = <&phy0>; |
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reg = <0x10e00000 0x10000>; |
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xlnx,duplex = <0x1>; |
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xlnx,include-global-buffers = <0x1>; |
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xlnx,include-internal-loopback = <0x0>; |
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xlnx,include-mdio = <0x1>; |
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xlnx,instance = "axi_ethernetlite_inst"; |
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xlnx,rx-ping-pong = <0x1>; |
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xlnx,s-axi-id-width = <0x1>; |
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xlnx,tx-ping-pong = <0x1>; |
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xlnx,use-internal = <0x0>; |
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mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy0: phy@1 { |
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compatible = <0x0007c0f0 0xfffffff0>; |
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device_type = "ethernet-phy"; |
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reg = <1>; |
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} ; |
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} ; |
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} ; |
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axi_uart16550: serial@10400000 { |
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compatible = "ns16550a"; |
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reg = <0x10400000 0x10000>; |
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reg-shift = <2>; |
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reg-offset = <0x1000>; |
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clock-frequency = <50000000>; |
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}; |
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}; |
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@ -0,0 +1,62 @@ |
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/*
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* MIPS Coherence Manager (CM) Register Definitions |
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* |
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* Copyright (c) 2016 Imagination Technologies Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __MIPS_ASM_CM_H__ |
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#define __MIPS_ASM_CM_H__ |
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|
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/* Global Control Register (GCR) offsets */ |
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#define GCR_BASE 0x0008 |
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#define GCR_BASE_UPPER 0x000c |
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#define GCR_REV 0x0030 |
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#define GCR_L2_CONFIG 0x0130 |
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#define GCR_L2_TAG_ADDR 0x0600 |
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#define GCR_L2_TAG_ADDR_UPPER 0x0604 |
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#define GCR_L2_TAG_STATE 0x0608 |
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#define GCR_L2_TAG_STATE_UPPER 0x060c |
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#define GCR_L2_DATA 0x0610 |
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#define GCR_L2_DATA_UPPER 0x0614 |
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#define GCR_Cx_COHERENCE 0x2008 |
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/* GCR_REV CM versions */ |
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#define GCR_REV_CM3 0x0800 |
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/* GCR_L2_CONFIG fields */ |
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#define GCR_L2_CONFIG_ASSOC_SHIFT 0 |
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#define GCR_L2_CONFIG_ASSOC_BITS 8 |
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#define GCR_L2_CONFIG_LINESZ_SHIFT 8 |
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#define GCR_L2_CONFIG_LINESZ_BITS 4 |
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#define GCR_L2_CONFIG_SETSZ_SHIFT 12 |
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#define GCR_L2_CONFIG_SETSZ_BITS 4 |
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#define GCR_L2_CONFIG_BYPASS (1 << 20) |
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|
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/* GCR_Cx_COHERENCE */ |
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#define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) |
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#define GCR_Cx_COHERENCE_EN (0x1 << 0) |
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#ifndef __ASSEMBLY__ |
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#include <asm/io.h> |
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static inline void *mips_cm_base(void) |
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{ |
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return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); |
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} |
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static inline unsigned long mips_cm_l2_line_size(void) |
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{ |
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unsigned long l2conf, line_sz; |
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l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG); |
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line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT; |
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line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0); |
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return line_sz ? (2 << line_sz) : 0; |
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} |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* __MIPS_ASM_CM_H__ */ |
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@ -0,0 +1,16 @@ |
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if TARGET_BOSTON |
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config SYS_BOARD |
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default "boston" |
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config SYS_VENDOR |
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default "imgtec" |
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config SYS_CONFIG_NAME |
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default "boston" |
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config SYS_TEXT_BASE |
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default 0x9fc00000 if 32BIT |
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default 0xffffffff9fc00000 if 64BIT |
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endif |
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@ -0,0 +1,6 @@ |
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BOSTON BOARD |
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M: Paul Burton <paul.burton@imgtec.com> |
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S: Maintained |
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F: board/imgtec/boston/ |
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F: include/configs/boston.h |
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F: configs/boston_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# Copyright (C) 2016 Imagination Technologies
|
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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|
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obj-y += checkboard.o
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obj-y += ddr.o
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obj-y += lowlevel_init.o
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@ -0,0 +1,21 @@ |
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/*
|
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* Copyright (C) 2016 Imagination Technologies |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#ifndef __BOARD_BOSTON_LCD_H__ |
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#define __BOARD_BOSTON_LCD_H__ |
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|
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/**
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* lowlevel_display() - Display a message on Boston's LCD |
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* @msg: The string to display |
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* |
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* Display the string @msg on the 7 character LCD display of the Boston board. |
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* This is typically used for debug or to present some form of status |
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* indication to the user, allowing faults to be identified when things go |
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* wrong early enough that the UART isn't up. |
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*/ |
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void lowlevel_display(const char msg[static 8]); |
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|
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#endif /* __BOARD_BOSTON_LCD_H__ */ |
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@ -0,0 +1,26 @@ |
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/*
|
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* Copyright (C) 2016 Imagination Technologies |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#ifndef __BOARD_BOSTON_REGS_H__ |
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#define __BOARD_BOSTON_REGS_H__ |
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|
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#include <asm/addrspace.h> |
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|
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#define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000) |
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#define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000) |
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|
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/*
|
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* Platform Register Definitions |
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*/ |
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#define BOSTON_PLAT_CORE_CL (BOSTON_PLAT_BASE + 0x04) |
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|
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#define BOSTON_PLAT_DDR3STAT (BOSTON_PLAT_BASE + 0x14) |
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# define BOSTON_PLAT_DDR3STAT_CALIB (1 << 2) |
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|
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#define BOSTON_PLAT_DDRCONF0 (BOSTON_PLAT_BASE + 0x38) |
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# define BOSTON_PLAT_DDRCONF0_SIZE (0xf << 0) |
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|
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#endif /* __BOARD_BOSTON_REGS_H__ */ |
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@ -0,0 +1,30 @@ |
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/*
|
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* Copyright (C) 2016 Imagination Technologies |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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|
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#include <asm/io.h> |
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#include <asm/mipsregs.h> |
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|
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#include "boston-lcd.h" |
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#include "boston-regs.h" |
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|
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int checkboard(void) |
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{ |
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u32 changelist; |
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|
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lowlevel_display("U-boot "); |
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|
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printf("Board: MIPS Boston\n"); |
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|
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printf("CPU: 0x%08x", read_c0_prid()); |
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changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL); |
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if (changelist > 1) |
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printf(" cl%x", changelist); |
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putc('\n'); |
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|
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return 0; |
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} |
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@ -0,0 +1,30 @@ |
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/*
|
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* Copyright (C) 2016 Imagination Technologies |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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|
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#include <asm/io.h> |
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|
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#include "boston-regs.h" |
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|
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phys_size_t initdram(int board_type) |
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{ |
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u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0); |
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|
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return (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << 30; |
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} |
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|
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ulong board_get_usable_ram_top(ulong total_size) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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|
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if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) { |
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/* 2GB wrapped around to 0 */ |
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return CKSEG0ADDR(256 << 20); |
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} |
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|
||||
return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20)); |
||||
} |
||||
@ -0,0 +1,56 @@ |
||||
/* |
||||
* Copyright (C) 2016 Imagination Technologies |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
|
||||
#include <asm/addrspace.h> |
||||
#include <asm/asm.h> |
||||
#include <asm/mipsregs.h> |
||||
#include <asm/regdef.h> |
||||
|
||||
#include "boston-regs.h" |
||||
|
||||
.data |
||||
|
||||
msg_ddr_cal: .ascii "DDR Cal " |
||||
msg_ddr_ok: .ascii "DDR OK " |
||||
|
||||
.text |
||||
|
||||
LEAF(lowlevel_init) |
||||
move s0, ra |
||||
|
||||
PTR_LA a0, msg_ddr_cal |
||||
bal lowlevel_display |
||||
|
||||
PTR_LI t0, BOSTON_PLAT_DDR3STAT |
||||
1: lw t1, 0(t0) |
||||
andi t1, t1, BOSTON_PLAT_DDR3STAT_CALIB |
||||
beqz t1, 1b |
||||
|
||||
PTR_LA a0, msg_ddr_ok |
||||
bal lowlevel_display |
||||
|
||||
move v0, zero |
||||
jr s0 |
||||
END(lowlevel_init) |
||||
|
||||
LEAF(lowlevel_display) |
||||
.set push
|
||||
.set noat
|
||||
PTR_LI AT, BOSTON_LCD_BASE |
||||
#ifdef CONFIG_64BIT |
||||
ld k1, 0(a0) |
||||
sd k1, 0(AT) |
||||
#else |
||||
lw k1, 0(a0) |
||||
sw k1, 0(AT) |
||||
lw k1, 4(a0) |
||||
sw k1, 4(AT) |
||||
#endif |
||||
.set pop
|
||||
1: jr ra |
||||
END(lowlevel_display) |
||||
@ -0,0 +1,15 @@ |
||||
if TARGET_XILFPGA |
||||
|
||||
config SYS_BOARD |
||||
default "xilfpga" |
||||
|
||||
config SYS_VENDOR |
||||
default "imgtec" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "imgtec_xilfpga" |
||||
|
||||
config SYS_TEXT_BASE |
||||
default 0x80C00000 |
||||
|
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
XILFPGA BOARD |
||||
M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
||||
S: Maintained |
||||
F: board/imgtec/xilfpga |
||||
F: include/configs/xilfpga.h |
||||
F: configs/imgtec_xilfpga_defconfig |
||||
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (C) 2016, Imagination Technologies Ltd.
|
||||
# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
obj-y := xilfpga.o
|
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* Copyright (C) 2016, Imagination Technologies Ltd. |
||||
* |
||||
* Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com |
||||
*/ |
||||
|
||||
MIPSfpga |
||||
======================================= |
||||
|
||||
MIPSfpga is an FPGA based development platform by Imagination Technologies |
||||
As we are dealing with a MIPS core instantiated on an FPGA, specifications |
||||
are fluid and can be varied in RTL. |
||||
|
||||
The example project provided by IMGTEC runs on the Nexys4DDR board by |
||||
Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about |
||||
the example project and the Nexys4DDR board: |
||||
|
||||
- microAptiv UP core m14Kc |
||||
- 50MHz clock speed |
||||
- 128Mbyte DDR RAM at 0x0000_0000 |
||||
- 8Kbyte RAM at 0x1000_0000 |
||||
- axi_intc at 0x1020_0000 |
||||
- axi_uart16550 at 0x1040_0000 |
||||
- axi_gpio at 0x1060_0000 |
||||
- axi_i2c at 0x10A0_0000 |
||||
- custom_gpio at 0x10C0_0000 |
||||
- axi_ethernetlite at 0x10E0_0000 |
||||
- 8Kbyte BootRAM at 0x1FC0_0000 |
||||
- 16Mbyte QPI at 0x1D00_0000 |
||||
|
||||
Boot protocol: |
||||
-------------- |
||||
|
||||
The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. |
||||
This is for easy reprogrammibility via JTAG. |
||||
|
||||
DDR initialization is already handled by a HW IP block. |
||||
|
||||
When the example project bitstream is loaded, the cpu_reset button |
||||
needs to be pressed. |
||||
|
||||
The bootram initializes the cache and axi_uart |
||||
Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000 |
||||
|
||||
If there is, then that is considered as u-boot. u-boot is copied from |
||||
0x1D40_0000 to memory and the bootram jumps into u-boot code. |
||||
|
||||
At this point, the board is ready to load the Linux kernel + buildroot initramfs |
||||
|
||||
This can be done in multiple ways: |
||||
|
||||
1- JTAG load the binary and jump into it. |
||||
2- Load kernel stored in the QSPI flash at 0x1D80_0000 |
||||
3- Load uImage via tftp. Ethernet works in u-boot. |
||||
e.g. env set server ip 192.168.154.45; dhcp uImage; bootm |
||||
@ -0,0 +1,20 @@ |
||||
/*
|
||||
* Imagination Technologies MIPSfpga platform code |
||||
* |
||||
* Copyright (C) 2016, Imagination Technologies Ltd. |
||||
* |
||||
* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
/* initialize the DDR Controller and PHY */ |
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
/* MIG IP block is smart and doesn't need SW
|
||||
* to do any init */ |
||||
return CONFIG_SYS_SDRAM_SIZE; /* in bytes */ |
||||
} |
||||
@ -0,0 +1,41 @@ |
||||
CONFIG_MIPS=y |
||||
CONFIG_TARGET_BOSTON=y |
||||
CONFIG_SYS_TEXT_BASE=0x9fc00000 |
||||
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set |
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
||||
CONFIG_MIPS_BOOT_FDT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="img,boston" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_FIT_BEST_MATCH=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="boston # " |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_SNTP=y |
||||
CONFIG_CMD_DNS=y |
||||
CONFIG_CMD_LINK_LOCAL=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_CLK=y |
||||
CONFIG_MTD=y |
||||
CONFIG_CFI_FLASH=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_PCH_GBE=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_PCI_XILINX=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_LZ4=y |
||||
@ -0,0 +1,42 @@ |
||||
CONFIG_MIPS=y |
||||
CONFIG_TARGET_BOSTON=y |
||||
CONFIG_SYS_TEXT_BASE=0x9fc00000 |
||||
CONFIG_SYS_LITTLE_ENDIAN=y |
||||
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set |
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
||||
CONFIG_MIPS_BOOT_FDT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="img,boston" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_FIT_BEST_MATCH=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="boston # " |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_SNTP=y |
||||
CONFIG_CMD_DNS=y |
||||
CONFIG_CMD_LINK_LOCAL=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_CLK=y |
||||
CONFIG_MTD=y |
||||
CONFIG_CFI_FLASH=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_PCH_GBE=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_PCI_XILINX=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_LZ4=y |
||||
@ -0,0 +1,41 @@ |
||||
CONFIG_MIPS=y |
||||
CONFIG_TARGET_BOSTON=y |
||||
CONFIG_CPU_MIPS64_R2=y |
||||
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set |
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
||||
CONFIG_MIPS_BOOT_FDT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="img,boston" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_FIT_BEST_MATCH=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="boston # " |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_SNTP=y |
||||
CONFIG_CMD_DNS=y |
||||
CONFIG_CMD_LINK_LOCAL=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_CLK=y |
||||
CONFIG_MTD=y |
||||
CONFIG_CFI_FLASH=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_PCH_GBE=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_PCI_XILINX=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_LZ4=y |
||||
@ -0,0 +1,42 @@ |
||||
CONFIG_MIPS=y |
||||
CONFIG_TARGET_BOSTON=y |
||||
CONFIG_SYS_LITTLE_ENDIAN=y |
||||
CONFIG_CPU_MIPS64_R2=y |
||||
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set |
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
||||
CONFIG_MIPS_BOOT_FDT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="img,boston" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_FIT_BEST_MATCH=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="boston # " |
||||
# CONFIG_CMD_ELF is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_LOADS is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_SNTP=y |
||||
CONFIG_CMD_DNS=y |
||||
CONFIG_CMD_LINK_LOCAL=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_CLK=y |
||||
CONFIG_MTD=y |
||||
CONFIG_CFI_FLASH=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_PCH_GBE=y |
||||
CONFIG_DM_PCI=y |
||||
CONFIG_PCI_XILINX=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_LZ4=y |
||||
@ -0,0 +1,25 @@ |
||||
CONFIG_MIPS=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x600 |
||||
CONFIG_TARGET_XILFPGA=y |
||||
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
||||
CONFIG_MIPS_BOOT_FDT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr" |
||||
CONFIG_BOOTDELAY=5 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="MIPSfpga # " |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_SAVEENV is not set |
||||
CONFIG_CMD_MEMINFO=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_TIME=y |
||||
CONFIG_OF_EMBED=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_NETCONSOLE=y |
||||
CONFIG_CLK=y |
||||
CONFIG_XILINX_EMACLITE=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_CMD_DHRYSTONE=y |
||||
@ -0,0 +1,58 @@ |
||||
MIPS Boston Development Board |
||||
|
||||
--------- |
||||
About |
||||
--------- |
||||
|
||||
The MIPS Boston development board is built around an FPGA & 3 PCIe controllers, |
||||
one of which is connected to an Intel EG20T Platform Controller Hub which |
||||
provides most connectivity to the board. It is used during the development & |
||||
testing of both new CPUs and the software support for them. It is essentially |
||||
the successor of the older MIPS Malta board. |
||||
|
||||
-------- |
||||
QEMU |
||||
-------- |
||||
|
||||
U-Boot can be run on a currently out-of-tree branch of QEMU with support for |
||||
the Boston board added. This QEMU code can currently be found in the "boston" |
||||
branch of git://git.linux-mips.org/pub/scm/paul/qemu.git and used like so: |
||||
|
||||
$ git clone git://git.linux-mips.org/pub/scm/paul/qemu.git -b boston |
||||
$ cd qemu |
||||
$ ./configure --target-list=mips64el-softmmu |
||||
$ make |
||||
$ ./mips64el-softmmu/qemu-system-mips64el -M boston -m 2G \ |
||||
-bios u-boot.bin -serial stdio |
||||
|
||||
Please note that QEMU will default to emulating the I6400 CPU which implements |
||||
the MIPS64r6 ISA, and at the time of writing doesn't implement any earlier CPUs |
||||
with support for the CPS features the Boston board relies upon. You will |
||||
therefore need to configure U-Boot to build for MIPSr6 in order to obtain a |
||||
binary that will work in QEMU. |
||||
|
||||
------------- |
||||
Toolchain |
||||
------------- |
||||
|
||||
If building for MIPSr6 then you will need a toolchain including GCC 5.x or |
||||
newer, or the Codescape toolchain available for download from Imagination |
||||
Technologies: |
||||
|
||||
http://codescape-mips-sdk.imgtec.com/components/toolchain/2015.06-05/ |
||||
|
||||
The "IMG GNU Linux Toolchain" is capable of building for all current MIPS ISAs, |
||||
architecture revisions & both endiannesses. |
||||
|
||||
-------- |
||||
TODO |
||||
-------- |
||||
|
||||
- AHCI support |
||||
- CPU driver |
||||
- Exception handling (+UHI?) |
||||
- Flash support |
||||
- IOCU support |
||||
- L2 cache support |
||||
- More general LCD display driver |
||||
- Multi-arch-variant multi-endian fat binary |
||||
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm.h> |
||||
#include <dt-bindings/clock/boston-clock.h> |
||||
#include <regmap.h> |
||||
#include <syscon.h> |
||||
|
||||
struct clk_boston { |
||||
struct regmap *regmap; |
||||
}; |
||||
|
||||
#define BOSTON_PLAT_MMCMDIV 0x30 |
||||
# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0) |
||||
# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8) |
||||
# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16) |
||||
# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24) |
||||
|
||||
static uint32_t ext_field(uint32_t val, uint32_t mask) |
||||
{ |
||||
return (val & mask) >> (ffs(mask) - 1); |
||||
} |
||||
|
||||
static ulong clk_boston_get_rate(struct clk *clk) |
||||
{ |
||||
struct clk_boston *state = dev_get_platdata(clk->dev); |
||||
uint32_t in_rate, mul, div; |
||||
uint mmcmdiv; |
||||
int err; |
||||
|
||||
err = regmap_read(state->regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv); |
||||
if (err) |
||||
return 0; |
||||
|
||||
in_rate = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT); |
||||
mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL); |
||||
|
||||
switch (clk->id) { |
||||
case BOSTON_CLK_SYS: |
||||
div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV); |
||||
break; |
||||
case BOSTON_CLK_CPU: |
||||
div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV); |
||||
break; |
||||
default: |
||||
return 0; |
||||
} |
||||
|
||||
return (in_rate * mul * 1000000) / div; |
||||
} |
||||
|
||||
const struct clk_ops clk_boston_ops = { |
||||
.get_rate = clk_boston_get_rate, |
||||
}; |
||||
|
||||
static int clk_boston_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct clk_boston *state = dev_get_platdata(dev); |
||||
struct udevice *syscon; |
||||
int err; |
||||
|
||||
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, |
||||
"regmap", &syscon); |
||||
if (err) { |
||||
error("unable to find syscon device\n"); |
||||
return err; |
||||
} |
||||
|
||||
state->regmap = syscon_get_regmap(syscon); |
||||
if (!state->regmap) { |
||||
error("unable to find regmap\n"); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct udevice_id clk_boston_match[] = { |
||||
{ |
||||
.compatible = "img,boston-clock", |
||||
}, |
||||
{ /* sentinel */ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(clk_boston) = { |
||||
.name = "boston_clock", |
||||
.id = UCLASS_CLK, |
||||
.of_match = clk_boston_match, |
||||
.ofdata_to_platdata = clk_boston_ofdata_to_platdata, |
||||
.platdata_auto_alloc_size = sizeof(struct clk_boston), |
||||
.ops = &clk_boston_ops, |
||||
}; |
||||
@ -0,0 +1,220 @@ |
||||
/*
|
||||
* Xilinx AXI Bridge for PCI Express Driver |
||||
* |
||||
* Copyright (C) 2016 Imagination Technologies |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <pci.h> |
||||
|
||||
#include <asm/io.h> |
||||
|
||||
/**
|
||||
* struct xilinx_pcie - Xilinx PCIe controller state |
||||
* @hose: The parent classes PCI controller state |
||||
* @cfg_base: The base address of memory mapped configuration space |
||||
*/ |
||||
struct xilinx_pcie { |
||||
struct pci_controller hose; |
||||
void *cfg_base; |
||||
}; |
||||
|
||||
/* Register definitions */ |
||||
#define XILINX_PCIE_REG_PSCR 0x144 |
||||
#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) |
||||
|
||||
/**
|
||||
* pcie_xilinx_link_up() - Check whether the PCIe link is up |
||||
* @pcie: Pointer to the PCI controller state |
||||
* |
||||
* Checks whether the PCIe link for the given device is up or down. |
||||
* |
||||
* Return: true if the link is up, else false |
||||
*/ |
||||
static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie) |
||||
{ |
||||
uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR); |
||||
|
||||
return pscr & XILINX_PCIE_REG_PSCR_LNKUP; |
||||
} |
||||
|
||||
/**
|
||||
* pcie_xilinx_config_address() - Calculate the address of a config access |
||||
* @pcie: Pointer to the PCI controller state |
||||
* @bdf: Identifies the PCIe device to access |
||||
* @offset: The offset into the device's configuration space |
||||
* @paddress: Pointer to the pointer to write the calculates address to |
||||
* |
||||
* Calculates the address that should be accessed to perform a PCIe |
||||
* configuration space access for a given device identified by the PCIe |
||||
* controller device @pcie and the bus, device & function numbers in @bdf. If |
||||
* access to the device is not valid then the function will return an error |
||||
* code. Otherwise the address to access will be written to the pointer pointed |
||||
* to by @paddress. |
||||
* |
||||
* Return: 0 on success, else -ENODEV |
||||
*/ |
||||
static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf, |
||||
uint offset, void **paddress) |
||||
{ |
||||
unsigned int bus = PCI_BUS(bdf); |
||||
unsigned int dev = PCI_DEV(bdf); |
||||
unsigned int func = PCI_FUNC(bdf); |
||||
void *addr; |
||||
|
||||
if ((bus > 0) && !pcie_xilinx_link_up(pcie)) |
||||
return -ENODEV; |
||||
|
||||
/*
|
||||
* Busses 0 (host-PCIe bridge) & 1 (its immediate child) are |
||||
* limited to a single device each. |
||||
*/ |
||||
if ((bus < 2) && (dev > 0)) |
||||
return -ENODEV; |
||||
|
||||
addr = pcie->cfg_base; |
||||
addr += bus << 20; |
||||
addr += dev << 15; |
||||
addr += func << 12; |
||||
addr += offset; |
||||
*paddress = addr; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* pcie_xilinx_read_config() - Read from configuration space |
||||
* @pcie: Pointer to the PCI controller state |
||||
* @bdf: Identifies the PCIe device to access |
||||
* @offset: The offset into the device's configuration space |
||||
* @valuep: A pointer at which to store the read value |
||||
* @size: Indicates the size of access to perform |
||||
* |
||||
* Read a value of size @size from offset @offset within the configuration |
||||
* space of the device identified by the bus, device & function numbers in @bdf |
||||
* on the PCI bus @bus. |
||||
* |
||||
* Return: 0 on success, else -ENODEV or -EINVAL |
||||
*/ |
||||
static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf, |
||||
uint offset, ulong *valuep, |
||||
enum pci_size_t size) |
||||
{ |
||||
struct xilinx_pcie *pcie = dev_get_priv(bus); |
||||
void *address; |
||||
int err; |
||||
|
||||
err = pcie_xilinx_config_address(pcie, bdf, offset, &address); |
||||
if (err < 0) { |
||||
*valuep = pci_get_ff(size); |
||||
return 0; |
||||
} |
||||
|
||||
switch (size) { |
||||
case PCI_SIZE_8: |
||||
*valuep = __raw_readb(address); |
||||
return 0; |
||||
case PCI_SIZE_16: |
||||
*valuep = __raw_readw(address); |
||||
return 0; |
||||
case PCI_SIZE_32: |
||||
*valuep = __raw_readl(address); |
||||
return 0; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* pcie_xilinx_write_config() - Write to configuration space |
||||
* @pcie: Pointer to the PCI controller state |
||||
* @bdf: Identifies the PCIe device to access |
||||
* @offset: The offset into the device's configuration space |
||||
* @value: The value to write |
||||
* @size: Indicates the size of access to perform |
||||
* |
||||
* Write the value @value of size @size from offset @offset within the |
||||
* configuration space of the device identified by the bus, device & function |
||||
* numbers in @bdf on the PCI bus @bus. |
||||
* |
||||
* Return: 0 on success, else -ENODEV or -EINVAL |
||||
*/ |
||||
static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, |
||||
uint offset, ulong value, |
||||
enum pci_size_t size) |
||||
{ |
||||
struct xilinx_pcie *pcie = dev_get_priv(bus); |
||||
void *address; |
||||
int err; |
||||
|
||||
err = pcie_xilinx_config_address(pcie, bdf, offset, &address); |
||||
if (err < 0) |
||||
return 0; |
||||
|
||||
switch (size) { |
||||
case PCI_SIZE_8: |
||||
__raw_writeb(value, address); |
||||
return 0; |
||||
case PCI_SIZE_16: |
||||
__raw_writew(value, address); |
||||
return 0; |
||||
case PCI_SIZE_32: |
||||
__raw_writel(value, address); |
||||
return 0; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state |
||||
* @dev: A pointer to the device being operated on |
||||
* |
||||
* Translate relevant data from the device tree pertaining to device @dev into |
||||
* state that the driver will later make use of. This state is stored in the |
||||
* device's private data structure. |
||||
* |
||||
* Return: 0 on success, else -EINVAL |
||||
*/ |
||||
static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev) |
||||
{ |
||||
struct xilinx_pcie *pcie = dev_get_priv(dev); |
||||
struct fdt_resource reg_res; |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int err; |
||||
|
||||
err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg", |
||||
0, ®_res); |
||||
if (err < 0) { |
||||
error("\"reg\" resource not found\n"); |
||||
return err; |
||||
} |
||||
|
||||
pcie->cfg_base = map_physmem(reg_res.start, |
||||
fdt_resource_size(®_res), |
||||
MAP_NOCACHE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_pci_ops pcie_xilinx_ops = { |
||||
.read_config = pcie_xilinx_read_config, |
||||
.write_config = pcie_xilinx_write_config, |
||||
}; |
||||
|
||||
static const struct udevice_id pcie_xilinx_ids[] = { |
||||
{ .compatible = "xlnx,axi-pcie-host-1.00.a" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(pcie_xilinx) = { |
||||
.name = "pcie_xilinx", |
||||
.id = UCLASS_PCI, |
||||
.of_match = pcie_xilinx_ids, |
||||
.ops = &pcie_xilinx_ops, |
||||
.ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata, |
||||
.priv_auto_alloc_size = sizeof(struct xilinx_pcie), |
||||
}; |
||||
@ -0,0 +1,81 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __CONFIGS_BOSTON_H__ |
||||
#define __CONFIGS_BOSTON_H__ |
||||
|
||||
/*
|
||||
* General board configuration |
||||
*/ |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/*
|
||||
* CPU |
||||
*/ |
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000 |
||||
|
||||
/*
|
||||
* PCI |
||||
*/ |
||||
#define CONFIG_PCI |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_CMD_PCI |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#ifdef CONFIG_64BIT |
||||
# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 |
||||
#else |
||||
# define CONFIG_SYS_SDRAM_BASE 0x80000000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
||||
|
||||
/*
|
||||
* Console |
||||
*/ |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Flash |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#ifdef CONFIG_64BIT |
||||
# define CONFIG_ENV_ADDR \ |
||||
(0xffffffffb8000000 + (128 << 20) - CONFIG_ENV_SIZE) |
||||
#else |
||||
# define CONFIG_ENV_ADDR \ |
||||
(0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE) |
||||
#endif |
||||
|
||||
#endif /* __CONFIGS_BOSTON_H__ */ |
||||
@ -0,0 +1,68 @@ |
||||
/*
|
||||
* Copyright (C) 2016, Imagination Technologies Ltd. |
||||
* |
||||
* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Imagination Technologies Ltd. MIPSfpga |
||||
*/ |
||||
|
||||
#ifndef __XILFPGA_CONFIG_H |
||||
#define __XILFPGA_CONFIG_H |
||||
|
||||
/* BootROM + MIG is pretty smart. DDR and Cache initialized */ |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT |
||||
|
||||
/*--------------------------------------------
|
||||
* CPU configuration |
||||
*/ |
||||
/* CPU Timer rate */ |
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 |
||||
|
||||
/* Cache Configuration */ |
||||
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT |
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* Memory Layout |
||||
*/ |
||||
|
||||
/* SDRAM Configuration (for final code, data, stack, heap) */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 |
||||
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ |
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* Commands |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
/*-------------------------------------------------
|
||||
* FLASH configuration |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/*------------------------------------------------------------
|
||||
* Console Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* -------------------------------------------------
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_ENV_IS_NOWHERE 1 |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Board boot configuration |
||||
*/ |
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
#endif /* __XILFPGA_CONFIG_H */ |
||||
@ -0,0 +1,13 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ |
||||
#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ |
||||
|
||||
#define BOSTON_CLK_SYS 0 |
||||
#define BOSTON_CLK_CPU 1 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ |
||||
@ -0,0 +1,9 @@ |
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H |
||||
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H |
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h> |
||||
|
||||
#define GIC_SHARED 0 |
||||
#define GIC_LOCAL 1 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue