parent
befe61a190
commit
43c377fc0a
@ -0,0 +1,97 @@ |
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/* |
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* Memory Setup stuff - taken from ??? |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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/* some parameters for the board */ |
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SYSCON1: .long 0x80000100 |
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SYSCON2: .long 0x80001100 |
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SYSCON3: .long 0x80002200 |
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MEMCFG1: .long 0x80000180 |
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MEMCFG2: .long 0x800001C0 |
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SDCONF: .long 0x80002300 |
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SDRFPR: .long 0x80002340 |
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syscon1_val: .long 0x00040100 |
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syscon2_val: .long 0x00000102 |
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syscon3_val: .long 0x0000020E |
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memcfg1_val: .long 0x1f101710 |
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memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
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memcfg2_val: .long 0x00001f13 @ upper 16 bits are reserved for CS7 + CS6
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sdrfpr_val: .long 0x00000240 |
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sdconf_val: .long 0x00000522 |
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/* setting up the memory */ |
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.globl memsetup
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memsetup: |
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/* |
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* SYSCON1-3 |
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*/ |
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ldr r0, SYSCON1 |
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ldr r1, syscon1_val |
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str r1, [r0] |
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ldr r0, SYSCON2 |
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ldr r1, syscon2_val |
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str r1, [r0] |
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ldr r0, SYSCON3 |
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ldr r1, syscon3_val |
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str r1, [r0] |
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/* |
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* MEMCFG1 |
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*/ |
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ldr r0, MEMCFG1 |
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ldr r1, memcfg1_val |
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str r1, [r0] |
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/* |
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* MEMCFG2 |
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*/ |
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ldr r0, MEMCFG2 |
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ldr r2, [r0] |
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ldr r1, memcfg2_mask |
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bic r2, r2, r1 |
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ldr r1, memcfg2_val |
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orr r2, r2, r1 |
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str r2, [r0] |
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/* |
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* SDRFPR,SDCONF |
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*/ |
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ldr r0, SDCONF |
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ldr r1, sdconf_val |
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str r1, [r0] |
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ldr r0, SDRFPR |
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ldr r1, sdrfpr_val |
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str r1, [r0] |
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/* everything is fine now */ |
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mov pc, lr |
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@ -0,0 +1,87 @@ |
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/* |
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* Memory Setup stuff - taken from ??? |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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/* some parameters for the board */ |
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SYSCON2: .long 0x80001100 |
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MEMCFG1: .long 0x80000180 |
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MEMCFG2: .long 0x800001C0 |
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DRFPR: .long 0x80000200 |
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syscon2_mask: .long 0x00000004 |
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memcfg1_val: .long 0x160c1414 |
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memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
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memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
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drfpr_val: .long 0x00000081 |
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/* setting up the memory */ |
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.globl memsetup
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memsetup: |
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/* |
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* DRFPR |
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* 64kHz DRAM refresh |
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*/ |
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ldr r0, DRFPR |
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ldr r1, drfpr_val |
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str r1, [r0] |
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/* |
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* SYSCON2: clear bit 2, DRAM is 32 bits wide |
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*/ |
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ldr r0, SYSCON2 |
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ldr r2, [r0] |
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ldr r1, syscon2_mask |
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bic r2, r2, r1 |
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str r2, [r0] |
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/* |
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* MEMCFG1 |
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* Setting up Keyboard at CS3, 8 Bit, 3 Waitstates |
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* Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates |
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* Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates |
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*/ |
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ldr r0, MEMCFG1 |
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ldr r1, memcfg1_val |
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str r1, [r0] |
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/* |
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* MEMCFG2 |
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* Setting up ? with 0 |
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* |
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*/ |
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ldr r0, MEMCFG2 |
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ldr r2, [r0] |
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ldr r1, memcfg2_mask |
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bic r2, r2, r1 |
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ldr r1, memcfg2_val |
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orr r2, r2, r1 |
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str r2, [r0] |
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/* everything is fine now */ |
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mov pc, lr |
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@ -0,0 +1,168 @@ |
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/* |
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* Memory Setup stuff - taken from blob memsetup.S |
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* |
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* |
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* Modified for the Samsung SMDK2410 by |
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* (C) Copyright 2002 |
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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/* some parameters for the board */ |
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/* |
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* |
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* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S |
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* |
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* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
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* |
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*/ |
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#define BWSCON 0x48000000 |
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/* BWSCON */ |
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#define DW8 (0x0) |
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#define DW16 (0x1) |
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#define DW32 (0x2) |
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#define WAIT (0x1<<2) |
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#define UBLB (0x1<<3) |
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#define B1_BWSCON (DW32) |
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#define B2_BWSCON (DW16) |
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#define B3_BWSCON (DW16 + WAIT + UBLB) |
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#define B4_BWSCON (DW16) |
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#define B5_BWSCON (DW16) |
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#define B6_BWSCON (DW32) |
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#define B7_BWSCON (DW32) |
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/* BANK0CON */ |
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#define B0_Tacs 0x0 /* 0clk */ |
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#define B0_Tcos 0x0 /* 0clk */ |
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#define B0_Tacc 0x7 /* 14clk */ |
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#define B0_Tcoh 0x0 /* 0clk */ |
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#define B0_Tah 0x0 /* 0clk */ |
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#define B0_Tacp 0x0 |
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#define B0_PMC 0x0 /* normal */ |
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/* BANK1CON */ |
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#define B1_Tacs 0x0 /* 0clk */ |
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#define B1_Tcos 0x0 /* 0clk */ |
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#define B1_Tacc 0x7 /* 14clk */ |
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#define B1_Tcoh 0x0 /* 0clk */ |
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#define B1_Tah 0x0 /* 0clk */ |
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#define B1_Tacp 0x0 |
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#define B1_PMC 0x0 |
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#define B2_Tacs 0x0 |
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#define B2_Tcos 0x0 |
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#define B2_Tacc 0x7 |
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#define B2_Tcoh 0x0 |
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#define B2_Tah 0x0 |
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#define B2_Tacp 0x0 |
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#define B2_PMC 0x0 |
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#define B3_Tacs 0x0 /* 0clk */ |
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#define B3_Tcos 0x3 /* 4clk */ |
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#define B3_Tacc 0x7 /* 14clk */ |
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#define B3_Tcoh 0x1 /* 1clk */ |
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#define B3_Tah 0x0 /* 0clk */ |
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#define B3_Tacp 0x3 /* 6clk */ |
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#define B3_PMC 0x0 /* normal */ |
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#define B4_Tacs 0x0 /* 0clk */ |
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#define B4_Tcos 0x0 /* 0clk */ |
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#define B4_Tacc 0x7 /* 14clk */ |
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#define B4_Tcoh 0x0 /* 0clk */ |
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#define B4_Tah 0x0 /* 0clk */ |
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#define B4_Tacp 0x0 |
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#define B4_PMC 0x0 /* normal */ |
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#define B5_Tacs 0x0 /* 0clk */ |
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#define B5_Tcos 0x0 /* 0clk */ |
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#define B5_Tacc 0x7 /* 14clk */ |
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#define B5_Tcoh 0x0 /* 0clk */ |
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#define B5_Tah 0x0 /* 0clk */ |
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#define B5_Tacp 0x0 |
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#define B5_PMC 0x0 /* normal */ |
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#define B6_MT 0x3 /* SDRAM */ |
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#define B6_Trcd 0x1 |
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#define B6_SCAN 0x1 /* 9bit */ |
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#define B7_MT 0x3 /* SDRAM */ |
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#define B7_Trcd 0x1 /* 3clk */ |
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#define B7_SCAN 0x1 /* 9bit */ |
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/* REFRESH parameter */ |
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#define REFEN 0x1 /* Refresh enable */ |
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
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#define Trp 0x0 /* 2clk */ |
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#define Trc 0x3 /* 7clk */ |
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#define Tchr 0x2 /* 3clk */ |
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#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ |
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/**************************************/ |
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_TEXT_BASE: |
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.word TEXT_BASE
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.globl memsetup
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memsetup: |
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/* memory control configuration */ |
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/* make r0 relative the current location so that it */ |
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/* reads SMRDATA out of FLASH rather than memory ! */ |
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ldr r0, =SMRDATA |
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ldr r1, _TEXT_BASE |
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sub r0, r0, r1 |
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ldr r1, =BWSCON /* Bus Width Status Controller */ |
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add r2, r0, #13*4 |
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0: |
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ldr r3, [r0], #4 |
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str r3, [r1], #4 |
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cmp r2, r0 |
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bne 0b |
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/* everything is fine now */ |
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mov pc, lr |
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.ltorg |
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/* the literal pools origin */ |
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SMRDATA: |
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) |
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) |
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) |
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) |
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) |
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) |
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) |
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) |
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) |
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) |
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.word 0x32
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.word 0x30
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.word 0x30
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