@ -23,22 +23,12 @@
* Foundation , Inc . , 59 Temple Place , Suite 330 , Boston ,
* MA 02111 - 1307 USA
*/
# ifndef _SDP4430_MUX_DATA_H
# define _SDP4430_MUX_DATA_H
# ifndef _PANDA_H_
# define _PANDA_H_
# include <asm/io.h>
# include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array [ ] = {
{ GPMC_AD0 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat0 */
{ GPMC_AD1 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat1 */
{ GPMC_AD2 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat2 */
{ GPMC_AD3 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat3 */
{ GPMC_AD4 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat4 */
{ GPMC_AD5 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat5 */
{ GPMC_AD6 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat6 */
{ GPMC_AD7 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_dat7 */
const struct pad_conf_entry core_padconf_array_non_essential [ ] = {
{ GPMC_AD8 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 ) } , /* gpio_32 */
{ GPMC_AD9 , ( PTU | IEN | M3 ) } , /* gpio_33 */
{ GPMC_AD10 , ( PTU | IEN | M3 ) } , /* gpio_34 */
@ -53,7 +43,7 @@ const struct pad_conf_entry core_padconf_array[] = {
{ GPMC_A19 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_row7 */
{ GPMC_A20 , ( IEN | M3 ) } , /* gpio_44 */
{ GPMC_A21 , ( M3 ) } , /* gpio_45 */
{ GPMC_A22 , ( M3 ) } , /* gpio_4 6 */
{ GPMC_A22 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col 6 */
{ GPMC_A23 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col7 */
{ GPMC_A24 , ( PTD | M3 ) } , /* gpio_48 */
{ GPMC_A25 , ( PTD | M3 ) } , /* gpio_49 */
@ -64,14 +54,12 @@ const struct pad_conf_entry core_padconf_array[] = {
{ GPMC_NWP , ( M3 ) } , /* gpio_54 */
{ GPMC_CLK , ( PTD | M3 ) } , /* gpio_55 */
{ GPMC_NADV_ALE , ( M3 ) } , /* gpio_56 */
{ GPMC_NOE , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1 ) } , /* sdmmc2_clk */
{ GPMC_NWE , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* sdmmc2_cmd */
{ GPMC_NBE0_CLE , ( M3 ) } , /* gpio_59 */
{ GPMC_NBE1 , ( PTD | M3 ) } , /* gpio_60 */
{ GPMC_WAIT0 , ( PTU | IEN | M3 ) } , /* gpio_61 */
{ GPMC_WAIT1 , ( PTD | OFF_ EN | OFF_PD | OFF_OUT_PTD | M3 ) } , /* gpio_62 */
{ GPMC_WAIT1 , ( I EN | M3 ) } , /* gpio_62 */
{ C2C_DATA11 , ( PTD | M3 ) } , /* gpio_100 */
{ C2C_DATA12 , ( PTU | IEN | M3 ) } , /* gpio_101 */
{ C2C_DATA12 , ( M1 ) } , /* dsi1_te0 */
{ C2C_DATA13 , ( PTD | M3 ) } , /* gpio_102 */
{ C2C_DATA14 , ( M1 ) } , /* dsi2_te0 */
{ C2C_DATA15 , ( PTD | M3 ) } , /* gpio_104 */
@ -96,14 +84,14 @@ const struct pad_conf_entry core_padconf_array[] = {
{ CAM_SHUTTER , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0 ) } , /* cam_shutter */
{ CAM_STROBE , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0 ) } , /* cam_strobe */
{ CAM_GLOBALRESET , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 ) } , /* gpio_83 */
{ USBB1_ULPITLL_CLK , ( PTD | IEN | OFF_EN | OFF_PD | OFF_ IN | M4 ) } , /* usbb1_ulpiphy_clk */
{ USBB1_ULPITLL_STP , ( OFF_EN | OFF_OUT_PTD | M4 ) } , /* usbb1_ulpiphy_stp */
{ USBB1_ULPITLL_DIR , ( IEN | OFF_EN | OFF_PD | OFF_ IN | M4 ) } , /* usbb1_ulpiphy_dir */
{ USBB1_ULPITLL_NXT , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_nxt */
{ USBB1_ULPITLL_DAT0 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat0 */
{ USBB1_ULPITLL_DAT1 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat1 */
{ USBB1_ULPITLL_DAT2 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat2 */
{ USBB1_ULPITLL_DAT3 , ( IEN | OFF_EN | OFF_PD | OFF_ IN | M4 ) } , /* usbb1_ulpiphy_dat3 */
{ USBB1_ULPITLL_CLK , ( IEN | OFF_EN | OFF_IN | M1 ) } , /* hsi1_cawake */
{ USBB1_ULPITLL_STP , ( IEN | OFF_EN | OFF_IN | M1 ) } , /* hsi1_cadata */
{ USBB1_ULPITLL_DIR , ( IEN | OFF_EN | OFF_IN | M1 ) } , /* hsi1_caflag */
{ USBB1_ULPITLL_NXT , ( OFF_EN | M1 ) } , /* hsi1_acready */
{ USBB1_ULPITLL_DAT0 , ( OFF_EN | M1 ) } , /* hsi1_acwake */
{ USBB1_ULPITLL_DAT1 , ( OFF_EN | M1 ) } , /* hsi1_acdata */
{ USBB1_ULPITLL_DAT2 , ( OFF_EN | M1 ) } , /* hsi1_acflag */
{ USBB1_ULPITLL_DAT3 , ( IEN | OFF_EN | OFF_IN | M1 ) } , /* hsi1_caready */
{ USBB1_ULPITLL_DAT4 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat4 */
{ USBB1_ULPITLL_DAT5 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat5 */
{ USBB1_ULPITLL_DAT6 , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4 ) } , /* usbb1_ulpiphy_dat6 */
@ -112,22 +100,12 @@ const struct pad_conf_entry core_padconf_array[] = {
{ USBB1_HSIC_STROBE , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* usbb1_hsic_strobe */
{ USBC1_ICUSB_DP , ( IEN | M0 ) } , /* usbc1_icusb_dp */
{ USBC1_ICUSB_DM , ( IEN | M0 ) } , /* usbc1_icusb_dm */
{ SDMMC1_CLK , ( PTU | OFF_EN | OFF_OUT_PTD | M0 ) } , /* sdmmc1_clk */
{ SDMMC1_CMD , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_cmd */
{ SDMMC1_DAT0 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat0 */
{ SDMMC1_DAT1 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat1 */
{ SDMMC1_DAT2 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat2 */
{ SDMMC1_DAT3 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat3 */
{ SDMMC1_DAT4 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat4 */
{ SDMMC1_DAT5 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat5 */
{ SDMMC1_DAT6 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat6 */
{ SDMMC1_DAT7 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc1_dat7 */
{ ABE_MCBSP2_CLKX , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* abe_mcbsp2_clkx */
{ ABE_MCBSP2_DR , ( IEN | OFF_EN | OFF_OUT_PTD | M0 ) } , /* abe_mcbsp2_dr */
{ ABE_MCBSP2_DX , ( OFF_EN | OFF_OUT_PTD | M0 ) } , /* abe_mcbsp2_dx */
{ ABE_MCBSP2_FSX , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* abe_mcbsp2_fsx */
{ ABE_MCBSP1_CLKX , ( IEN | M1 ) } , /* abe_sli mbu s1_cloc k */
{ ABE_MCBSP1_DR , ( IEN | M1 ) } , /* abe_slimbus1_data */
{ ABE_MCBSP1_CLKX , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* abe_mcbsp1_clkx */
{ ABE_MCBSP1_DR , ( IEN | OFF_EN | OFF_OUT_PTD | M0 ) } , /* abe_mcbsp1_dr */
{ ABE_MCBSP1_DX , ( OFF_EN | OFF_OUT_PTD | M0 ) } , /* abe_mcbsp1_dx */
{ ABE_MCBSP1_FSX , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* abe_mcbsp1_fsx */
{ ABE_PDM_UL_DATA , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* abe_pdm_ul_data */
@ -144,14 +122,6 @@ const struct pad_conf_entry core_padconf_array[] = {
{ UART2_RX , ( PTU | IEN | M0 ) } , /* uart2_rx */
{ UART2_TX , ( M0 ) } , /* uart2_tx */
{ HDQ_SIO , ( M3 ) } , /* gpio_127 */
{ I2C1_SCL , ( PTU | IEN | M0 ) } , /* i2c1_scl */
{ I2C1_SDA , ( PTU | IEN | M0 ) } , /* i2c1_sda */
{ I2C2_SCL , ( PTU | IEN | M0 ) } , /* i2c2_scl */
{ I2C2_SDA , ( PTU | IEN | M0 ) } , /* i2c2_sda */
{ I2C3_SCL , ( PTU | IEN | M0 ) } , /* i2c3_scl */
{ I2C3_SDA , ( PTU | IEN | M0 ) } , /* i2c3_sda */
{ I2C4_SCL , ( PTU | IEN | M0 ) } , /* i2c4_scl */
{ I2C4_SDA , ( PTU | IEN | M0 ) } , /* i2c4_sda */
{ MCSPI1_CLK , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* mcspi1_clk */
{ MCSPI1_SOMI , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* mcspi1_somi */
{ MCSPI1_SIMO , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* mcspi1_simo */
@ -159,10 +129,6 @@ const struct pad_conf_entry core_padconf_array[] = {
{ MCSPI1_CS1 , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3 ) } , /* mcspi1_cs1 */
{ MCSPI1_CS2 , ( PTU | OFF_EN | OFF_OUT_PTU | M3 ) } , /* gpio_139 */
{ MCSPI1_CS3 , ( PTU | IEN | M3 ) } , /* gpio_140 */
{ UART3_CTS_RCTX , ( PTU | IEN | M0 ) } , /* uart3_tx */
{ UART3_RTS_SD , ( M0 ) } , /* uart3_rts_sd */
{ UART3_RX_IRRX , ( IEN | M0 ) } , /* uart3_rx */
{ UART3_TX_IRTX , ( M0 ) } , /* uart3_tx */
{ SDMMC5_CLK , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0 ) } , /* sdmmc5_clk */
{ SDMMC5_CMD , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc5_cmd */
{ SDMMC5_DAT0 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* sdmmc5_dat0 */
@ -175,7 +141,7 @@ const struct pad_conf_entry core_padconf_array[] = {
{ MCSPI4_CS0 , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* mcspi4_cs0 */
{ UART4_RX , ( IEN | M0 ) } , /* uart4_rx */
{ UART4_TX , ( M0 ) } , /* uart4_tx */
{ USBB2_ULPITLL_CLK , ( IEN | M3 ) } , /* gpio_157 */
{ USBB2_ULPITLL_CLK , ( PTD | IEN | M3 ) } , /* gpio_157 */
{ USBB2_ULPITLL_STP , ( IEN | M5 ) } , /* dispc2_data23 */
{ USBB2_ULPITLL_DIR , ( IEN | M5 ) } , /* dispc2_data22 */
{ USBB2_ULPITLL_NXT , ( IEN | M5 ) } , /* dispc2_data21 */
@ -189,12 +155,12 @@ const struct pad_conf_entry core_padconf_array[] = {
{ USBB2_ULPITLL_DAT7 , ( IEN | M5 ) } , /* dispc2_data11 */
{ USBB2_HSIC_DATA , ( PTD | OFF_EN | OFF_OUT_PTU | M3 ) } , /* gpio_169 */
{ USBB2_HSIC_STROBE , ( PTD | OFF_EN | OFF_OUT_PTU | M3 ) } , /* gpio_170 */
{ UNIPRO_TX0 , ( PT D | IE N | M3 ) } , /* gpio_171 */
{ UNIPRO_TX0 , ( OFF_EN | OFF_ PD | OFF_ IN | M1 ) } , /* kpd_col0 */
{ UNIPRO_TY0 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col1 */
{ UNIPRO_TX1 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col2 */
{ UNIPRO_TY1 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col3 */
{ UNIPRO_TX2 , ( PTU | IEN | M3 ) } , /* gpio_0 */
{ UNIPRO_TY2 , ( PTU | IEN | M3 ) } , /* gpio_1 */
{ UNIPRO_TX2 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col4 */
{ UNIPRO_TY2 , ( OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_col5 */
{ UNIPRO_RX0 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_row0 */
{ UNIPRO_RY0 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_row1 */
{ UNIPRO_RX1 , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 ) } , /* kpd_row2 */
@ -205,13 +171,13 @@ const struct pad_conf_entry core_padconf_array[] = {
{ USBA0_OTG_DP , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* usba0_otg_dp */
{ USBA0_OTG_DM , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0 ) } , /* usba0_otg_dm */
{ FREF_CLK1_OUT , ( M0 ) } , /* fref_clk1_out */
{ FREF_CLK2_OUT , ( PTU | IEN | M3 ) } , /* gpio_182 */
{ FREF_CLK2_OUT , ( M0 ) } , /* fref_clk2_out */
{ SYS_NIRQ1 , ( PTU | IEN | M0 ) } , /* sys_nirq1 */
{ SYS_NIRQ2 , ( PTU | IEN | M0 ) } , /* sys_nirq2 */
{ SYS_NIRQ2 , ( M7 ) } , /* sys_nirq2 */
{ SYS_BOOT0 , ( PTU | IEN | M3 ) } , /* gpio_184 */
{ SYS_BOOT1 , ( M3 ) } , /* gpio_185 */
{ SYS_BOOT2 , ( PTD | IEN | M3 ) } , /* gpio_186 */
{ SYS_BOOT3 , ( M3 ) } , /* gpio_187 */
{ SYS_BOOT3 , ( PTD | IEN | M3 ) } , /* gpio_187 */
{ SYS_BOOT4 , ( M3 ) } , /* gpio_188 */
{ SYS_BOOT5 , ( PTD | IEN | M3 ) } , /* gpio_189 */
{ DPM_EMU0 , ( IEN | M0 ) } , /* dpm_emu0 */
@ -236,29 +202,29 @@ const struct pad_conf_entry core_padconf_array[] = {
{ DPM_EMU19 , ( IEN | M5 ) } , /* dispc2_data0 */
} ;
const struct pad_conf_entry wkup_padconf_array [ ] = {
{ PAD0_SIM_IO , ( IEN | M0 ) } , /* sim_io */
{ PAD1_SIM_CLK , ( M0 ) } , /* sim_clk */
{ PAD0_SIM_RESET , ( M0 ) } , /* sim_reset */
{ PAD1_SIM_CD , ( PTU | IEN | M0 ) } , /* sim_cd */
{ PAD0_SIM_PWRCTRL , ( M0 ) } , /* sim_pwrctrl */
{ PAD1_SR_SCL , ( PTU | IEN | M0 ) } , /* sr_scl */
{ PAD0_SR_SDA , ( PTU | IEN | M0 ) } , /* sr_sda */
{ PAD1_FREF_XTAL_IN , ( M0 ) } , /* # */
{ PAD0_FREF_SLICER_IN , ( M0 ) } , /* fref_slicer_in */
{ PAD1_FREF_CLK_IO REQ , ( M0 ) } , /* fref_clk_ioreq */
{ PAD0_FREF_CLK0_OUT , ( M2 ) } , /* sys_drm_msecure */
{ PAD1_FREF_CLK3_REQ , ( M3 ) } , /* gpio_wk30 */
{ PAD0_FREF_CLK3 _OUT , ( M0 ) } , /* fref_clk3_out */
{ PAD1_FREF_CLK4_REQ , ( PTU | OFF_EN | OFF_OUT_PTU | M3 ) } , /* led status_1 */
{ PAD0_FREF_CLK4_OUT , ( PTU | OFF_EN | OFF_OUT_PTU | M3 ) } , /* led status_2 */
{ PAD1_SYS_32K , ( IEN | M0 ) } , /* sys_32k */
{ PAD0_SYS_NRESPWRON , ( M0 ) } , /* sys_nrespwron */
{ PAD1_SYS_NRESWARM , ( M0 ) } , /* sys_nreswarm */
{ PAD0_SYS_PWR_REQ , ( PTU | M0 ) } , /* sys_pwr_req */
{ PAD1_SYS_PWRON_RESET , ( M3 ) } , /* gpio_wk29 */
{ PAD0_SYS_BOOT6 , ( IEN | M3 ) } , /* gpio_wk9 */
{ PAD1_SYS_BOOT7 , ( IEN | M3 ) } , /* gpio_wk10 */
const struct pad_conf_entry wkup_padconf_array_non_essential [ ] = {
{ PAD0_SIM_IO , ( IEN | M0 ) } , /* sim_io */
{ PAD1_SIM_CLK , ( M0 ) } , /* sim_clk */
{ PAD0_SIM_RESET , ( M0 ) } , /* sim_reset */
{ PAD1_SIM_CD , ( PTU | IEN | M0 ) } , /* sim_cd */
{ PAD0_SIM_PWRCTRL , ( M0 ) } , /* sim_pwrctrl */
{ PAD1_FREF_XTAL_IN , ( M0 ) } , /* # */
{ PAD0_FREF_SLICER_IN , ( M0 ) } , /* fref_slicer_in */
{ PAD1_FREF_CLK_IOREQ , ( M0 ) } , /* fref_clk_ioreq */
{ PAD0_FREF_CLK0_OUT , ( M2 ) } , /* sys_drm_msecure */
{ PAD1_FREF_CLK3 _REQ , ( PTU | IEN | M0 ) } , /* # */
{ PAD0_FREF_CLK3_OUT , ( M0 ) } , /* fref_clk3_out */
{ PAD1_FREF_CLK4_REQ , ( PTU | IEN | M0 ) } , /* # */
{ PAD0_FREF_CLK4 _OUT , ( M0 ) } , /* # */
{ PAD0_SYS_NRESPWRON , ( M0 ) } , /* sys_nrespwron */
{ PAD1_SYS_NRESWARM , ( M0 ) } , /* sys_nreswarm */
{ PAD0_SYS_PWR_REQ , ( PTU | M0 ) } , /* sys_pwr_req */
{ PAD1_SYS_PWRON_RESET , ( M3 ) } , /* gpio_wk29 */
{ PAD0_SYS_BOOT6 , ( IEN | M3 ) } , /* gpio_wk9 */
{ PAD1_SYS_BOOT7 , ( IEN | M3 ) } , /* gpio_wk10 */
{ PAD1_FREF_CLK3_REQ , ( M3 ) } , /* gpio_wk30 */
{ PAD1_FREF_CLK4_REQ , ( M3 ) } , /* gpio_wk7 */
{ PAD0_FREF_CLK4_OUT , ( M3 ) } , /* gpio_wk8 */
} ;
# endif
# endif /* _SDP4430_MUX_DATA_H */