driver: timer: Add the Atmel PIT timer driver

Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

arch/arm/mach-at91/arm926ejs/Makefile

@@ -22,7 +22,9 @@ obj-y += cache.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y	+= reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y	+= timer.o
+endif
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o

arch/arm/mach-at91/armv7/Makefile

@@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4)	+= sama5d4_devices.o
 obj-y += clock.o
 obj-y += cpu.o
 obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y += timer.o
+endif

drivers/timer/Kconfig

@@ -44,6 +44,14 @@ config ALTERA_TIMER
 	  Select this to enable a timer for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ATMEL_PIT_TIMER
+	bool "Atmel periodic interval timer support"
+	depends on TIMER
+	help
+	  Select this to enable a periodic interval timer for Atmel devices,
+	  it is designed to offer maximum accuracy and efficient management,
+	  even for systems with long response time.
+
 config SANDBOX_TIMER
 	bool "Sandbox timer support"
 	depends on SANDBOX && TIMER

drivers/timer/Makefile

@@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER)	+= arc_timer.o
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o

drivers/timer/atmel_pit_timer.c

@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * 		      Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define AT91_PIT_VALUE		0xfffff
+#define AT91_PIT_PITEN		BIT(24)		/* Timer Enabled */
+
+struct atmel_pit_regs {
+	u32	mode;
+	u32	status;
+	u32	value;
+	u32	value_image;
+};
+
+struct atmel_pit_platdata {
+	struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+	struct atmel_pit_regs *const regs = plat->regs;
+	u32 val = readl(&regs->value_image);
+
+	*count = timer_conv_64(val);
+
+	return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+	struct atmel_pit_regs *const regs = plat->regs;
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct clk clk;
+	ulong clk_rate;
+	int ret;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return -EINVAL;
+
+	clk_rate = clk_get_rate(&clk);
+	if (!clk_rate)
+		return -EINVAL;
+
+	uc_priv->clock_rate = clk_rate / 16;
+
+	writel(AT91_PIT_VALUE | AT91_PIT_PITEN, &regs->mode);
+
+	return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+	plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+	return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+	.get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+	.name	= "atmel_pit",
+	.id	= UCLASS_TIMER,
+	.of_match = atmel_pit_ids,
+	.ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+	.probe	= atmel_pit_probe,
+	.ops	= &atmel_pit_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};