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@ -26,6 +26,7 @@ |
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#if defined(CONFIG_440) |
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#include <ppc440.h> |
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#include <asm/cache.h> |
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#include <asm/io.h> |
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#include <asm/mmu.h> |
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@ -42,7 +43,6 @@ void remove_tlb(u32 vaddr, u32 size) |
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u32 tlb_vaddr; |
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u32 tlb_size = 0; |
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/* First, find the index of a TLB entry not being used */ |
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for (i=0; i<PPC4XX_TLB_SIZE; i++) { |
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tlb_word0_value = mftlb1(i); |
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tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value); |
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@ -96,6 +96,92 @@ void remove_tlb(u32 vaddr, u32 size) |
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asm("isync"); |
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} |
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/*
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* Change the I attribute (cache inhibited) of a TLB or multiple TLB's. |
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* This function is used to either turn cache on or off in a specific |
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* memory area. |
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*/ |
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void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) |
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{ |
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int i; |
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u32 tlb_word0_value; |
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u32 tlb_word2_value; |
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u32 tlb_vaddr; |
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u32 tlb_size = 0; |
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for (i=0; i<PPC4XX_TLB_SIZE; i++) { |
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tlb_word0_value = mftlb1(i); |
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tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value); |
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if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) && |
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(tlb_vaddr >= vaddr)) { |
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/*
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* TLB is enabled and start address is lower or equal |
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* than the area we are looking for. Now we only have |
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* to check the size/end address for a match. |
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*/ |
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switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) { |
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case TLB_WORD0_SIZE_1KB: |
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tlb_size = 1 << 10; |
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break; |
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case TLB_WORD0_SIZE_4KB: |
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tlb_size = 4 << 10; |
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break; |
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case TLB_WORD0_SIZE_16KB: |
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tlb_size = 16 << 10; |
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break; |
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case TLB_WORD0_SIZE_64KB: |
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tlb_size = 64 << 10; |
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break; |
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case TLB_WORD0_SIZE_256KB: |
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tlb_size = 256 << 10; |
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break; |
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case TLB_WORD0_SIZE_1MB: |
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tlb_size = 1 << 20; |
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break; |
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case TLB_WORD0_SIZE_16MB: |
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tlb_size = 16 << 20; |
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break; |
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case TLB_WORD0_SIZE_256MB: |
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tlb_size = 256 << 20; |
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break; |
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} |
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/*
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* Now check the end-address if it's in the range |
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*/ |
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if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) { |
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/*
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* Found a TLB in the range. |
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* Change cache attribute in tlb2 word. |
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*/ |
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tlb_word2_value = |
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TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | |
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TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | |
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TLB_WORD2_W_DISABLE | tlb_word2_i_value | |
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TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE | |
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TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE | |
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TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE | |
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TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE | |
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TLB_WORD2_SR_ENABLE; |
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/*
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* Now either flush or invalidate the dcache |
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*/ |
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if (tlb_word2_i_value) |
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flush_dcache(); |
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else |
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invalidate_dcache(); |
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mttlb3(i, tlb_word2_value); |
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asm("iccci 0,0"); |
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} |
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} |
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} |
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/* Execute an ISYNC instruction so that the new TLB entry takes effect */ |
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asm("isync"); |
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} |
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static int add_tlb_entry(unsigned long phys_addr, |
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unsigned long virt_addr, |
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unsigned long tlb_word0_size_value, |
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