xpedite5370: Enable multi-core support

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

board/xes/xpedite5370/tlb.c

@@ -61,32 +61,37 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, 2, BOOKE_PAGESZ_1M, 1),
 
+	/* **M** - Boot page for secondary processors */
+	SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+		0, 3, BOOKE_PAGESZ_4K, 1),
+
 #ifdef CONFIG_PCIE1
 	/* *I*G* - PCIe */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 3, BOOKE_PAGESZ_1G, 1),
+		0, 4, BOOKE_PAGESZ_1G, 1),
 #endif
 
 #ifdef CONFIG_PCIE2
 	/* *I*G* - PCIe */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 4, BOOKE_PAGESZ_256M, 1),
+		0, 5, BOOKE_PAGESZ_256M, 1),
 #endif
 
 #ifdef CONFIG_PCIE3
 	/* *I*G* - PCIe */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 5, BOOKE_PAGESZ_256M, 1),
+		0, 6, BOOKE_PAGESZ_256M, 1),
 #endif
 
 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
 	/* *I*G* - PCIe */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		0, 6, BOOKE_PAGESZ_64M, 1),
+		0, 7, BOOKE_PAGESZ_64M, 1),
 #endif
 
 };

include/configs/XPEDITE5370.h

@@ -49,6 +49,13 @@
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
  * DDR config
  */
 #define CONFIG_FSL_DDR2
@@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable