DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>master
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