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@ -36,12 +36,6 @@ |
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#define CQSPI_FIFO_WIDTH (4) |
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/* Controller sram size in word */ |
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#define CQSPI_REG_SRAM_SIZE_WORD (128) |
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#define CQSPI_REG_SRAM_RESV_WORDS (2) |
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#define CQSPI_REG_SRAM_PARTITION_WR (1) |
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#define CQSPI_REG_SRAM_PARTITION_RD \ |
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(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS) |
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#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) |
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/* Transfer mode */ |
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@ -206,18 +200,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, |
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unsigned int *dest_ptr = (unsigned int *)dest; |
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unsigned int *src_ptr = (unsigned int *)src_ahb_addr; |
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while (remaining > 0) { |
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if (remaining >= CQSPI_FIFO_WIDTH) { |
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*dest_ptr = readl(src_ptr); |
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remaining -= CQSPI_FIFO_WIDTH; |
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} else { |
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/* dangling bytes */ |
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temp = readl(src_ptr); |
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memcpy(dest_ptr, &temp, remaining); |
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break; |
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} |
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while (remaining >= sizeof(dest_ptr)) { |
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*dest_ptr = readl(src_ptr); |
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remaining -= sizeof(src_ptr); |
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dest_ptr++; |
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} |
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if (remaining) { |
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/* dangling bytes */ |
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temp = readl(src_ptr); |
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memcpy(dest_ptr, &temp, remaining); |
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} |
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return; |
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} |
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@ -225,24 +217,26 @@ static void cadence_qspi_apb_read_fifo_data(void *dest, |
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static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr, |
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const void *src, unsigned int bytes) |
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{ |
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unsigned int temp; |
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unsigned int temp = 0; |
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int i; |
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int remaining = bytes; |
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unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr; |
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unsigned int *src_ptr = (unsigned int *)src; |
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while (remaining > 0) { |
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if (remaining >= CQSPI_FIFO_WIDTH) { |
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writel(*src_ptr, dest_ptr); |
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remaining -= sizeof(unsigned int); |
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} else { |
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/* dangling bytes */ |
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memcpy(&temp, src_ptr, remaining); |
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writel(temp, dest_ptr); |
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break; |
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} |
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src_ptr++; |
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while (remaining >= CQSPI_FIFO_WIDTH) { |
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for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--) |
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writel(*(src_ptr+i), dest_ptr+i); |
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src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr); |
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remaining -= CQSPI_FIFO_WIDTH; |
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} |
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if (remaining) { |
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/* dangling bytes */ |
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i = remaining/sizeof(dest_ptr); |
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memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr)); |
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writel(temp, dest_ptr+i); |
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for (--i; i >= 0; i--) |
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writel(*(src_ptr+i), dest_ptr+i); |
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} |
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return; |
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} |
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@ -538,6 +532,9 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) |
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/* Configure the remap address register, no remap */ |
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writel(0, plat->regbase + CQSPI_REG_REMAP); |
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/* Indirect mode configurations */ |
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writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); |
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/* Disable all interrupts */ |
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writel(0, plat->regbase + CQSPI_REG_IRQMASK); |
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@ -700,10 +697,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, |
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writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), |
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plat->regbase + CQSPI_REG_INDIRECTTRIGGER); |
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/* Configure SRAM partition for read. */ |
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writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase + |
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CQSPI_REG_SRAMPARTITION); |
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/* Configure the opcode */ |
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rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; |
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@ -801,9 +794,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, |
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writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), |
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plat->regbase + CQSPI_REG_INDIRECTTRIGGER); |
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writel(CQSPI_REG_SRAM_PARTITION_WR, |
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plat->regbase + CQSPI_REG_SRAMPARTITION); |
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/* Configure the opcode */ |
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reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; |
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writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); |
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