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@ -1,5 +1,5 @@ |
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/*
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* (C) Copyright 2007 |
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* (C) Copyright 2007-2008 |
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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@ -24,8 +24,7 @@ |
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#ifndef __PMC440_H__ |
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#define __PMC440_H__ |
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/*-----------------------------------------------------------------------
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/*
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* GPIOs |
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*/ |
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#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ |
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@ -41,9 +40,10 @@ |
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#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ |
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#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ |
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#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ |
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#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */ |
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/* FPGA programming pin configuration */ |
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/*
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* FPGA programming pin configuration |
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*/ |
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#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ |
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#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ |
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#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ |
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@ -51,7 +51,7 @@ |
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#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ |
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#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ |
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/*-----------------------------------------------------------------------
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/*
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* FPGA interface |
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*/ |
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#define FPGA_BA CONFIG_SYS_FPGA_BASE0 |
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@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; |
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#define RESET_OUT (1 << 19) |
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#define IRIGB_R_OUT (1 << 14) |
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/* status register */ |
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#define STATUS_VERSION_SHIFT 24 |
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#define STATUS_VERSION_MASK 0xff000000 |
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@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; |
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#define STATUS_FIFO_ISF (1 << 9) |
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#define STATUS_HOST_ISF (1 << 8) |
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/* inputs */ |
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#define RESET_IN (1 << 0) |
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#define CLOCK_IN (1 << 1) |
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#define IRIGB_R_IN (1 << 5) |
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/* hostctrl register */ |
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#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) |
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#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) |
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@ -137,7 +134,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; |
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#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) |
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#define NGCC_CTRL_FPGARST_N (1 << 2) |
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/*-----------------------------------------------------------------------
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/*
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* FPGA to PPC interrupt |
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*/ |
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#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ |
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