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mpc8260: remove ep8260 board support

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This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Frank Panno <fpanno@delphintech.com>
master
Masahiro Yamada 10 years ago committed by Tom Rini
parent 793116d2c5
commit 4ad015bab0
11 changed files with 1 additions and 1604 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/mpc8260/Kconfig
  2. 9
      board/ep8260/Kconfig
  3. 6
      board/ep8260/MAINTAINERS
  4. 8
      board/ep8260/Makefile
  5. 304
      board/ep8260/ep8260.c
  6. 24
      board/ep8260/ep8260.h
  7. 395
      board/ep8260/flash.c
  8. 107
      board/ep8260/mii_phy.c
  9. 3
      configs/ep8260_defconfig
  10. 1
      doc/README.scrapyard
  11. 744
      include/configs/ep8260.h

4
arch/powerpc/cpu/mpc8260/Kconfig
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@ -16,9 +16,6 @@ config TARGET_CPU86
config TARGET_CPU87
bool "Support CPU87"
config TARGET_EP8260
bool "Support ep8260"
config TARGET_EP82XXM
bool "Support ep82xxm"
@ -51,7 +48,6 @@ endchoice
source "board/atc/Kconfig"
source "board/cpu86/Kconfig"
source "board/cpu87/Kconfig"
source "board/ep8260/Kconfig"
source "board/ep82xxm/Kconfig"
source "board/freescale/mpc8266ads/Kconfig"
source "board/funkwerk/vovpn-gw/Kconfig"

9
board/ep8260/Kconfig
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@ -1,9 +0,0 @@
if TARGET_EP8260
config SYS_BOARD
default "ep8260"
config SYS_CONFIG_NAME
default "ep8260"
endif

6
board/ep8260/MAINTAINERS
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@ -1,6 +0,0 @@
EP8260 BOARD
#M: Frank Panno <fpanno@delphintech.com>
S: Orphan (since 2014-06)
F: board/ep8260/
F: include/configs/ep8260.h
F: configs/ep8260_defconfig

8
board/ep8260/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = ep8260.o flash.o mii_phy.o

304
board/ep8260/ep8260.c
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@ -1,304 +0,0 @@
/*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "ep8260.h"
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/*
* Setup CS4 to enable the Board Control/Status registers.
* Otherwise the smcs won't work.
*/
int board_early_init_f (void)
{
volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
}
void reset_phy (void)
{
volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
regs->bcsr4 = 0xC0;
}
/*
* Check Board Identity:
* I don' know, how the next board revisions will be coded.
* Thats why its a static interpretation ...
*/
int checkboard (void)
{
volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
uint major = 0, minor = 0;
switch (regs->bcsr0) {
case 0x02:
major = 1;
break;
case 0x03:
major = 1;
minor = 1;
break;
case 0x06:
major = 1;
minor = 3;
break;
default:
break;
}
printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
major, minor);
return 0;
}
/* ------------------------------------------------------------------------- */
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0;
volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
/*
ulong psdmr = CONFIG_SYS_PSDMR;
#ifdef CONFIG_SYS_LSDRAM
ulong lsdmr = CONFIG_SYS_LSDMR;
#endif
*/
long size = CONFIG_SYS_SDRAM0_SIZE;
int i;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
#ifndef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_SYS_LSDRAM
size += CONFIG_SYS_SDRAM1_SIZE;
ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
memctl->memc_lsrt = CONFIG_SYS_LSRT;
memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
#endif /* CONFIG_SYS_LSDRAM */
#endif /* CONFIG_SYS_RAMBOOT */
return (size * 1024 * 1024);
}

24
board/ep8260/ep8260.h
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@ -1,24 +0,0 @@
#ifndef __EP8260_H__
#define __EP8260_H__
typedef struct tt_ep_regs {
volatile unsigned char bcsr0;
volatile unsigned char bcsr1;
volatile unsigned char bcsr2;
volatile unsigned char bcsr3;
volatile unsigned char bcsr4;
volatile unsigned char bcsr5;
volatile unsigned char bcsr6;
volatile unsigned char bcsr7;
volatile unsigned char bcsr8;
volatile unsigned char bcsr9;
volatile unsigned char bcsr10;
volatile unsigned char bcsr11;
volatile unsigned char bcsr12;
volatile unsigned char bcsr13;
volatile unsigned char bcsr14;
volatile unsigned char bcsr15;
} t_ep_regs;
typedef t_ep_regs *tp_ep_regs;
#endif

395
board/ep8260/flash.c
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@ -1,395 +0,0 @@
/*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* Flash Routines for AMD device AM29DL323DB on the EP8260 board.
*
* This file is based on board/tqm8260/flash.c.
*--------------------------------------------------------------------
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
void flash_reset(void)
{
if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
}
}
/*-----------------------------------------------------------------------
*/
ulong flash_get_size( ulong baseaddr, flash_info_t *info )
{
short i;
unsigned long flashtest_h, flashtest_l;
/* Write auto select command sequence and test FLASH answer */
V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
flashtest_h = V_ULONG(baseaddr); /* manufacturer ID */
flashtest_l = V_ULONG(baseaddr + 4);
if ((int)flashtest_h == AMD_MANUFACT) {
info->flash_id = FLASH_MAN_AMD;
} else {
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
flashtest_h = V_ULONG(baseaddr + 8); /* device ID */
flashtest_l = V_ULONG(baseaddr + 12);
if (flashtest_h != flashtest_l) {
info->flash_id = FLASH_UNKNOWN;
return(0);
}
switch((int)flashtest_h) {
case AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000; /* 4 * 4 MB = 16 MB */
break;
case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */
info->flash_id += FLASH_AMLV640U;
info->sector_count = 128;
info->size = 0x02000000; /* 4 * 8 MB = 32 MB */
break;
default:
info->flash_id = FLASH_UNKNOWN;
return(0); /* no or unknown flash */
}
if(flashtest_h == AMD_ID_LV640U) {
/* set up sector start adress table (uniform sector type) */
for (i = 0; i < info->sector_count; i++)
info->start[i] = baseaddr + (i * 0x00040000);
} else {
/* set up sector start adress table (bottom sector type) */
for (i = 0; i < 8; i++) {
info->start[i] = baseaddr + (i * 0x00008000);
}
for (i = 8; i < info->sector_count; i++) {
info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
(V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
info->protect[i] = 1; /* D0 = 1 if protected */
} else {
info->protect[i] = 0;
}
}
flash_reset();
return(info->size);
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 = 0;
int i;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here (only one bank) */
size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0>>20);
}
/*
* protect monitor and environment sectors
*/
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
# endif
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
&flash_info[0]);
#endif
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch ((info->flash_id >> 16) & 0xff) {
case FLASH_MAN_AMD: printf ("AMD "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMDL323B: printf ("29DL323B (32 M, bottom sector)\n");
break;
case FLASH_AMLV640U: printf ("29LV640U (64 M, uniform sector)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
udelay (1000);
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
V_ULONG( info->start[sect] ) = 0x00300030;
V_ULONG( info->start[sect] + 4 ) = 0x00300030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
(V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
{
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
flash_reset ();
printf (" done\n");
return 0;
}
static int write_dword (flash_info_t *, ulong, unsigned char *);
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong dp;
static unsigned char bb[8];
int i, l, rc, cc = cnt;
dp = (addr & ~7); /* get lower dword aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - dp) != 0) {
for (i = 0; i < 8; i++)
bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
if ((rc = write_dword(info, dp, bb)) != 0)
{
return (rc);
}
dp += 8;
cc -= 8 - l;
}
/*
* handle word aligned part
*/
while (cc >= 8) {
if ((rc = write_dword(info, dp, src)) != 0) {
return (rc);
}
dp += 8;
src += 8;
cc -= 8;
}
if (cc <= 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
for (i = 0; i < 8; i++) {
bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
}
return (write_dword(info, dp, bb));
}
/*-----------------------------------------------------------------------
* Write a dword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
{
ulong start;
ulong cl = 0, ch =0;
int flag, i;
for (ch=0, i=0; i < 4; i++)
ch = (ch << 8) + *pdata++; /* high word */
for (cl=0, i=0; i < 4; i++)
cl = (cl << 8) + *pdata++; /* low word */
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & ch) != ch
||(*((vu_long *)(dest + 4)) & cl) != cl)
{
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
V_ULONG( dest ) = ch;
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
V_ULONG( dest + 4 ) = cl;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}

107
board/ep8260/mii_phy.c
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@ -1,107 +0,0 @@
#include <common.h>
#include <mii_phy.h>
#include "ep8260.h"
#define MII_MDIO 0x01
#define MII_MDCK 0x02
#define MII_MDIR 0x04
void
mii_discover_phy(void)
{
int known;
unsigned short phy_reg;
unsigned long phy_id;
known = 0;
printf("Discovering phy @ 0: ");
phy_id = mii_phy_read(2) << 16;
phy_id |= mii_phy_read(3);
if ((phy_id & 0xFFFFFC00) == 0x00137800) {
printf("Level One ");
if ((phy_id & 0x000003F0) == 0xE0) {
printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
known = 1;
}
else printf("unknown type\n");
}
else printf("unknown OUI = 0x%08lX\n", phy_id);
phy_reg = mii_phy_read(1);
if (!(phy_reg & 0x0004)) printf("Link is down\n");
if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
if (phy_reg & 0x0002) printf("Jabber condition detected\n");
if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
if (known) {
phy_reg = mii_phy_read(17);
if (phy_reg & 0x0400)
printf("Phy operating at %d MBit/s in %s-duplex mode\n",
phy_reg & 0x4000 ? 100 : 10,
phy_reg & 0x0200 ? "full" : "half");
else
printf("bad link!!\n");
/*
left off: no link, green 100MBit, yellow 10MBit
right off: no activity, green full-duplex, yellow half-duplex
*/
mii_phy_write(20, 0x0452);
}
}
unsigned short
mii_phy_read(unsigned short reg)
{
int i;
unsigned short tmp, val = 0, adr = 0;
t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
tmp = 0x6002 | (adr << 7) | (reg << 2);
regs->bcsr4 = 0xC3;
for (i = 0; i < 64; i++) {
regs->bcsr4 ^= MII_MDCK;
}
for (i = 0; i < 16; i++) {
regs->bcsr4 &= ~MII_MDCK;
if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
else regs->bcsr4 &= ~MII_MDIO;
regs->bcsr4 |= MII_MDCK;
tmp <<= 1;
}
regs->bcsr4 |= MII_MDIR;
for (i = 0; i < 16; i++) {
val <<= 1;
regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
if (regs->bcsr4 & MII_MDIO) val |= 1;
regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
}
return val;
}
void
mii_phy_write(unsigned short reg, unsigned short val)
{
int i;
unsigned short tmp, adr = 0;
t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
tmp = 0x5002 | (adr << 7) | (reg << 2);
regs->bcsr4 = 0xC3;
for (i = 0; i < 64; i++) {
regs->bcsr4 ^= MII_MDCK;
}
for (i = 0; i < 16; i++) {
regs->bcsr4 &= ~MII_MDCK;
if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
else regs->bcsr4 &= ~MII_MDIO;
regs->bcsr4 |= MII_MDCK;
tmp <<= 1;
}
for (i = 0; i < 16; i++) {
regs->bcsr4 &= ~MII_MDCK;
if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
else regs->bcsr4 &= ~MII_MDIO;
regs->bcsr4 |= MII_MDCK;
val <<= 1;
}
}

3
configs/ep8260_defconfig
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CONFIG_PPC=y
CONFIG_MPC8260=y
CONFIG_TARGET_EP8260=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
ep8260 powerpc mpc8260 - - Frank Panno <fpanno@delphintech.com>
ppmc8260 powerpc mpc8260 - - Brad Kemp <Brad.Kemp@seranoa.com>
sacsng powerpc mpc8260 - - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
cogent_mpc8260 powerpc mpc8260 - - Murray Jensen <Murray.Jensen@csiro.au>

744
include/configs/ep8260.h
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/*
* (C) Copyright 2002
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* This file is based on similar values for other boards found in other
* U-Boot config files, and some that I found in the EP8260 manual.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*
* "EP8260 H, V.1.1"
* - 64M 60x Bus SDRAM
* - 32M Local Bus SDRAM
* - 16M Flash (4 x AM29DL323DB90WDI)
* - 128k NVRAM with RTC
*
* "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
* - 300MHz/133MHz/66MHz
* - 64M 60x Bus SDRAM
* - 32M Local Bus SDRAM
* - 32M Flash
* - 128k NVRAM with RTC
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Define this to enable support the EP8260 H2 version */
#define CONFIG_SYS_EP8260_H2 1
/* #undef CONFIG_SYS_EP8260_H2 */
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
#define CONFIG_CPM2 1 /* Has a CPM2 */
/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
/*-----------------------------------------------------------------------
* MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
*-----------------------------------------------------------------------
* What should MODCK_H be? It is dependent on the oscillator
* frequency, MODCK[1-3], and desired CPM and core frequencies.
* Here are some example values (all frequencies are in MHz):
*
* MODCK_H MODCK[1-3] Osc CPM Core
* ------- ---------- --- --- ----
* 0x2 0x2 33 133 133
* 0x2 0x3 33 133 166
* 0x2 0x4 33 133 200
* 0x2 0x5 33 133 233
* 0x2 0x6 33 133 266
*
* 0x5 0x5 66 133 133
* 0x5 0x6 66 133 166
* 0x5 0x7 66 133 200 *
* 0x6 0x0 66 133 233
* 0x6 0x1 66 133 266
* 0x6 0x2 66 133 300
*/
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
#else
#define CONFIG_SYS_SBC_MODCK_H (HRCW_MODCK_H0110)
#endif
/* Define this if you want to boot from 0x00000100. If you don't define
* this, you will need to program the bootloader to 0xfff00000, and
* get the hardware reset config words at 0xfe000000. The simplest
* way to do that is to program the bootloader at both addresses.
* It is suggested that you just let U-Boot live at 0x00000000.
*/
/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */ /* only for HRCW */
/* #undef CONFIG_SYS_SBC_BOOT_LOW */
/* The reset command will not work as expected if the reset address does
* not point to the correct address.
*/
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
/* What should the base address of the main FLASH be and how big is
* it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
* The main FLASH is whichever is connected to *CS0. U-Boot expects
* this to be the SIMM.
*/
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_FLASH0_BASE 0xFE000000
#define CONFIG_SYS_FLASH0_SIZE 32
#else
#define CONFIG_SYS_FLASH0_BASE 0xFF000000
#define CONFIG_SYS_FLASH0_SIZE 16
#endif
/* What should the base address of the secondary FLASH be and how big
* is it (in Mbytes)? The secondary FLASH is whichever is connected
* to *CS6. U-Boot expects this to be the on board FLASH. If you don't
* want it enabled, don't define these constants.
*/
#define CONFIG_SYS_FLASH1_BASE 0
#define CONFIG_SYS_FLASH1_SIZE 0
#undef CONFIG_SYS_FLASH1_BASE
#undef CONFIG_SYS_FLASH1_SIZE
/* What should be the base address of SDRAM DIMM (60x bus) and how big is
* it (in Mbytes)?
*/
#define CONFIG_SYS_SDRAM0_BASE 0x00000000
#define CONFIG_SYS_SDRAM0_SIZE 64
/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
* local bus (8260 local bus is NOT cacheable!)
*/
/* #define CONFIG_SYS_LSDRAM */
#undef CONFIG_SYS_LSDRAM
#ifdef CONFIG_SYS_LSDRAM
/* What should be the base address of SDRAM DIMM (local bus) and how big is
* it (in Mbytes)?
*/
#define CONFIG_SYS_SDRAM1_BASE 0x04000000
#define CONFIG_SYS_SDRAM1_SIZE 32
#else
#define CONFIG_SYS_SDRAM1_BASE 0
#define CONFIG_SYS_SDRAM1_SIZE 0
#undef CONFIG_SYS_SDRAM1_BASE
#undef CONFIG_SYS_SDRAM1_SIZE
#endif /* CONFIG_SYS_LSDRAM */
/* What should be the base address of NVRAM and how big is
* it (in Bytes)
*/
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000
#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16
/* The RTC is a Dallas DS1556
*/
#define CONFIG_RTC_DS1556
/* What should be the base address of the LEDs and switch S0?
* If you don't want them enabled, don't define this.
*/
#define CONFIG_SYS_LED_BASE 0x00000000
#undef CONFIG_SYS_LED_BASE
/*
* select serial console configuration
*
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*
* if CONFIG_CONS_NONE is defined, then the serial console routines must
* defined elsewhere.
*/
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
#undef CONFIG_CONS_NONE /* define if console on neither */
#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
/*
* select ethernet configuration
*
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
#if ( CONFIG_ETHER_INDEX == 3 )
/*
* - Rx-CLK is CLK15
* - Tx-CLK is CLK16
* - RAM for BD/Buffers is on the local Bus (see 28-13)
* - Enable Half Duplex in FSMR
*/
# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
/*
* - RAM for BD/Buffers is on the local Bus (see 28-13)
*/
#ifdef CONFIG_SYS_LSDRAM
#define CONFIG_SYS_CPMFCR_RAMTYPE 3
#else /* CONFIG_SYS_LSDRAM */
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
#endif /* CONFIG_SYS_LSDRAM */
/* - Enable Half Duplex in FSMR */
/* # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
# define CONFIG_SYS_FCC_PSMR 0
#else /* CONFIG_ETHER_INDEX */
# error "on EP8260 ethernet must be FCC3"
#endif /* CONFIG_ETHER_INDEX */
/*
* select i2c support configuration
*
* Supported configurations are {none, software, hardware} drivers.
* If the software driver is chosen, there are some additional
* configuration items that the driver uses to drive the port pins.
*/
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* This is for HARD, must go */
/*
* Software (bit-bang) I2C driver configuration
*/
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
else iop->pdat &= ~0x00010000
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
else iop->pdat &= ~0x00020000
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#endif /* CONFIG_SYS_I2C_SOFT */
/* #define CONFIG_RTC_DS174x */
/* Define this to reserve an entire FLASH sector (256 KB) for
* environment variables. Otherwise, the environment will be
* put in the same sector as U-Boot, and changing variables
* will erase U-Boot temporarily
*/
#define CONFIG_ENV_IN_OWN_SECT
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* What should the console's baud rate be? */
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_BAUDRATE 9600
#else
#define CONFIG_BAUDRATE 115200
#endif
/* Ethernet MAC address */
#define CONFIG_ETHADDR 00:10:EC:00:30:8C
#define CONFIG_IPADDR 192.168.254.130
#define CONFIG_SERVERIP 192.168.254.49
/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY -1
/* undef this to save memory */
#define CONFIG_SYS_LONGHELP
/* Monitor Command Prompt */
/* Define this variable to enable the "hush" shell (from
Busybox) as command line interpreter, thus enabling
powerful command line syntax like
if...then...else...fi conditionals or `&&' and '||'
constructs ("shell scripts").
If undefined, you get the old, much simpler behaviour
with a somewhat smapper memory footprint.
*/
#define CONFIG_SYS_HUSH_PARSER
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CDP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_PORTIO
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#undef CONFIG_CMD_XIMG
/* Where do the internal registers live? */
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
/* Where do the on board registers (CS4) live? */
#define CONFIG_SYS_REGS_BASE 0xFA000000
/*****************************************************************************
*
* You should not have to modify any of the following settings
*
*****************************************************************************/
#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/*
* Miscellaneous configurable options
*/
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#ifdef CONFIG_SYS_LSDRAM
#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
#else
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */
#endif /* CONFIG_SYS_LSDRAM */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
/*-----------------------------------------------------------------------
* Hard Reset Configuration Words
*/
#if defined(CONFIG_SYS_SBC_BOOT_LOW)
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
#else
# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0x00000000)
#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
#ifdef CONFIG_SYS_EP8260_H2
/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7) |\
((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM |\
HRCW_L2CPC01 |\
CONFIG_SYS_SBC_HRCW_IMMR |\
HRCW_APPC10 |\
HRCW_CS10PC01 |\
CONFIG_SYS_SBC_MODCK_H |\
CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
#else
#define CONFIG_SYS_HRCW_MASTER 0x10400245
#endif
/* no slaves */
#define CONFIG_SYS_HRCW_SLAVE1 0
#define CONFIG_SYS_HRCW_SLAVE2 0
#define CONFIG_SYS_HRCW_SLAVE3 0
#define CONFIG_SYS_HRCW_SLAVE4 0
#define CONFIG_SYS_HRCW_SLAVE5 0
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#else
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#endif
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#else
#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
#endif
#ifndef CONFIG_SYS_RAMBOOT
# define CONFIG_ENV_IS_IN_FLASH 1
# ifdef CONFIG_ENV_IN_OWN_SECT
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
# define CONFIG_ENV_SECT_SIZE 0x40000
# else
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
# endif /* CONFIG_ENV_IN_OWN_SECT */
#else
# define CONFIG_ENV_IS_IN_NVRAM 1
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
# define CONFIG_ENV_SIZE 0x200
#endif /* CONFIG_SYS_RAMBOOT */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* HIDx - Hardware Implementation-dependent Registers 2-11
*-----------------------------------------------------------------------
* HID0 also contains cache control - initially enable both caches and
* invalidate contents, then the final state leaves only the instruction
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
* but Soft reset does not.
*
* HID1 has only read-only information - nothing to set.
*/
#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
HID0_DCE |\
HID0_ICFI |\
HID0_DCI |\
HID0_IFEM |\
HID0_ABE)
#ifdef CONFIG_SYS_LSDRAM
/* 8260 local bus is NOT cacheable */
#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
HID0_IFEM |\
HID0_ABE |\
HID0_EMCP)
#else /* !CONFIG_SYS_LSDRAM */
#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
HID0_IFEM |\
HID0_ABE |\
HID0_EMCP)
#endif /* CONFIG_SYS_LSDRAM */
#define CONFIG_SYS_HID2 0
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RMR 0
/*-----------------------------------------------------------------------
* BCR - Bus Configuration 4-25
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_BCR (BCR_EBM |\
BCR_PLDP |\
BCR_EAV |\
BCR_NPQM0)
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 4-31
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
SIUMCR_APPC10 |\
SIUMCR_CS10PC01)
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
*/
#ifdef CONFIG_SYS_EP8260_H2
/* TBD: Find out why setting the BMT to 0xff causes the FCC to
* generate TX buffer underrun errors for large packets under
* Linux
*/
#define CONFIG_SYS_SYPCR_BMT 0x00000600
#else
#define CONFIG_SYS_SYPCR_BMT SYPCR_BMT
#endif
#ifdef CONFIG_SYS_LSDRAM
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
CONFIG_SYS_SYPCR_BMT |\
SYPCR_PBME |\
SYPCR_LBME |\
SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
CONFIG_SYS_SYPCR_BMT |\
SYPCR_PBME |\
SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
TMCNTSC_ALR |\
TMCNTSC_TCF |\
TMCNTSC_TCE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_PISCR (PISCR_PS |\
PISCR_PTF |\
PISCR_PTE)
#else
#define CONFIG_SYS_PISCR 0
#endif
/*-----------------------------------------------------------------------
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_SCCR (SCCR_DFBRG00)
#else
#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
#endif
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RCCR 0
/*-----------------------------------------------------------------------
* MPTPR - Memory Refresh Timer Prescale Register 10-32
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_MPTPR (0x0A00 & MPTPR_PTP_MSK)
/*
* Init Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
* 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
* 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
* 3 unused
* 4 60x GPCM 8 bit Board Regs, NVRTC
* 5 unused
* 6 unused
* 7 unused
* 8 PCMCIA
* 9 unused
* 10 unused
* 11 unused
*/
/*-----------------------------------------------------------------------
* BRx - Base Register
* Ref: Section 10.3.1 on page 10-14
* ORx - Option Register
* Ref: Section 10.3.2 on page 10-18
*-----------------------------------------------------------------------
*/
/* Bank 0 - FLASH
*
*/
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_DECC_NONE |\
BRx_MS_GPCM_P |\
BRx_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_8_CLK |\
ORxG_EHTR)
/* Bank 1 - SDRAM
* PSDRAM
*/
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI1_A6 |\
ORxS_NUMR_12)
#ifdef CONFIG_SYS_EP8260_H2
#define CONFIG_SYS_PSDMR 0xC34E246E
#else
#define CONFIG_SYS_PSDMR 0xC34E2462
#endif
#define CONFIG_SYS_PSRT 0x64
#ifdef CONFIG_SYS_LSDRAM
/* Bank 2 - SDRAM
* LSDRAM
*/
#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
BRx_PS_32 |\
BRx_MS_SDRAM_L |\
BRx_V)
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI0_A9 |\
ORxS_NUMR_12)
#define CONFIG_SYS_LSDMR 0x416A2562
#define CONFIG_SYS_LSRT 0x64
#else
#define CONFIG_SYS_LSRT 0x0
#endif /* CONFIG_SYS_LSDRAM */
/* Bank 4 - On board registers
* NVRTC and BCSR
*/
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
/*
#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SCY_10_CLK |\
ORxG_TRLX)
*/
#define CONFIG_SYS_OR4_PRELIM 0xfff00854
#ifdef _NOT_USED_SINCE_NOT_WORKING_
/* Bank 8 - On board registers
* PCMCIA (currently not working!)
*/
#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
BRx_PS_16 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CONFIG_SYS_OR8_PRELIM (ORxG_AM_MSK |\
ORxG_CSNT |\
ORxG_ACS_DIV1 |\
ORxG_SETA |\
ORxG_SCY_10_CLK)
#endif
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT ""
#define MTDPARTS_DEFAULT ""
*/
#endif /* __CONFIG_H */
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