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spi: Zap andes_spi driver

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Zap andes_spi driver since the boards used this driver
is no longer been active.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Macpaul Lin <macpaul@andestech.com>
master
Jagan Teki 9 years ago
parent 9c5a70dbe8
commit 4ad479e3d6
3 changed files with 0 additions and 400 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 1
      drivers/spi/Makefile
  2. 284
      drivers/spi/andes_spi.c
  3. 115
      drivers/spi/andes_spi.h

1
drivers/spi/Makefile
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@ -17,7 +17,6 @@ endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ANDES_SPI) += andes_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o

284
drivers/spi/andes_spi.c
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@ -1,284 +0,0 @@
/*
* Driver of Andes SPI Controller
*
* (C) Copyright 2011 Andes Technology
* Macpaul Lin <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/io.h>
#include "andes_spi.h"
void spi_init(void)
{
/* do nothing */
}
static void andes_spi_spit_en(struct andes_spi_slave *ds)
{
unsigned int dcr = readl(&ds->regs->dcr);
debug("%s: dcr: %x, write value: %x\n",
__func__, dcr, (dcr | ANDES_SPI_DCR_SPIT));
writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct andes_spi_slave *ds;
if (!spi_cs_is_valid(bus, cs))
return NULL;
ds = spi_alloc_slave(struct andes_spi_slave, bus, cs);
if (!ds)
return NULL;
ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
/*
* The hardware of andes_spi will set its frequency according
* to APB/AHB bus clock. Hence the hardware doesn't allow changing of
* requency and so the user requested speed is always ignored.
*/
ds->freq = max_hz;
return &ds->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct andes_spi_slave *ds = to_andes_spi(slave);
free(ds);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct andes_spi_slave *ds = to_andes_spi(slave);
unsigned int apb;
unsigned int baud;
/* Enable the SPI hardware */
writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
udelay(1000);
/* setup format */
baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF;
/*
* SPI_CLK = AHB bus clock / ((BAUD + 1)*2)
* BAUD = AHB bus clock / SPI_CLK / 2) - 1
*/
apb = (readl(&ds->regs->apb) & 0xffffff00) | baud;
writel(apb, &ds->regs->apb);
/* no interrupts */
writel(0, &ds->regs->ie);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
struct andes_spi_slave *ds = to_andes_spi(slave);
/* Disable the SPI hardware */
writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr);
}
static int andes_spi_read(struct spi_slave *slave, unsigned int len,
u8 *rxp, unsigned long flags)
{
struct andes_spi_slave *ds = to_andes_spi(slave);
unsigned int i, left;
unsigned int data;
debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n",
__func__, slave, len, rxp, flags);
debug("%s: data: ", __func__);
while (len > 0) {
left = min(len, 4);
data = readl(&ds->regs->data);
debug(" ");
for (i = 0; i < left; i++) {
debug("%02x ", data & 0xff);
*rxp++ = data;
data >>= 8;
len--;
}
}
debug("\n");
return 0;
}
static int andes_spi_write(struct spi_slave *slave, unsigned int wlen,
unsigned int rlen, const u8 *txp, unsigned long flags)
{
struct andes_spi_slave *ds = to_andes_spi(slave);
unsigned int data;
unsigned int i, left;
unsigned int spit_enabled = 0;
debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n",
__func__, slave, wlen, rlen, txp, flags);
/* The value of wlen and rlen wrote to register must minus 1 */
if (rlen == 0) /* write only */
writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) |
ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr);
else /* write then read */
writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) |
ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr);
/* wait till SPIBSY is cleared */
while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY)
;
/* data write process */
debug("%s: txp: ", __func__);
while (wlen > 0) {
/* clear the data */
data = 0;
/* data are usually be read 32bits once a time */
left = min(wlen, 4);
for (i = 0; i < left; i++) {
debug("%x ", *txp);
data |= *txp++ << (i * 8);
wlen--;
}
debug("\n");
debug("data: %08x\n", data);
debug("streg before write: %08x\n", readl(&ds->regs->st));
/* wait till TXFULL is deasserted */
while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL)
;
writel(data, &ds->regs->data);
debug("streg after write: %08x\n", readl(&ds->regs->st));
if (spit_enabled == 0) {
/* enable SPIT bit - trigger the tx and rx progress */
andes_spi_spit_en(ds);
spit_enabled = 1;
}
}
debug("\n");
return 0;
}
/*
* spi_xfer:
* Since andes_spi doesn't support independent command transaction,
* that is, write and than read must be operated in continuous
* execution, there is no need to set dcr and trigger spit again in
* RX process.
*/
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
unsigned int len;
static int op_nextime;
static u8 tmp_cmd[5];
static int tmp_wlen;
unsigned int i;
if (bitlen == 0)
/* Finish any previously submitted transfers */
goto out;
if (bitlen % 8) {
/* Errors always terminate an ongoing transfer */
flags |= SPI_XFER_END;
goto out;
}
len = bitlen / 8;
debug("%s: slave: %08x, bitlen: %d, dout: "
"%08x, din: %08x, flags: %d, len: %d\n",
__func__, slave, bitlen, dout, din, flags, len);
/*
* Important:
* andes_spi's hardware doesn't support 2 data channel. The read
* and write cmd/data share the same register (data register).
*
* If a command has write and read transaction, you cannot do write
* this time and then do read on next time.
*
* A command writes first with a read response must indicating
* the read length in write operation. Hence the write action must
* be stored temporary and wait until the next read action has been
* arrived. Then we flush the write and read action out together.
*/
if (!dout) {
if (op_nextime == 1) {
/* flags should be SPI_XFER_END, value is 2 */
op_nextime = 0;
andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags);
}
return andes_spi_read(slave, len, din, flags);
} else if (!din) {
if (flags == SPI_XFER_BEGIN) {
/* store the write command and do operation next time */
op_nextime = 1;
memset(tmp_cmd, 0, sizeof(tmp_cmd));
memcpy(tmp_cmd, dout, len);
debug("%s: tmp_cmd: ", __func__);
for (i = 0; i < len; i++)
debug("%x ", *(tmp_cmd + i));
debug("\n");
tmp_wlen = len;
} else {
/*
* flags should be (SPI_XFER_BEGIN | SPI_XFER_END),
* the value is 3.
*/
if (op_nextime == 1) {
/* flags should be SPI_XFER_END, value is 2 */
op_nextime = 0;
/* flags 3 implies write only */
andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3);
}
debug("flags: %x\n", flags);
return andes_spi_write(slave, len, 0, dout, flags);
}
}
out:
return 0;
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
/* do nothing */
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* do nothing */
}

115
drivers/spi/andes_spi.h
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@ -1,115 +0,0 @@
/*
* Register definitions for the Andes SPI Controller
*
* (C) Copyright 2011 Andes Technology
* Macpaul Lin <macpaul@andestech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ANDES_SPI_H
#define __ANDES_SPI_H
struct andes_spi_regs {
unsigned int apb; /* 0x00 - APB SPI interface setting */
unsigned int pio; /* 0x04 - PIO reg */
unsigned int cr; /* 0x08 - SPI Control reg */
unsigned int st; /* 0x0c - SPI Status reg */
unsigned int ie; /* 0x10 - Interrupt Enable reg */
unsigned int ist; /* 0x14 - Interrupt Status reg */
unsigned int dcr; /* 0x18 - data control reg */
unsigned int data; /* 0x1c - data register */
unsigned int ahb; /* 0x20 - AHB SPI interface setting */
unsigned int ver; /* 0x3c - SPI version reg */
};
#define BIT(x) (1 << (x))
/* 0x00 - APB SPI interface setting register */
#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0)
#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16)
#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */
#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */
#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */
/* 0x04 - PIO register */
#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */
#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */
#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */
#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */
#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */
/* 0x08 - SPI Control register */
#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */
#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */
#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */
#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */
#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */
/* 0x0c - SPI Status register */
#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */
#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */
#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */
#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f)
#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */
#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */
#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f)
/* 0x10 - Interrupt Enable register */
#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */
#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */
#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */
#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */
#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */
#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */
/* 0x14 - Interrupt Status Register */
#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */
#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */
#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */
#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */
#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */
#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */
/* 0x18 - Data Control Register */
#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0)
#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12)
#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16)
#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28)
#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */
#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */
#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */
#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */
#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */
#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */
#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */
#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */
#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */
/* 0x20 - AHB SPI interface setting register */
#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0)
#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16)
#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */
#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */
#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */
#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */
/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */
#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf)
#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf)
#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf)
struct andes_spi_slave {
struct spi_slave slave;
struct andes_spi_regs *regs;
unsigned int freq;
};
static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave)
{
return container_of(slave, struct andes_spi_slave, slave);
}
#endif /* __ANDES_SPI_H */
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