ppc4xx: Add AMCC Glacier 406GT eval board support

This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
17 years ago · 4c9e855734
parent d8bd643141
commit 4c9e855734
8 changed files with 195 additions and 25 deletions
--- a/1
+++ b/1
@ -322,6 +322,7 @@ Stefan Roese <sr@denx.de>
 	bunbinga		PPC405EP
 	canyonlands		PPC460EX
 	ebony			PPC440GP
+	glacier			PPC460GT
 	haleakala		PPC405EXr
 	katmai			PPC440SPe
 	kilauea			PPC405EX
--- a/1
+++ b/1
@ -185,6 +185,7 @@ LIST_4xx="		\
 	ERIC		\
 	EXBITGEN	\
 	G2000		\
+	glacier		\
 	haleakala	\
 	haleakala_nand	\
 	hcu4		\
--- a/9
+++ b/9
@ -1172,8 +1172,13 @@ bubinga_config:	unconfig
 CANBT_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd

-canyonlands_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc
+# Canyonlands & Glacier use different U-Boot images
+canyonlands_config \
+glacier_config:	unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc

 canyonlands_nand_config:	unconfig
 	@mkdir -p $(obj)include $(obj)board/amcc/canyonlands
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	u32 sdr0_cust0;
+	u32 pvr = get_pvr();

 	/*------------------------------------------------------------------+
 	 * Setup the interrupt controller polarities, triggers, etc.
@ -105,14 +106,16 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);

-	/*
-	 * Configure USB-STP pins as alternate and not GPIO
-	 * It seems to be neccessary to configure the STP pins as GPIO
-	 * input at powerup (perhaps while USB reset is asserted). So
-	 * we configure those pins to their "real" function now.
-	 */
-	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
+		/*
+		 * Configure USB-STP pins as alternate and not GPIO
+		 * It seems to be neccessary to configure the STP pins as GPIO
+		 * input at powerup (perhaps while USB reset is asserted). So
+		 * we configure those pins to their "real" function now.
+		 */
+		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	}

 	return 0;
 }
@ -369,6 +372,7 @@ int misc_init_r(void)
 {
 	u32 sdr0_srst1 = 0;
 	u32 eth_cfg;
+	u32 pvr = get_pvr();

 	/*
 	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
@ -382,7 +386,10 @@ int misc_init_r(void)
 	/* Set the for 2 RGMII mode */
 	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
+		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+	else
+		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 	mtsdr(SDR0_ETH_CFG, eth_cfg);

 	/*
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@ -275,6 +275,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 	uint32_t failsafe = 10000;
+	u32 eth_cfg = 0;

 	out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000);	/* disable emac interrupts */

@ -308,6 +309,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	hw_p->print_speed = 1;	/* print speed message again next time */
 #endif

+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
+	mfsdr(SDR0_ETH_CFG, eth_cfg);
+	eth_cfg &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+	mtsdr(SDR0_ETH_CFG, eth_cfg);
+#endif
+
 	return;
 }

@ -494,11 +502,18 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	u32 zmiifer;		/* ZMII0_FER reg. */
 	u32 rmiifer;		/* RGMII0_FER reg. Bridge 0 */
 	u32 rmiifer1;		/* RGMII0_FER reg. Bridge 1 */
+	int mode;

 	zmiifer  = 0;
 	rmiifer  = 0;
 	rmiifer1 = 0;

+#if defined(CONFIG_460EX)
+	mode = 9;
+#else
+	mode = 10;
+#endif
+
 	/* TODO:
 	 * NOTE: 460GT has 2 RGMII bridge cores:
 	 *		emac0 ------ RGMII0_BASE
@ -520,7 +535,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	 * Right now only 2*RGMII is supported. Please extend when needed.
 	 * sr - 2008-02-19
 	 */
-	switch (9) {
+	switch (mode) {
 	case 1:
 		/* 1 MII - 460EX */
 		/* GMC0 EMAC4_0, ZMII Bridge */
@ -836,10 +851,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		reg = CONFIG_PHY1_ADDR;
 		break;
 #endif
-#if defined (CONFIG_440GX)
+#if defined (CONFIG_PHY2_ADDR)
 	case 2:
 		reg = CONFIG_PHY2_ADDR;
 		break;
+#endif
+#if defined (CONFIG_PHY3_ADDR)
 	case 3:
 		reg = CONFIG_PHY3_ADDR;
 		break;
@ -1131,7 +1148,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif

 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-		mtdcr (malrxctp8r, hw_p->rx);
+		mtdcr (malrxctp8r, hw_p->rx_phys);
 		/* set RX buffer size */
 		mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
 #else
@ -1160,6 +1177,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
 		break;
 #endif /* CONFIG_440GX */
+#if defined (CONFIG_460GT)
+	case 2:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp2r, hw_p->tx_phys);
+		mtdcr (malrxctp16r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+	case 3:
+		/* setup MAL tx & rx channel pointers */
+		mtdcr (maltxbattr, 0x0);
+		mtdcr (malrxbattr, 0x0);
+		mtdcr (maltxctp3r, hw_p->tx_phys);
+		mtdcr (malrxctp24r, hw_p->rx_phys);
+		/* set RX buffer size */
+		mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16);
+		break;
+#endif /* CONFIG_460GT */
 	case 0:
 	default:
 		/* setup MAL tx & rx channel pointers */
@ -1866,14 +1903,22 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 		case 2:
 			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
 			       bis->bi_enet2addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x300;
+#else
 			hw_addr[eth_num] = 0x400;
+#endif
 			break;
 #endif
 #ifdef CONFIG_HAS_ETH3
 		case 3:
 			memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
 			       bis->bi_enet3addr, 6);
+#if defined(CONFIG_460GT)
+			hw_addr[eth_num] = 0x400;
+#else
 			hw_addr[eth_num] = 0x600;
+#endif
 			break;
 #endif
 		}
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@ -27,10 +27,14 @@
 /*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
-#define CONFIG_CANYONLANDS	1	/* Board is Canyonlands	*/
+/* This config file is used for Canyonlands (460EX) and Glacier (460GT)	*/
+#ifndef CONFIG_CANYONLANDS
+#define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#else
+#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
-#define CONFIG_460EX		1	/* Specific PPC460EX support */

 #define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/

@ -262,8 +266,15 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
 #define CONFIG_PHY1_ADDR	1
-#define CONFIG_HAS_ETH0		1
-#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+/* Only Glacier (460GT) has 4 EMAC interfaces */
+#ifdef CONFIG_460GT
+#define CONFIG_PHY2_ADDR	2
+#define CONFIG_PHY3_ADDR	3
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
 #define CONFIG_NET_MULTI	1

 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
@ -275,6 +286,8 @@
 /*-----------------------------------------------------------------------
 * USB-OHCI
 *----------------------------------------------------------------------*/
+/* Only Canyonlands (460EX) has USB */
+#ifdef CONFIG_460EX
 #define CONFIG_USB_OHCI_NEW
 #define CONFIG_USB_STORAGE
 #undef CFG_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
@ -283,6 +296,7 @@
 #define CFG_USB_OHCI_REGS_BASE	(CFG_AHB_BASE | 0xd0000)
 #define CFG_USB_OHCI_SLOT_NAME	"ppc440"
 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#endif

 /*-----------------------------------------------------------------------
 * Default environment
@ -293,9 +307,21 @@

 #undef	CONFIG_BOOTARGS

+/* Setup some board specific values for the default environment variables */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_HOSTNAME		canyonlands
+#define CFG_BOOTFILE		"bootfile=canyonlands/uImage\0"
+#define CFG_DTBFILE		"fdt_file=canyonlands/canyonlands.dtb\0"
+#else
+#define CONFIG_HOSTNAME		glacier
+#define CFG_BOOTFILE		"bootfile=glacier/uImage\0"
+#define CFG_DTBFILE		"fdt_file=glacier/glacier.dtb\0"
+#endif
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CFG_BOOTFILE							\
+	CFG_DTBFILE							\
 	"netdev=eth0\0"							\
-	"hostname=canyonlands\0"					\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
@ -315,18 +341,16 @@
 	"flash_self=run ramargs addip addtty;"				\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
 	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
-	"bootfile=canyonlands/uImage\0"					\
-	"fdt_file=canyonlands/canyonlands.dtb\0"			\
 	"fdt_addr=400000\0"						\
 	"kernel_addr=fc000000\0"					\
 	"ramdisk_addr=fc200000\0"					\
 	"initrd_high=30000000\0"					\
-	"load=tftp 200000 canyonlands/u-boot.bin\0"			\
+	"load=tftp 200000 ${hostname}/u-boot.bin\0"			\
 	"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"	\
 		"cp.b ${fileaddr} fffa0000 ${filesize};"		\
 		"setenv filesize;saveenv\0"				\
 	"upd=run load update\0"						\
-	"nload=tftp 200000 canyonlands/u-boot-nand.bin\0"		\
+	"nload=tftp 200000 ${hostname}/u-boot-nand.bin\0"		\
 	"nupdate=nand erase 0 60000;nand write 200000 0 60000;"		\
 		"setenv filesize;saveenv\0"				\
 	"nupd=run nload nupdate\0"					\
@ -361,8 +385,6 @@
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
@ -373,7 +395,11 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
+#ifdef CONFIG_460EX
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
 #define CONFIG_CMD_USB
+#endif

 /* Partitions */
 #define CONFIG_MAC_PARTITION
@ -487,6 +513,8 @@
 /*
 * PPC4xx GPIO Configuration
 */
+#ifdef CONFIG_460EX
+/* 460EX: Use USB configuration */
 #define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
 {											\
 /* GPIO Core 0 */									\
@ -559,6 +587,81 @@
 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
 }											\
 }
+#else
+/* 460GT: Use EMAC2+3 configuration */
+#define CFG_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+#endif

 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
--- a/include/ppc440.h
+++ b/include/ppc440.h
@ -2023,9 +2023,13 @@
 #define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg   */
 #define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg   */
 #define malrxctp8r  (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg   */
+#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg  */
+#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg  */
 #define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
 #define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
 #define malrcbs8    (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg	    */
+#define malrcbs16   (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg    */
+#define malrcbs24   (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg    */
 #endif /* CONFIG_440GX */


--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)

+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET	0x100
+#endif
+
 /* RGMII Function Enable (FER) Register Bit Definitions */
 /* Note: for EMAC 2 and 3 only, 440GX only */
 #define RGMII_FER_DIS		(0x00)