Wolfgang Denk
17 years ago
commit
4cc64742a8
@ -1,230 +0,0 @@ |
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/* flush.S - low level cache flushing routines |
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* Copyright (C) 2003-2007 Analog Devices Inc. |
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* Licensed under the GPL-2 or later. |
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*/ |
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|
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#include <config.h> |
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#include <asm/blackfin.h> |
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#include <asm/cplb.h> |
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#include <asm/mach-common/bits/mpu.h> |
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.text |
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/* This is an external function being called by the user |
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* application through __flush_cache_all. Currently this function |
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* serves the purpose of flushing all the pending writes in |
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* in the data cache. |
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*/ |
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ENTRY(_flush_data_cache) |
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[--SP] = ( R7:6, P5:4 );
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LINK 12;
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SP += -12;
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P5.H = HI(DCPLB_ADDR0);
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P5.L = LO(DCPLB_ADDR0);
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P4.H = HI(DCPLB_DATA0);
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P4.L = LO(DCPLB_DATA0);
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R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
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R6 = 16;
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.Lnext: R0 = [P5++];
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R1 = [P4++];
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CC = BITTST(R1, 14); /* Is it write-through?*/
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IF CC JUMP .Lskip; /* If so, ignore it.*/
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R2 = R1 & R7; /* Is it a dirty, cached page?*/
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CC = R2;
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IF !CC JUMP .Lskip; /* If not, ignore it.*/
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[--SP] = RETS;
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CALL _dcplb_flush; /* R0 = page, R1 = data*/
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RETS = [SP++];
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.Lskip: R6 += -1;
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CC = R6;
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IF CC JUMP .Lnext;
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SSYNC;
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SP += 12;
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UNLINK;
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( R7:6, P5:4 ) = [SP++];
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RTS;
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ENDPROC(_flush_data_cache) |
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/* This is an internal function to flush all pending |
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* writes in the cache associated with a particular DCPLB. |
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* |
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* R0 - page's start address |
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* R1 - CPLB's data field. |
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*/ |
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.align 2
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ENTRY(_dcplb_flush) |
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[--SP] = ( R7:0, P5:0 );
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[--SP] = LC0;
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[--SP] = LT0;
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[--SP] = LB0;
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[--SP] = LC1;
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[--SP] = LT1;
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[--SP] = LB1;
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/* If it's a 1K or 4K page, then it's quickest to |
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* just systematically flush all the addresses in |
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* the page, regardless of whether they're in the |
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* cache, or dirty. If it's a 1M or 4M page, there |
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* are too many addresses, and we have to search the |
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* cache for lines corresponding to the page. |
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*/ |
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CC = BITTST(R1, 17); /* 1MB or 4MB */
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IF !CC JUMP .Ldflush_whole_page;
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/* We're only interested in the page's size, so extract |
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* this from the CPLB (bits 17:16), and scale to give an |
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* offset into the page_size and page_prefix tables. |
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*/ |
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R1 <<= 14;
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R1 >>= 30;
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R1 <<= 2;
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/* The page could be mapped into Bank A or Bank B, depending |
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* on (a) whether both banks are configured as cache, and |
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* (b) on whether address bit A[x] is set. x is determined |
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* by DCBS in DMEM_CONTROL |
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*/ |
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R2 = 0; /* Default to Bank A (Bank B would be 1)*/
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P0.L = LO(DMEM_CONTROL);
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P0.H = HI(DMEM_CONTROL);
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R3 = [P0]; /* If Bank B is not enabled as cache*/
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CC = BITTST(R3, 2); /* then Bank A is our only option.*/
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IF CC JUMP .Lbank_chosen;
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R4 = 1<<14; /* If DCBS==0, use A[14].*/
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R5 = R4 << 7; /* If DCBS==1, use A[23];*/
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CC = BITTST(R3, 4);
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IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
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R5 = R0 & R4; /* Use it to test the Page address*/
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CC = R5; /* and if that bit is set, we use Bank B,*/
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R2 = CC; /* else we use Bank A.*/
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R2 <<= 23; /* The Bank selection's at posn 23.*/
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.Lbank_chosen: |
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/* We can also determine the sub-bank used, because this is |
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* taken from bits 13:12 of the address. |
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*/ |
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R3 = ((12<<8)|2); /* Extraction pattern */
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nop; /*Anamoly 05000209*/
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R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
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/* Save in extraction pattern for later deposit.*/ |
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R3.H = R4.L << 0;
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/* So: |
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* R0 = Page start |
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* R1 = Page length (actually, offset into size/prefix tables) |
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* R2 = Bank select mask |
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* R3 = sub-bank deposit values |
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* |
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* The cache has 2 Ways, and 64 sets, so we iterate through |
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* the sets, accessing the tag for each Way, for our Bank and |
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* sub-bank, looking for dirty, valid tags that match our |
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* address prefix. |
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*/ |
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P5.L = LO(DTEST_COMMAND);
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P5.H = HI(DTEST_COMMAND);
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P4.L = LO(DTEST_DATA0);
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P4.H = HI(DTEST_DATA0);
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P0.L = page_prefix_table;
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P0.H = page_prefix_table;
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P1 = R1;
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R5 = 0; /* Set counter*/
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P0 = P1 + P0;
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R4 = [P0]; /* This is the address prefix*/
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/* We're reading (bit 1==0) the tag (bit 2==0), and we |
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* don't care about which double-word, since we're only |
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* fetching tags, so we only have to set Set, Bank, |
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* Sub-bank and Way. |
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*/ |
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P2 = 2;
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LSETUP (.Lfs1, .Lfe1) LC1 = P2;
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.Lfs1: P0 = 64; /* iterate over all sets*/
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LSETUP (.Lfs0, .Lfe0) LC0 = P0;
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.Lfs0: R6 = R5 << 5; /* Combine set*/
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R6.H = R3.H << 0 ; /* and sub-bank*/
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R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
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BITSET(R6,14);
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[P5] = R6; /* Issue Command*/
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SSYNC;
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R7 = [P4]; /* and read Tag.*/
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CC = BITTST(R7, 0); /* Check if valid*/
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IF !CC JUMP .Lfskip; /* and skip if not.*/
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CC = BITTST(R7, 1); /* Check if dirty*/
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IF !CC JUMP .Lfskip; /* and skip if not.*/
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/* Compare against the page address. First, plant bits 13:12 |
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* into the tag, since those aren't part of the returned data. |
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*/ |
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R7 = DEPOSIT(R7, R3); /* set 13:12*/
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R1 = R7 & R4; /* Mask off lower bits*/
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CC = R1 == R0; /* Compare against page start.*/
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IF !CC JUMP .Lfskip; /* Skip it if it doesn't match.*/
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/* Tag address matches against page, so this is an entry |
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* we must flush. |
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*/ |
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R7 >>= 10; /* Mask off the non-address bits*/
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R7 <<= 10;
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P3 = R7;
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SSYNC;
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FLUSHINV [P3]; /* And flush the entry*/
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.Lfskip: |
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.Lfe0: R5 += 1; /* Advance to next Set*/
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.Lfe1: BITSET(R2, 26); /* Go to next Way.*/
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.Ldfinished: |
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SSYNC; /* Ensure the data gets out to mem.*/
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/*Finished. Restore context.*/ |
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LB1 = [SP++];
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LT1 = [SP++];
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LC1 = [SP++];
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LB0 = [SP++];
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LT0 = [SP++];
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LC0 = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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.Ldflush_whole_page: |
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/* It's a 1K or 4K page, so quicker to just flush the |
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* entire page. |
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*/ |
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P1 = 32; /* For 1K pages*/
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P2 = P1 << 2; /* For 4K pages*/
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P0 = R0; /* Start of page*/
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CC = BITTST(R1, 16); /* Whether 1K or 4K*/
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IF CC P1 = P2;
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P1 += -1; /* Unroll one iteration*/
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SSYNC;
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FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
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LSETUP (.Leall, .Leall) LC0 = P1;
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.Leall: FLUSHINV [P0++];
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SSYNC;
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JUMP .Ldfinished;
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ENDPROC(_dcplb_flush) |
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.align 4;
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page_prefix_table: |
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.byte4 0xFFFFFC00; /* 1K */
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.byte4 0xFFFFF000; /* 4K */
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.byte4 0xFFF00000; /* 1M */
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.byte4 0xFFC00000; /* 4M */
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.page_prefix_table.end: |
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@ -1,321 +0,0 @@ |
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/*
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* U-boot - mem_init.h Header file for memory initialization |
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* |
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* Copyright (c) 2005-2007 Analog Devices Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ |
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CONFIG_MEM_MT48LC64M4A2FB_7E || \
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CONFIG_MEM_MT48LC16M8A2TG_75 || \
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CONFIG_MEM_MT48LC8M16A2TG_7E || \
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CONFIG_MEM_MT48LC8M32B2B5_7 || \
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CONFIG_MEM_MT48LC32M8A2_75) |
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#if ( CONFIG_SCLK_HZ > 119402985 ) |
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#define SDRAM_tRP TRP_2 |
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#define SDRAM_tRP_num 2 |
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#define SDRAM_tRAS TRAS_7 |
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#define SDRAM_tRAS_num 7 |
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#define SDRAM_tRCD TRCD_2 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 ) |
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#define SDRAM_tRP TRP_2 |
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#define SDRAM_tRP_num 2 |
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#define SDRAM_tRAS TRAS_6 |
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#define SDRAM_tRAS_num 6 |
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#define SDRAM_tRCD TRCD_2 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 ) |
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#define SDRAM_tRP TRP_2 |
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#define SDRAM_tRP_num 2 |
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#define SDRAM_tRAS TRAS_5 |
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#define SDRAM_tRAS_num 5 |
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#define SDRAM_tRCD TRCD_2 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 ) |
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#define SDRAM_tRP TRP_2 |
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#define SDRAM_tRP_num 2 |
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#define SDRAM_tRAS TRAS_4 |
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#define SDRAM_tRAS_num 4 |
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#define SDRAM_tRCD TRCD_2 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 ) |
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#define SDRAM_tRP TRP_2 |
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#define SDRAM_tRP_num 2 |
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#define SDRAM_tRAS TRAS_3 |
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#define SDRAM_tRAS_num 3 |
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#define SDRAM_tRCD TRCD_2 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) |
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#define SDRAM_tRP TRP_1 |
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#define SDRAM_tRP_num 1 |
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#define SDRAM_tRAS TRAS_3 |
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#define SDRAM_tRAS_num 3 |
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#define SDRAM_tRCD TRCD_1 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 ) |
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#define SDRAM_tRP TRP_1 |
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#define SDRAM_tRP_num 1 |
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#define SDRAM_tRAS TRAS_3 |
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#define SDRAM_tRAS_num 3 |
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#define SDRAM_tRCD TRCD_1 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 ) |
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#define SDRAM_tRP TRP_1 |
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#define SDRAM_tRP_num 1 |
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#define SDRAM_tRAS TRAS_2 |
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#define SDRAM_tRAS_num 2 |
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#define SDRAM_tRCD TRCD_1 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#if ( CONFIG_SCLK_HZ <= 29850746 ) |
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#define SDRAM_tRP TRP_1 |
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#define SDRAM_tRP_num 1 |
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#define SDRAM_tRAS TRAS_1 |
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#define SDRAM_tRAS_num 1 |
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#define SDRAM_tRCD TRCD_1 |
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#define SDRAM_tWR TWR_2 |
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#endif |
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#endif |
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#if (CONFIG_MEM_MT48LC16M16A2TG_75) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_3 |
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#endif |
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#if (CONFIG_MEM_MT48LC64M4A2FB_7E) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_2 |
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#endif |
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#if (CONFIG_MEM_MT48LC16M8A2TG_75) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_3 |
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#endif |
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#if (CONFIG_MEM_MT48LC32M8A2_75) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_3 |
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#endif |
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#if (CONFIG_MEM_MT48LC8M16A2TG_7E) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_2 |
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#endif |
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#if (CONFIG_MEM_MT48LC8M32B2B5_7) |
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/*SDRAM INFORMATION: */ |
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */ |
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ |
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#define SDRAM_CL CL_3 |
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#endif |
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#if ( CONFIG_MEM_SIZE == 128 ) |
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#define SDRAM_SIZE EBSZ_128 |
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#endif |
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#if ( CONFIG_MEM_SIZE == 64 ) |
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#define SDRAM_SIZE EBSZ_64 |
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#endif |
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#if ( CONFIG_MEM_SIZE == 32 ) |
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#define SDRAM_SIZE EBSZ_32 |
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#endif |
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#if ( CONFIG_MEM_SIZE == 16 ) |
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#define SDRAM_SIZE EBSZ_16 |
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#endif |
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#if ( CONFIG_MEM_ADD_WDTH == 11 ) |
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#define SDRAM_WIDTH EBCAW_11 |
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#endif |
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#if ( CONFIG_MEM_ADD_WDTH == 10 ) |
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#define SDRAM_WIDTH EBCAW_10 |
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#endif |
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#if ( CONFIG_MEM_ADD_WDTH == 9 ) |
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#define SDRAM_WIDTH EBCAW_9 |
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#endif |
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#if ( CONFIG_MEM_ADD_WDTH == 8 ) |
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#define SDRAM_WIDTH EBCAW_8 |
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#endif |
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#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE |
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/* Equation from section 17 (p17-46) of BF533 HRM */ |
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#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) |
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/* Enable SCLK Out */ |
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#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS ) |
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#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 |
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#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 |
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#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) |
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#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 |
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#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1 |
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#if (flash_EBIU_AMBCTL_TT > 3 ) |
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#define flash_EBIU_AMBCTL0_TT B0TT_4 |
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#endif |
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#if (flash_EBIU_AMBCTL_TT == 3 ) |
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#define flash_EBIU_AMBCTL0_TT B0TT_3 |
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#endif |
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#if (flash_EBIU_AMBCTL_TT == 2 ) |
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#define flash_EBIU_AMBCTL0_TT B0TT_2 |
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#endif |
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#if (flash_EBIU_AMBCTL_TT < 2 ) |
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#define flash_EBIU_AMBCTL0_TT B0TT_1 |
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#endif |
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#if (flash_EBIU_AMBCTL_ST > 3 ) |
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#define flash_EBIU_AMBCTL0_ST B0ST_4 |
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#endif |
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#if (flash_EBIU_AMBCTL_ST == 3 ) |
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#define flash_EBIU_AMBCTL0_ST B0ST_3 |
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#endif |
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#if (flash_EBIU_AMBCTL_ST == 2 ) |
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#define flash_EBIU_AMBCTL0_ST B0ST_2 |
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#endif |
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#if (flash_EBIU_AMBCTL_ST < 2 ) |
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#define flash_EBIU_AMBCTL0_ST B0ST_1 |
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#endif |
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#if (flash_EBIU_AMBCTL_HT > 2 ) |
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#define flash_EBIU_AMBCTL0_HT B0HT_3 |
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#endif |
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#if (flash_EBIU_AMBCTL_HT == 2 ) |
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#define flash_EBIU_AMBCTL0_HT B0HT_2 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_HT == 1 ) |
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) |
||||
#define flash_EBIU_AMBCTL0_HT B0HT_0 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) |
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1 |
||||
#endif |
||||
|
||||
#if (flash_EBIU_AMBCTL_WAT > 14) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_15 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 14) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_14 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 13) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_13 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 12) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_12 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 11) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_11 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 10) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_10 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 9) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_9 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 8) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_8 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 7) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_7 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 6) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_6 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 5) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_5 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 4) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_4 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 3) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_3 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 2) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_2 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_WAT == 1) |
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_1 |
||||
#endif |
||||
|
||||
#if (flash_EBIU_AMBCTL_RAT > 14) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_15 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 14) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_14 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 13) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_13 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 12) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_12 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 11) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_11 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 10) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_10 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 9) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_9 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 8) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_8 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 7) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_7 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 6) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_6 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 5) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_5 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 4) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_4 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 3) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_3 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 2) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_2 |
||||
#endif |
||||
#if (flash_EBIU_AMBCTL_RAT == 1) |
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_1 |
||||
#endif |
||||
|
||||
#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN |
||||
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Reference in new issue