Wolfgang Denk
16 years ago
commit
4e37963af7
@ -1,195 +0,0 @@ |
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/*
|
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* (C) Copyright 2008 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <asm/io.h> |
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|
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/*
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* NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The |
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* values are independent of the rest of the clock settings. |
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*/ |
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|
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#define NAND_COMPATIBLE 0x01 |
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#define NOR_COMPATIBLE 0x02 |
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#define I2C_EEPROM_ADDR 0x52 |
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static char *config_labels[] = { |
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"CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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"CPU: 800 PLB: 200 OPB: 100 EBC: 100", |
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"CPU:1000 PLB: 200 OPB: 100 EBC: 100", |
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"CPU:1066 PLB: 266 OPB: 88 EBC: 88", |
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NULL |
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}; |
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|
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static u8 boot_configs[][17] = { |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, |
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0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08, |
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0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08, |
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0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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(NAND_COMPATIBLE | NOR_COMPATIBLE), |
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0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08, |
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0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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}, |
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{ |
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0, |
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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} |
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}; |
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|
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/*
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* Bytes 5,6,8,9,11 change for NAND boot |
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*/ |
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#if 0 |
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/*
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* Values for 512 page size NAND chips, not used anymore, just |
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* keep them here for reference |
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*/ |
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static u8 nand_boot[] = { |
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0x90, 0x01, 0xa0, 0x68, 0x58 |
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}; |
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#else |
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/*
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* Values for 2k page size NAND chips |
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*/ |
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static u8 nand_boot[] = { |
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0x90, 0x01, 0xa0, 0xe8, 0x58 |
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}; |
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#endif |
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static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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u8 *buf, b_nand; |
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int x, y, nbytes, selcfg; |
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extern char console_buffer[]; |
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if (argc < 2) { |
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cmd_usage(cmdtp); |
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return 1; |
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} |
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if ((strcmp(argv[1], "nor") != 0) && |
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(strcmp(argv[1], "nand") != 0)) { |
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printf("Unsupported boot-device - only nor|nand support\n"); |
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return 1; |
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} |
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|
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/* set the nand flag based on provided input */ |
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if ((strcmp(argv[1], "nand") == 0)) |
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b_nand = 1; |
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else |
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b_nand = 0; |
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printf("Available configurations: \n\n"); |
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if (b_nand) { |
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { |
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/* filter on nand compatible */ |
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if (boot_configs[x][0] & NAND_COMPATIBLE) { |
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printf(" %d - %s\n", (y+1), config_labels[x]); |
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y++; |
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} |
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} |
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} else { |
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for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { |
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/* filter on nor compatible */ |
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if (boot_configs[x][0] & NOR_COMPATIBLE) { |
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printf(" %d - %s\n", (y+1), config_labels[x]); |
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y++; |
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} |
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} |
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} |
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do { |
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nbytes = readline(" Selection [1-x / quit]: "); |
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if (nbytes) { |
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if (strcmp(console_buffer, "quit") == 0) |
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return 0; |
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selcfg = simple_strtol(console_buffer, NULL, 10); |
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if ((selcfg < 1) || (selcfg > y)) |
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nbytes = 0; |
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} |
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} while (nbytes == 0); |
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y = (selcfg - 1); |
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for (x = 0; boot_configs[x][0] != 0; x++) { |
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if (b_nand) { |
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if (boot_configs[x][0] & NAND_COMPATIBLE) { |
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if (y > 0) |
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y--; |
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else if (y < 1) |
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break; |
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} |
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} else { |
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if (boot_configs[x][0] & NOR_COMPATIBLE) { |
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if (y > 0) |
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y--; |
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else if (y < 1) |
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break; |
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} |
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} |
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} |
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buf = &boot_configs[x][1]; |
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if (b_nand) { |
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buf[5] = nand_boot[0]; |
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buf[6] = nand_boot[1]; |
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buf[8] = nand_boot[2]; |
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buf[9] = nand_boot[3]; |
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buf[11] = nand_boot[4]; |
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} |
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if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) |
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printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); |
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udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
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printf("Done\n"); |
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printf("Please power-cycle the board for the changes to take effect\n"); |
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return 0; |
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} |
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U_BOOT_CMD( |
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bootstrap, 2, 0, do_bootstrap, |
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"program the I2C bootstrap EEPROM", |
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"<nand|nor> - strap to boot from NAND or NOR flash" |
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); |
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@ -0,0 +1,87 @@ |
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/*
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* (C) Copyright 2008-2009 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <asm/ppc4xx_config.h> |
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struct ppc4xx_config ppc4xx_config_val[] = { |
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{ |
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"600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0, |
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0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0, |
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0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0, |
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0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88", |
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{ |
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0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, |
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0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88", |
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{ |
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0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0, |
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0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 |
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} |
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}, |
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}; |
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); |
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@ -0,0 +1,73 @@ |
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/*
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* (C) Copyright 2009 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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|
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#include <common.h> |
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#include <asm/ppc4xx_config.h> |
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|
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struct ppc4xx_config ppc4xx_config_val[] = { |
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{ |
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"333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", |
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{ |
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", |
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{ |
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", |
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{ |
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", |
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{ |
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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{ |
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"666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", |
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{ |
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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} |
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}, |
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}; |
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|
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int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); |
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@ -1,297 +0,0 @@ |
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/*
|
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* (C) Copyright 2000, 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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* |
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*/ |
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|
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/*
|
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* ehnus: change pll frequency. |
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* Wed Sep 5 11:45:17 CST 2007 |
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* hsun@udtech.com.cn |
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*/ |
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|
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|
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#include <common.h> |
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#include <config.h> |
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#include <command.h> |
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#include <i2c.h> |
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|
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#ifdef CONFIG_CMD_EEPROM |
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|
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#define EEPROM_CONF_OFFSET 0 |
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#define EEPROM_TEST_OFFSET 16 |
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#define EEPROM_SDSTP_PARAM 16 |
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|
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#define PLL_NAME_MAX 12 |
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#define BUF_STEP 8 |
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|
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/* eeprom_wirtes 8Byte per op. */ |
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#define EEPROM_ALTER_FREQ(freq) \ |
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do { \
|
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int __i; \
|
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for (__i = 0; __i < 2; __i++) \
|
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eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
|
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EEPROM_CONF_OFFSET + __i*BUF_STEP, \
|
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pll_select[freq], \
|
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BUF_STEP + __i*BUF_STEP); \
|
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} while (0) |
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|
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#define PDEBUG |
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#ifdef PDEBUG |
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#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) |
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#else |
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#define PLL_DEBUG |
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#endif |
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|
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typedef enum { |
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PLL_ebc20, |
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PLL_333, |
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PLL_4001, |
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PLL_4002, |
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PLL_533, |
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PLL_600, |
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PLL_666, /* For now, kilauea can't support */ |
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RCONF, |
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WTEST, |
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PLL_TOTAL |
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} pll_freq_t; |
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|
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static const char |
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pll_name[][PLL_NAME_MAX] = { |
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"PLL_ebc20", |
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"PLL_333", |
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"PLL_400@1", |
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"PLL_400@2", |
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"PLL_533", |
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"PLL_600", |
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"PLL_666", |
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"RCONF", |
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"WTEST", |
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"" |
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}; |
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|
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/*
|
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* ehnus: |
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*/ |
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static uchar |
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pll_select[][EEPROM_SDSTP_PARAM] = { |
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/* 0: CPU 333MHz EBC 20MHz, for test only */ |
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{ |
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0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 0: 333 */ |
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{ |
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0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 1: 400_266 */ |
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{ |
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0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 2: 400 */ |
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{ |
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0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 3: 533 */ |
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{ |
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0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 4: 600 */ |
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{ |
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0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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/* 5: 666 */ |
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{ |
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0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, |
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0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 |
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}, |
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|
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{} |
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}; |
||||
|
||||
static uchar |
||||
testbuf[EEPROM_SDSTP_PARAM] = { |
||||
0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, |
||||
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff |
||||
}; |
||||
|
||||
static void |
||||
pll_debug(int off) |
||||
{ |
||||
int i; |
||||
uchar buffer[EEPROM_SDSTP_PARAM]; |
||||
|
||||
memset(buffer, 0, sizeof(buffer)); |
||||
eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, |
||||
buffer, EEPROM_SDSTP_PARAM); |
||||
|
||||
printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); |
||||
for (i = 0; i < EEPROM_SDSTP_PARAM; i++) |
||||
printf("%02x ", buffer[i]); |
||||
printf("\n"); |
||||
} |
||||
|
||||
static void |
||||
test_write(void) |
||||
{ |
||||
printf("Debug: test eeprom_write ... "); |
||||
|
||||
/*
|
||||
* Write twice, 8 bytes per write |
||||
*/ |
||||
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, |
||||
testbuf, 8); |
||||
eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, |
||||
testbuf, 16); |
||||
printf("done\n"); |
||||
|
||||
pll_debug(EEPROM_TEST_OFFSET); |
||||
} |
||||
|
||||
int |
||||
do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
char c = '\0'; |
||||
pll_freq_t pll_freq; |
||||
if (argc < 2) { |
||||
cmd_usage(cmdtp); |
||||
goto ret; |
||||
} |
||||
|
||||
for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) |
||||
if (!strcmp(pll_name[pll_freq], argv[1])) |
||||
break; |
||||
|
||||
switch (pll_freq) { |
||||
case PLL_ebc20: |
||||
case PLL_333: |
||||
case PLL_4001: |
||||
case PLL_4002: |
||||
case PLL_533: |
||||
case PLL_600: |
||||
EEPROM_ALTER_FREQ(pll_freq); |
||||
break; |
||||
|
||||
case PLL_666: /* not support */ |
||||
printf("Choose this option will result in a boot failure." |
||||
"\nContinue? (Y/N): "); |
||||
|
||||
c = getc(); putc('\n'); |
||||
|
||||
if ((c == 'y') || (c == 'Y')) { |
||||
EEPROM_ALTER_FREQ(pll_freq); |
||||
break; |
||||
} |
||||
goto ret; |
||||
|
||||
case RCONF: |
||||
pll_debug(EEPROM_CONF_OFFSET); |
||||
goto ret; |
||||
case WTEST: |
||||
printf("DEBUG: write test\n"); |
||||
test_write(); |
||||
goto ret; |
||||
|
||||
default: |
||||
printf("Invalid options\n\n"); |
||||
cmd_usage(cmdtp); |
||||
goto ret; |
||||
} |
||||
|
||||
printf("PLL set to %s, " |
||||
"reset the board to take effect\n", pll_name[pll_freq]); |
||||
|
||||
PLL_DEBUG; |
||||
ret: |
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, |
||||
"change pll frequence", |
||||
"pllalter <selection> - change pll frequence \n\n\
|
||||
** New freq take effect after reset. ** \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t Same as PLL_333 \n\
|
||||
\t except \n\
|
||||
\t EBC: 20 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 666 MHz \n\
|
||||
\t CPU: 333 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 83 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 133 MHz \n\
|
||||
\t OPB: 66 MHz \n\
|
||||
\t DDR: 133 MHz \n\
|
||||
------------------------------------------------\n\
|
||||
PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 800 MHz \n\
|
||||
\t CPU: 400 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1066 MHz \n\
|
||||
\t CPU: 533 MHz \n\
|
||||
\t PLB: 177 MHz \n\
|
||||
\t OPB: 88 MHz \n\
|
||||
\t DDR: 177 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1200 MHz \n\
|
||||
\t CPU: 600 MHz \n\
|
||||
\t PLB: 200 MHz \n\
|
||||
\t OPB: 100 MHz \n\
|
||||
\t DDR: 200 MHz \n\
|
||||
----------------------------------------------\n\
|
||||
PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
|
||||
\t VCO: 1333 MHz \n\
|
||||
\t CPU: 666 MHz \n\
|
||||
\t PLB: 166 MHz \n\
|
||||
\t OPB: 83 MHz \n\
|
||||
\t DDR: 166 MHz \n\
|
||||
-----------------------------------------------\n\
|
||||
RCONF: Read current eeprom configuration. \n\
|
||||
-----------------------------------------------\n\
|
||||
WTEST: Test EEPROM write with predefined values\n\
|
||||
-----------------------------------------------" |
||||
); |
||||
|
||||
#endif /* CONFIG_CMD_EEPROM */ |
||||
@ -0,0 +1,53 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y = $(BOARD).o
|
||||
COBJS-y += ../common/cmd_loadpci.o
|
||||
COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,61 @@ |
||||
/*
|
||||
* (C) Copyright 2008-2009 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/ppc4xx_config.h> |
||||
|
||||
struct ppc4xx_config ppc4xx_config_val[] = { |
||||
{ |
||||
"133", |
||||
"CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", |
||||
{ |
||||
0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00 |
||||
} |
||||
}, |
||||
{ |
||||
"266", |
||||
"CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66", |
||||
{ |
||||
0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00 |
||||
} |
||||
}, |
||||
{ |
||||
"333", |
||||
"CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111", |
||||
{ |
||||
0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00 |
||||
} |
||||
}, |
||||
}; |
||||
|
||||
int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); |
||||
@ -0,0 +1,23 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
@ -0,0 +1,521 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/4xx_pci.h> |
||||
#include <command.h> |
||||
#include <malloc.h> |
||||
|
||||
/*
|
||||
* PMC405-DE cpld registers |
||||
* - all registers are 8 bit |
||||
* - all registers are on 32 bit addesses |
||||
*/ |
||||
struct pmc405de_cpld { |
||||
/* cpld design version */ |
||||
u8 version; |
||||
u8 reserved0[3]; |
||||
|
||||
/* misc. status lines */ |
||||
u8 status; |
||||
u8 reserved1[3]; |
||||
|
||||
/*
|
||||
* gated control flags |
||||
* gate bit(s) must be written with '1' to |
||||
* access control flag |
||||
*/ |
||||
u8 control; |
||||
u8 reserved2[3]; |
||||
}; |
||||
|
||||
#define CPLD_VERSION_MASK 0x0f |
||||
#define CPLD_CONTROL_POSTLED_N 0x01 |
||||
#define CPLD_CONTROL_POSTLED_GATE 0x02 |
||||
#define CPLD_CONTROL_RESETOUT_N 0x40 |
||||
#define CPLD_CONTROL_RESETOUT_N_GATE 0x80 |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
extern void __ft_board_setup(void *blob, bd_t *bd); |
||||
extern void pll_write(u32 a, u32 b); |
||||
|
||||
static int wait_for_pci_ready_done; |
||||
|
||||
static int is_monarch(void); |
||||
static int pci_is_66mhz(void); |
||||
static int board_revision(void); |
||||
static int cpld_revision(void); |
||||
static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div); |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
u32 pllmr0, pllmr1; |
||||
|
||||
/*
|
||||
* check M66EN and patch PLB:PCI divider for 66MHz PCI |
||||
* |
||||
* fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1 |
||||
* fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2 |
||||
* fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2 |
||||
* fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3 |
||||
* |
||||
* calling upd_plb_pci_div() may end in calling pll_write() which will |
||||
* do a chip reset and never return. |
||||
*/ |
||||
pllmr0 = mfdcr(CPC0_PLLMR0); |
||||
pllmr1 = mfdcr(CPC0_PLLMR1); |
||||
|
||||
if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) { |
||||
/* fCPU=333MHz, fPLB=111MHz */ |
||||
if (pci_is_66mhz()) |
||||
upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1); |
||||
else |
||||
upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); |
||||
} else { |
||||
/* fCPU=133|266MHz, fPLB=133MHz */ |
||||
if (pci_is_66mhz()) |
||||
upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2); |
||||
else |
||||
upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3); |
||||
} |
||||
|
||||
/*
|
||||
* IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive |
||||
* IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive |
||||
* IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive |
||||
* IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive |
||||
* IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive |
||||
* IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive |
||||
* IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive |
||||
*/ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr(uicer, 0x00000000); /* disable all ints */ |
||||
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
||||
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ |
||||
mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest prio */ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
|
||||
/*
|
||||
* EBC Configuration Register: |
||||
* - set ready timeout to 512 ebc-clks -> ca. 15 us |
||||
* - EBC lines are always driven |
||||
*/ |
||||
mtebc(epcr, 0xa8400000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div) |
||||
{ |
||||
if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div) |
||||
pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
int i; |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
struct pmc405de_cpld *cpld = |
||||
(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
if (!is_monarch()) { |
||||
/* PCI configuration done: release EREADY */ |
||||
setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY); |
||||
setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY); |
||||
} |
||||
|
||||
/* turn off POST LED */ |
||||
out_8(&cpld->control, |
||||
CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE); |
||||
|
||||
/* turn on LEDs: RUN, A, B */ |
||||
clrbits_be32(&gpio0->or, |
||||
CONFIG_SYS_GPIO_LEDRUN_N | |
||||
CONFIG_SYS_GPIO_LEDA_N | |
||||
CONFIG_SYS_GPIO_LEDB_N); |
||||
|
||||
for (i=0; i < 200; i++) |
||||
udelay(1000); |
||||
|
||||
/* turn off LEDs: A, B */ |
||||
setbits_be32(&gpio0->or, |
||||
CONFIG_SYS_GPIO_LEDA_N | |
||||
CONFIG_SYS_GPIO_LEDB_N); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
static int is_monarch(void) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0; |
||||
} |
||||
|
||||
static int pci_is_66mhz(void) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN); |
||||
} |
||||
|
||||
static int board_revision(void) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >> |
||||
CONFIG_SYS_GPIO_HWREV_SHIFT); |
||||
} |
||||
|
||||
static int cpld_revision(void) |
||||
{ |
||||
struct pmc405de_cpld *cpld = |
||||
(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; |
||||
return ((in_8(&cpld->version) & CPLD_VERSION_MASK)); |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity |
||||
*/ |
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: esd GmbH - PMC-CPU/405-DE"); |
||||
|
||||
gd->board_type = board_revision(); |
||||
printf(", Rev 1.%ld, ", gd->board_type); |
||||
|
||||
if (!is_monarch()) |
||||
puts("non-"); |
||||
|
||||
printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n", |
||||
pci_is_66mhz() ? "66" : "33", cpld_revision()); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
static void wait_for_pci_ready(void) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
int i; |
||||
char *s = getenv("pcidelay"); |
||||
|
||||
/* only wait once */ |
||||
if (wait_for_pci_ready_done) |
||||
return; |
||||
|
||||
/*
|
||||
* We have our own handling of the pcidelay variable. |
||||
* Using CONFIG_PCI_BOOTDELAY enables pausing for host |
||||
* and adapter devices. For adapter devices we do not |
||||
* want this. |
||||
*/ |
||||
if (s) { |
||||
int ms = simple_strtoul(s, NULL, 10); |
||||
printf("PCI: Waiting for %d ms\n", ms); |
||||
for (i=0; i<ms; i++) |
||||
udelay(1000); |
||||
} |
||||
|
||||
if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) { |
||||
printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); |
||||
while (1) { |
||||
if (ctrlc()) { |
||||
puts("abort\n"); |
||||
break; |
||||
} |
||||
if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) { |
||||
printf("done\n"); |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
wait_for_pci_ready_done = 1; |
||||
} |
||||
|
||||
/*
|
||||
* Overwrite weak is_pci_host() |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
*/ |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
char *s; |
||||
|
||||
if (!is_monarch()) { |
||||
/*
|
||||
* Overwrite PCI identification when running in |
||||
* non-monarch mode |
||||
* This should be moved into pci_target_init() |
||||
* when it is sometimes available for 405 CPUs |
||||
*/ |
||||
pci_write_config_word(PCIDEVID_405GP, |
||||
PCI_SUBSYSTEM_ID, |
||||
CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); |
||||
pci_write_config_word(PCIDEVID_405GP, |
||||
PCI_CLASS_SUB_CODE, |
||||
CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); |
||||
} |
||||
|
||||
s = getenv("pciscan"); |
||||
if (s == NULL) { |
||||
if (is_monarch()) { |
||||
wait_for_pci_ready(); |
||||
return 1; |
||||
} else { |
||||
return 0; |
||||
} |
||||
} else { |
||||
if (!strcmp(s, "yes")) |
||||
return 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Overwrite weak pci_pre_init() |
||||
* |
||||
* The default implementation enables the 405EP |
||||
* internal PCI arbiter. We do not want that |
||||
* on a PMC module. |
||||
*/ |
||||
int pci_pre_init(struct pci_controller *hose) |
||||
{ |
||||
return 1; |
||||
} |
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
||||
void ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
int rc; |
||||
|
||||
__ft_board_setup(blob, bd); |
||||
|
||||
/*
|
||||
* Disable PCI in non-monarch mode. |
||||
*/ |
||||
if (!is_monarch()) { |
||||
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", |
||||
"disabled", sizeof("disabled"), 1); |
||||
if (rc) { |
||||
printf("Unable to update property status in PCI node, " |
||||
"err=%s\n", |
||||
fdt_strerror(rc)); |
||||
} |
||||
} |
||||
} |
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |
||||
|
||||
#if defined(CONFIG_SYS_EEPROM_WREN) |
||||
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||
* <state> -1: deliver current state |
||||
* 0: disable write |
||||
* 1: enable write |
||||
* Returns: -1: wrong device address |
||||
* 0: dis-/en- able done |
||||
* 0/1: current state if <state> was -1. |
||||
*/ |
||||
int eeprom_write_enable(unsigned dev_addr, int state) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
|
||||
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { |
||||
return -1; |
||||
} else { |
||||
switch (state) { |
||||
case 1: |
||||
/* Enable write access, clear bit GPIO0. */ |
||||
clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); |
||||
state = 0; |
||||
break; |
||||
case 0: |
||||
/* Disable write access, set bit GPIO0. */ |
||||
setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); |
||||
state = 0; |
||||
break; |
||||
default: |
||||
/* Read current status back. */ |
||||
state = (0 == (in_be32(&gpio0->or) & |
||||
CONFIG_SYS_GPIO_EEPROM_WP)); |
||||
break; |
||||
} |
||||
} |
||||
return state; |
||||
} |
||||
|
||||
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
int query = argc == 1; |
||||
int state = 0; |
||||
|
||||
if (query) { |
||||
/* Query write access state. */ |
||||
state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1); |
||||
if (state < 0) { |
||||
puts("Query of write access state failed.\n"); |
||||
} else { |
||||
printf("Write access for device 0x%0x is %sabled.\n", |
||||
CONFIG_SYS_I2C_EEPROM_ADDR, |
||||
state ? "en" : "dis"); |
||||
state = 0; |
||||
} |
||||
} else { |
||||
if ('0' == argv[1][0]) { |
||||
/* Disable write access. */ |
||||
state = eeprom_write_enable( |
||||
CONFIG_SYS_I2C_EEPROM_ADDR, 0); |
||||
} else { |
||||
/* Enable write access. */ |
||||
state = eeprom_write_enable( |
||||
CONFIG_SYS_I2C_EEPROM_ADDR, 1); |
||||
} |
||||
if (state < 0) |
||||
puts ("Setup of write access state failed.\n"); |
||||
} |
||||
|
||||
return state; |
||||
} |
||||
|
||||
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, |
||||
"Enable / disable / query EEPROM write access", |
||||
"" |
||||
); |
||||
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ |
||||
|
||||
#if defined(CONFIG_PRAM) |
||||
#include <environment.h> |
||||
extern env_t *env_ptr; |
||||
|
||||
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
u32 pram, nextbase, base; |
||||
char *v; |
||||
u32 param; |
||||
ulong *lptr; |
||||
|
||||
v = getenv("pram"); |
||||
if (v) |
||||
pram = simple_strtoul(v, NULL, 10); |
||||
else { |
||||
printf("Error: pram undefined. Please define pram in KiB\n"); |
||||
return 1; |
||||
} |
||||
|
||||
base = gd->bd->bi_memsize; |
||||
#if defined(CONFIG_LOGBUFFER) |
||||
base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; |
||||
#endif |
||||
/*
|
||||
* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE |
||||
*/ |
||||
param = base - (pram << 10); |
||||
printf("PARAM: @%08x\n", param); |
||||
debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base); |
||||
|
||||
/* clear entire PA ram */ |
||||
memset((void*)param, 0, (pram << 10)); |
||||
|
||||
/* reserve 4k for pointer field */ |
||||
nextbase = base - 4096; |
||||
lptr = (ulong*)(base); |
||||
|
||||
/*
|
||||
* *(--lptr) = item_size; |
||||
* *(--lptr) = base - item_base = distance from field top; |
||||
*/ |
||||
|
||||
/* env is first (4k aligned) */ |
||||
nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); |
||||
memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); |
||||
*(--lptr) = CONFIG_ENV_SIZE; /* size */ |
||||
*(--lptr) = base - nextbase; /* offset | type=0 */ |
||||
|
||||
/* free section */ |
||||
*(--lptr) = nextbase - param; /* size */ |
||||
*(--lptr) = (base - param) | 126; /* offset | type=126 */ |
||||
|
||||
/* terminate pointer field */ |
||||
*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); |
||||
*(--lptr) = 0; /* offset=0 -> terminator */ |
||||
return 0; |
||||
} |
||||
U_BOOT_CMD( |
||||
painit, 1, 1, do_painit, |
||||
"prepare PciAccess system", |
||||
"" |
||||
); |
||||
#endif /* CONFIG_PRAM */ |
||||
|
||||
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; |
||||
setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N); |
||||
return 0; |
||||
} |
||||
U_BOOT_CMD( |
||||
selfreset, 1, 1, do_selfreset, |
||||
"assert self-reset# signal", |
||||
"" |
||||
); |
||||
|
||||
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
struct pmc405de_cpld *cpld = |
||||
(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
if (argc > 1) { |
||||
if (argv[1][0] == '0') { |
||||
/* assert */ |
||||
printf("PMC-RESETOUT# asserted\n"); |
||||
out_8(&cpld->control, |
||||
CPLD_CONTROL_RESETOUT_N_GATE); |
||||
} else { |
||||
/* deassert */ |
||||
printf("PMC-RESETOUT# deasserted\n"); |
||||
out_8(&cpld->control, |
||||
CPLD_CONTROL_RESETOUT_N | |
||||
CPLD_CONTROL_RESETOUT_N_GATE); |
||||
} |
||||
} else { |
||||
printf("PMC-RESETOUT# is %s\n", |
||||
(in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ? |
||||
"inactive" : "active"); |
||||
} |
||||
return 0; |
||||
} |
||||
U_BOOT_CMD( |
||||
resetout, 2, 1, do_resetout, |
||||
"assert PMC-RESETOUT# signal", |
||||
"" |
||||
); |
||||
@ -0,0 +1,133 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.eh_frame) |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,51 @@ |
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,24 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
@ -0,0 +1,137 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
enum { |
||||
HWTYPE_DLVISION_CPU = 0, |
||||
HWTYPE_DLVISION_CON = 1, |
||||
}; |
||||
|
||||
#define HWREV_100 6 |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr(uicer, 0x00000000); /* disable all ints */ |
||||
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ |
||||
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ |
||||
mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
|
||||
/*
|
||||
* EBC Configuration Register: set ready timeout to 512 ebc-clks |
||||
* -> ca. 15 us |
||||
*/ |
||||
mtebc(epcr, 0xa8400000); /* ebc always driven */ |
||||
|
||||
/*
|
||||
* setup io-latches |
||||
*/ |
||||
out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0); |
||||
out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002); |
||||
out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000); |
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
/*
|
||||
* set "startup-finished"-gpios |
||||
*/ |
||||
gpio_write_bit(21, 0); |
||||
gpio_write_bit(22, 1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26); |
||||
u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36); |
||||
u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76); |
||||
u8 unit_type; |
||||
u8 local_con; |
||||
u8 audio; |
||||
u8 hardware_version; |
||||
|
||||
printf("Board: "); |
||||
|
||||
unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00; |
||||
local_con = (channel2_msr & 0x20) ? 0x01 : 0x00; |
||||
audio = (channel3_msr & 0x20) ? 0x01 : 0x00; |
||||
hardware_version = |
||||
((channel7_msr & 0x20) ? 0x01 : 0x00) |
||||
| ((channel7_msr & 0x80) ? 0x02 : 0x00) |
||||
| ((channel7_msr & 0x40) ? 0x04 : 0x00); |
||||
|
||||
switch (unit_type) { |
||||
case HWTYPE_DLVISION_CON: |
||||
printf("DL-Vision-CON"); |
||||
break; |
||||
|
||||
case HWTYPE_DLVISION_CPU: |
||||
printf("DL-Vision-CPU"); |
||||
break; |
||||
|
||||
default: |
||||
printf("UnitType %d, unsupported", unit_type); |
||||
break; |
||||
} |
||||
|
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
puts("\n "); |
||||
|
||||
switch (hardware_version) { |
||||
case HWREV_100: |
||||
printf("HW-Ver 1.00"); |
||||
break; |
||||
|
||||
default: |
||||
printf("HW-Ver %d, unsupported", |
||||
hardware_version); |
||||
break; |
||||
} |
||||
|
||||
if (local_con) |
||||
printf(", local console"); |
||||
|
||||
if (audio) |
||||
printf(", audio support"); |
||||
|
||||
puts("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,132 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,244 @@ |
||||
/*
|
||||
* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <spd_sdram.h> |
||||
#include <i2c.h> |
||||
#include <net.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
unsigned long sdrreg; |
||||
|
||||
/*
|
||||
* Enable GPIO for pins 18 - 24 |
||||
* 18 = SEEPROM_WP |
||||
* 19 = #M_RST |
||||
* 20 = #MONARCH |
||||
* 21 = #LED_ALARM |
||||
* 22 = #LED_ACT |
||||
* 23 = #LED_STATUS1 |
||||
* 24 = #LED_STATUS2 |
||||
*/ |
||||
mfsdr(sdr_pfc0, sdrreg); |
||||
mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); |
||||
out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); |
||||
LED0_OFF(); |
||||
LED1_OFF(); |
||||
LED2_OFF(); |
||||
LED3_OFF(); |
||||
|
||||
/* Setup the external bus controller/chip selects */ |
||||
mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */ |
||||
mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ |
||||
mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */ |
||||
mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ |
||||
mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ |
||||
mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ |
||||
mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ |
||||
mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ |
||||
|
||||
/*
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
* |
||||
* Because of the interrupt handling rework to handle 440GX interrupts |
||||
* with the common code, we needed to change names of the UIC registers. |
||||
* Here the new relationship: |
||||
* |
||||
* U-Boot name 440GX name |
||||
* ----------------------- |
||||
* UIC0 UICB0 |
||||
* UIC1 UIC0 |
||||
* UIC2 UIC1 |
||||
* UIC3 UIC2 |
||||
*/ |
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic1er, 0x00000000); /* disable all */ |
||||
mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ |
||||
mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */ |
||||
mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */ |
||||
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic2er, 0x00000000); /* disable all */ |
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */ |
||||
mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */ |
||||
mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */ |
||||
mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr(uic3sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic3er, 0x00000000); /* disable all */ |
||||
mtdcr(uic3cr, 0x00000000); /* all non-critical */ |
||||
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */ |
||||
mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic3sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr(uic0sr, 0xfc000000); /* clear all */ |
||||
mtdcr(uic0er, 0x00000000); /* disable all */ |
||||
mtdcr(uic0cr, 0x00000000); /* all non-critical */ |
||||
mtdcr(uic0pr, 0xfc000000); /* */ |
||||
mtdcr(uic0tr, 0x00000000); /* */ |
||||
mtdcr(uic0vr, 0x00000001); /* */ |
||||
|
||||
LED0_ON(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char *s; |
||||
|
||||
printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME); |
||||
printf(" "); |
||||
s = getenv("board_rev"); |
||||
if (s) |
||||
printf("Rev %s, ", s); |
||||
s = getenv("serial#"); |
||||
if (s) |
||||
printf("Serial# %s, ", s); |
||||
s = getenv("board_cfg"); |
||||
if (s) |
||||
printf("Cfg %s", s); |
||||
printf("\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
return spd_sdram(); |
||||
} |
||||
|
||||
/*
|
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
*/ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
int pci_pre_init(struct pci_controller * hose) |
||||
{ |
||||
unsigned long strap; |
||||
|
||||
/* See if we're supposed to setup the pci */ |
||||
mfsdr(sdr_sdstp1, strap); |
||||
if ((strap & 0x00010000) == 0) |
||||
return 0; |
||||
|
||||
#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) |
||||
/* Setup System Device Register PCIX0_XCR */ |
||||
mfsdr(sdr_xcr, strap); |
||||
strap &= 0x0f000000; |
||||
mtsdr(sdr_xcr, strap); |
||||
#endif |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
||||
/*
|
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
*/ |
||||
void pci_target_init(struct pci_controller * hose) |
||||
{ |
||||
/* Disable everything */ |
||||
out32r(PCIX0_PIM0SA, 0); |
||||
out32r(PCIX0_PIM1SA, 0); |
||||
out32r(PCIX0_PIM2SA, 0); |
||||
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ |
||||
|
||||
/*
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
||||
* options to not support sizes such as 128/256 MB. |
||||
*/ |
||||
out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); |
||||
out32r(PCIX0_PIM0LAH, 0); |
||||
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); |
||||
|
||||
out32r(PCIX0_BAR0, 0); |
||||
|
||||
/* Program the board's subsystem id/vendor id */ |
||||
out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); |
||||
out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); |
||||
|
||||
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
*/ |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
return ctrlc(); |
||||
} |
||||
|
||||
void post_word_store(ulong a) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); |
||||
|
||||
*save_addr = a; |
||||
} |
||||
|
||||
ulong post_word_load(void) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); |
||||
|
||||
return *save_addr; |
||||
} |
||||
#endif |
||||
@ -1,607 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com> |
||||
* Add support for Am29F016D and dynamic switch setting. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Modified 4/5/2001 |
||||
* Wait for completion of each sector erase command issued |
||||
* 4/5/2001 |
||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com |
||||
*/ |
||||
|
||||
/*
|
||||
* Ported to XPedite1000, 1/2 mb boot flash only |
||||
* Travis B. Sawyer, <travis.sawyer@sandburst.com> |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
|
||||
#undef DEBUG |
||||
#ifdef DEBUG |
||||
#define DEBUGF(x...) printf(x) |
||||
#else |
||||
#define DEBUGF(x...) |
||||
#endif /* DEBUG */ |
||||
|
||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
||||
#define FLASH_ONBD_N 2 /* 00000010 */ |
||||
#define FLASH_SRAM_SEL 1 /* 00000001 */ |
||||
|
||||
#define BOOT_SMALL_FLASH_VAL 4 |
||||
#define FLASH_ONBD_N_VAL 2 |
||||
#define FLASH_SRAM_SEL_VAL 1 |
||||
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { |
||||
{0xfff80000}, /* 0:000: configuraton 3 */ |
||||
{0xfff90000}, /* 1:001: configuraton 4 */ |
||||
{0xfffa0000}, /* 2:010: configuraton 7 */ |
||||
{0xfffb0000}, /* 3:011: configuraton 8 */ |
||||
{0xfffc0000}, /* 4:100: configuraton 1 */ |
||||
{0xfffd0000}, /* 5:101: configuraton 2 */ |
||||
{0xfffe0000}, /* 6:110: configuraton 5 */ |
||||
{0xffff0000} /* 7:111: configuraton 6 */ |
||||
}; |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data); |
||||
|
||||
|
||||
#ifdef CONFIG_XPEDITE1K |
||||
#define ADDR0 0x5555 |
||||
#define ADDR1 0x2aaa |
||||
#define FLASH_WORD_SIZE unsigned char |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long total_b = 0; |
||||
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; |
||||
unsigned short index = 0; |
||||
int i; |
||||
|
||||
|
||||
DEBUGF("\n"); |
||||
DEBUGF("FLASH: Index: %d\n", index); |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
flash_info[i].sector_count = -1; |
||||
flash_info[i].size = 0; |
||||
|
||||
/* check whether the address is 0 */ |
||||
if (flash_addr_table[index][i] == 0) { |
||||
continue; |
||||
} |
||||
|
||||
/* call flash_get_size() to initialize sector address */ |
||||
size_b[i] = flash_get_size( |
||||
(vu_long *)flash_addr_table[index][i], &flash_info[i]); |
||||
flash_info[i].size = size_b[i]; |
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
||||
i, size_b[i], size_b[i]<<20); |
||||
flash_info[i].sector_count = -1; |
||||
flash_info[i].size = 0; |
||||
} |
||||
|
||||
total_b += flash_info[i].size; |
||||
} |
||||
|
||||
return total_b; |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
int k; |
||||
int size; |
||||
int erased; |
||||
volatile unsigned long *flash; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_SST: printf ("SST "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n", |
||||
info->size >> 10, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
/*
|
||||
* Check if whole sector is erased |
||||
*/ |
||||
if (i != (info->sector_count-1)) |
||||
size = info->start[i+1] - info->start[i]; |
||||
else |
||||
size = info->start[0] + info->size - info->start[i]; |
||||
erased = 1; |
||||
flash = (volatile unsigned long *)info->start[i]; |
||||
size = size >> 2; /* divide by 4 for longword access */ |
||||
for (k=0; k<size; k++) |
||||
{ |
||||
if (*flash++ != 0xffffffff) |
||||
{ |
||||
erased = 0; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s%s", |
||||
info->start[i], |
||||
erased ? " E" : " ", |
||||
info->protect[i] ? "RO " : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
||||
{ |
||||
short i; |
||||
FLASH_WORD_SIZE value; |
||||
ulong base = (ulong)addr; |
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; |
||||
|
||||
DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
udelay(10000); |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
udelay(1000); |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
udelay(1000); |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; |
||||
udelay(1000); |
||||
|
||||
#ifdef CONFIG_ADCIOP |
||||
value = addr2[2]; |
||||
#else |
||||
value = addr2[0]; |
||||
#endif |
||||
|
||||
DEBUGF("FLASH MANUFACT: %x\n", value); |
||||
|
||||
switch (value) { |
||||
case (FLASH_WORD_SIZE)AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case (FLASH_WORD_SIZE)FUJ_MANUFACT: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
case (FLASH_WORD_SIZE)SST_MANUFACT: |
||||
info->flash_id = FLASH_MAN_SST; |
||||
break; |
||||
case (FLASH_WORD_SIZE)STM_MANUFACT: |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
#ifdef CONFIG_ADCIOP |
||||
value = addr2[0]; /* device ID */ |
||||
debug ("\ndev_code=%x\n", value); |
||||
#else |
||||
value = addr2[1]; /* device ID */ |
||||
#endif |
||||
|
||||
DEBUGF("\nFLASH DEVICEID: %x\n", value); |
||||
|
||||
switch (value) { |
||||
case (FLASH_WORD_SIZE)AMD_ID_LV040B: |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; /* => 512 kb */ |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
/* set up sector start address table */ |
||||
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
||||
(info->flash_id == FLASH_AM040) || |
||||
(info->flash_id == FLASH_AMD016)) { |
||||
for (i = 0; i < info->sector_count; i++) |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} else { |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00004000; |
||||
info->start[2] = base + 0x00006000; |
||||
info->start[3] = base + 0x00008000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00010000) - 0x00030000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00004000; |
||||
info->start[i--] = base + info->size - 0x00006000; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00010000; |
||||
} |
||||
} |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
||||
#ifdef CONFIG_ADCIOP |
||||
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
||||
info->protect[i] = addr2[4] & 1; |
||||
#else |
||||
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) |
||||
info->protect[i] = 0; |
||||
else |
||||
info->protect[i] = addr2[2] & 1; |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
#if 0 /* test-only */
|
||||
#ifdef CONFIG_ADCIOP |
||||
addr2 = (volatile unsigned char *)info->start[0]; |
||||
addr2[ADDR0] = 0xAA; |
||||
addr2[ADDR1] = 0x55; |
||||
addr2[ADDR0] = 0xF0; /* reset bank */ |
||||
#else |
||||
addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
||||
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
#endif |
||||
#else /* test-only */ |
||||
addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
||||
*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
#endif /* test-only */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
int wait_for_DQ7(flash_info_t *info, int sect) |
||||
{ |
||||
ulong start, now, last; |
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { |
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return -1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); |
||||
volatile FLASH_WORD_SIZE *addr2; |
||||
int flag, prot, sect, l_sect; |
||||
int i; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("Can't erase unknown flash type - aborted\n"); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); |
||||
printf("Erasing sector %p\n", addr2); |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ |
||||
for (i=0; i<50; i++) |
||||
udelay(1000); /* wait 1 ms */ |
||||
} else { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ |
||||
} |
||||
l_sect = sect; |
||||
/*
|
||||
* Wait for each sector to complete, it's more |
||||
* reliable. According to AMD Spec, you must |
||||
* issue all erase commands within a specified |
||||
* timeout. This has been seen to fail, especially |
||||
* if printf()s are included (for debug)!! |
||||
*/ |
||||
wait_for_DQ7(info, sect); |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
#if 0 |
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
wait_for_DQ7(info, l_sect); |
||||
|
||||
DONE: |
||||
#endif |
||||
/* reset to read mode */ |
||||
addr = (FLASH_WORD_SIZE *)info->start[0]; |
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t * info, ulong dest, ulong data) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); |
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; |
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; |
||||
ulong start; |
||||
int i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) & |
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { |
||||
return (2); |
||||
} |
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { |
||||
int flag; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; |
||||
|
||||
dest2[i] = data2[i]; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != |
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { |
||||
|
||||
if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
@ -1,393 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <spd_sdram.h> |
||||
#include <i2c.h> |
||||
#include <net.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
||||
#define FLASH_ONBD_N 2 /* 00000010 */ |
||||
#define FLASH_SRAM_SEL 1 /* 00000001 */ |
||||
|
||||
long int fixed_sdram (void); |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
unsigned long sdrreg; |
||||
/* TBS: Setup the GPIO access for the user LEDs */ |
||||
mfsdr(sdr_pfc0, sdrreg); |
||||
mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); |
||||
out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); |
||||
LED0_OFF(); |
||||
LED1_OFF(); |
||||
LED2_OFF(); |
||||
LED3_OFF(); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects |
||||
*-------------------------------------------------------------------*/ |
||||
|
||||
/* set the bus controller */ |
||||
mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ |
||||
mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ |
||||
mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ |
||||
mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
*-------------------------------------------------------------------*/ |
||||
/*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts |
||||
* with the common code, we needed to change names of the UIC registers. |
||||
* Here the new relationship: |
||||
* |
||||
* U-Boot name 440GX name |
||||
* ----------------------- |
||||
* UIC0 UICB0 |
||||
* UIC1 UIC0 |
||||
* UIC2 UIC1 |
||||
* UIC3 UIC2 |
||||
*/ |
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic1er, 0x00000000); /* disable all */ |
||||
mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ |
||||
mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */ |
||||
mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */ |
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic2er, 0x00000000); /* disable all */ |
||||
mtdcr (uic2cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */ |
||||
mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */ |
||||
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic3sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic3er, 0x00000000); /* disable all */ |
||||
mtdcr (uic3cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ |
||||
mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic3sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic0sr, 0xfc000000); /* clear all */ |
||||
mtdcr (uic0er, 0x00000000); /* disable all */ |
||||
mtdcr (uic0cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic0pr, 0xfc000000); /* */ |
||||
mtdcr (uic0tr, 0x00000000); /* */ |
||||
mtdcr (uic0vr, 0x00000001); /* */ |
||||
|
||||
LED0_ON(); |
||||
|
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
printf ("Board: XES XPedite1000 440GX\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
phys_size_t initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CONFIG_SYS_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) 0x00000000; |
||||
uint *pend = (uint *) 0x08000000; |
||||
uint *p; |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
* |
||||
* Assumes: 128 MB, non-ECC, non-registered |
||||
* PLB @ 133 MHz |
||||
* |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
uint reg; |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ |
||||
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
||||
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ |
||||
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ |
||||
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem |
||||
*------------------------------------------------------------------*/ |
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB |
||||
*/ |
||||
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
||||
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ |
||||
/* RA=10 RD=3 */ |
||||
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
||||
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ |
||||
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ |
||||
udelay (400); /* Delay 200 usecs (min) */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ |
||||
for (;;) { |
||||
mfsdram (mem_mcsts, reg); |
||||
if (reg & 0x80000000) |
||||
break; |
||||
} |
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */ |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int pci_pre_init(struct pci_controller * hose ) |
||||
{ |
||||
unsigned long strap; |
||||
/* See if we're supposed to setup the pci */ |
||||
mfsdr(sdr_sdstp1, strap); |
||||
if ((strap & 0x00010000) == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) |
||||
/* Setup System Device Register PCIX0_XCR */ |
||||
mfsdr(sdr_xcr, strap); |
||||
strap &= 0x0f000000; |
||||
mtsdr(sdr_xcr, strap); |
||||
#endif |
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller * hose ) |
||||
{ |
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */ |
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
||||
* options to not support sizes such as 128/256 MB. |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); |
||||
out32r( PCIX0_PIM0LAH, 0 ); |
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
||||
|
||||
out32r( PCIX0_BAR0, 0 ); |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id |
||||
*--------------------------------------------------------------------------*/ |
||||
out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); |
||||
out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); |
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
|
||||
return (ctrlc()); |
||||
} |
||||
|
||||
void post_word_store (ulong a) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); |
||||
|
||||
*save_addr = a; |
||||
} |
||||
|
||||
ulong post_word_load (void) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); |
||||
|
||||
return *save_addr; |
||||
} |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
static int read_i2c; |
||||
static void board_get_enetaddr(uchar *enet) |
||||
{ |
||||
int i; |
||||
unsigned char buff[0x100], *cp; |
||||
|
||||
if (read_i2c) |
||||
return; |
||||
|
||||
/* Initialize I2C */ |
||||
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
|
||||
/* Read 256 bytes in EEPROM */ |
||||
i2c_read (0x50, 0, 1, buff, 0x100); |
||||
|
||||
cp = &buff[0xF4]; |
||||
for (i = 0; i < 6; i++,cp++) |
||||
enet[i] = *cp; |
||||
|
||||
printf("MAC address = %pM\n", enet); |
||||
read_i2c = 1; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
uchar enetaddr[6], i2c_enetaddr[6]; |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { |
||||
board_get_enetaddr(i2c_enetaddr); |
||||
eth_setenv_enetaddr("ethaddr", i2c_enetaddr); |
||||
} |
||||
|
||||
#ifdef CONFIG_HAS_ETH1 |
||||
if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { |
||||
board_get_enetaddr(i2c_enetaddr); |
||||
eth_setenv_enetaddr("eth1addr", i2c_enetaddr); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HAS_ETH2 |
||||
if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { |
||||
board_get_enetaddr(i2c_enetaddr); |
||||
eth_setenv_enetaddr("eth2addr", i2c_enetaddr); |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HAS_ETH3 |
||||
if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { |
||||
board_get_enetaddr(i2c_enetaddr); |
||||
eth_setenv_enetaddr("eth3addr", i2c_enetaddr); |
||||
} |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,142 @@ |
||||
/*
|
||||
* (C) Copyright 2008-2009 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2009 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <i2c.h> |
||||
#include <asm/ppc4xx_config.h> |
||||
#include <asm/io.h> |
||||
|
||||
static void print_configs(int cur_config_nr) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < ppc4xx_config_count; i++) { |
||||
printf("%-16s - %s", ppc4xx_config_val[i].label, |
||||
ppc4xx_config_val[i].description); |
||||
if (i == cur_config_nr) |
||||
printf(" ***"); |
||||
printf("\n"); |
||||
} |
||||
|
||||
} |
||||
|
||||
static int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
int i; |
||||
int ret; |
||||
int cur_config_nr = -1; |
||||
u8 cur_config[CONFIG_4xx_CONFIG_BLOCKSIZE]; |
||||
|
||||
#ifdef CONFIG_CMD_EEPROM |
||||
ret = eeprom_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, |
||||
cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE); |
||||
#else |
||||
ret = i2c_read(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, |
||||
1, cur_config, CONFIG_4xx_CONFIG_BLOCKSIZE); |
||||
#endif |
||||
if (ret) { |
||||
printf("Error reading EEPROM at addr 0x%x\n", |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Search the current configuration |
||||
*/ |
||||
for (i = 0; i < ppc4xx_config_count; i++) { |
||||
if (memcmp(cur_config, ppc4xx_config_val[i].val, |
||||
CONFIG_4xx_CONFIG_BLOCKSIZE) == 0) |
||||
cur_config_nr = i; |
||||
} |
||||
|
||||
if (cur_config_nr == -1) { |
||||
printf("Warning: The I2C bootstrap values don't match any" |
||||
" of the available options!\n"); |
||||
printf("I2C bootstrap EEPROM values are (I2C address 0x%02x):\n", |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); |
||||
for (i = 0; i < CONFIG_4xx_CONFIG_BLOCKSIZE; i++) { |
||||
printf("%02x ", cur_config[i]); |
||||
} |
||||
printf("\n"); |
||||
} |
||||
|
||||
if (argc < 2) { |
||||
printf("Available configurations (I2C address 0x%02x):\n", |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); |
||||
print_configs(cur_config_nr); |
||||
return 0; |
||||
} |
||||
|
||||
for (i = 0; i < ppc4xx_config_count; i++) { |
||||
/*
|
||||
* Search for configuration name/label |
||||
*/ |
||||
if (strcmp(argv[1], ppc4xx_config_val[i].label) == 0) { |
||||
printf("Using configuration:\n%-16s - %s\n", |
||||
ppc4xx_config_val[i].label, |
||||
ppc4xx_config_val[i].description); |
||||
|
||||
#ifdef CONFIG_CMD_EEPROM |
||||
ret = eeprom_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, |
||||
ppc4xx_config_val[i].val, |
||||
CONFIG_4xx_CONFIG_BLOCKSIZE); |
||||
#else |
||||
ret = i2c_write(CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET, |
||||
1, ppc4xx_config_val[i].val, |
||||
CONFIG_4xx_CONFIG_BLOCKSIZE); |
||||
#endif |
||||
udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
||||
if (ret) { |
||||
printf("Error updating EEPROM at addr 0x%x\n", |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR); |
||||
return -1; |
||||
} |
||||
|
||||
printf("done (dump via 'i2c md %x 0.1 %x')\n", |
||||
CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR, |
||||
CONFIG_4xx_CONFIG_BLOCKSIZE); |
||||
printf("Reset the board for the changes to" |
||||
" take effect\n"); |
||||
return 0; |
||||
} |
||||
} |
||||
|
||||
printf("Configuration %s not found!\n", argv[1]); |
||||
print_configs(cur_config_nr); |
||||
return -1; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
chip_config, 2, 0, do_chip_config, |
||||
"program the I2C bootstrap EEPROM", |
||||
"[config-label]" |
||||
); |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* (C) Copyright 2008-2009 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2009 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __PPC4xx_CONFIG_H |
||||
#define __PPC4xx_CONFIG_H |
||||
|
||||
#include <common.h> |
||||
|
||||
struct ppc4xx_config { |
||||
char label[16]; |
||||
char description[64]; |
||||
u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE]; |
||||
}; |
||||
|
||||
extern struct ppc4xx_config ppc4xx_config_val[]; |
||||
extern int ppc4xx_config_count; |
||||
|
||||
#endif /* __PPC4xx_CONFIG_H */ |
||||
@ -0,0 +1,378 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_405EP 1 /* This is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#undef CONFIG_BOOTCOMMAND |
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/ |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_HAS_ETH1 |
||||
|
||||
#define CONFIG_PPC4xx_EMAC |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */ |
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_BSP |
||||
#define CONFIG_CMD_CHIP_CONFIG |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
#define CONFIG_PRAM 0 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ |
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK |
||||
#define CONFIG_SYS_BASE_BAUD 691200 |
||||
#define CONFIG_UART1_CONSOLE |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{ 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED 1 |
||||
#define CONFIG_AUTOBOOT_PROMPT \ |
||||
"Press SPACE to abort autoboot in %d seconds\n", bootdelay |
||||
#undef CONFIG_AUTOBOOT_DELAY_STR |
||||
#define CONFIG_AUTOBOOT_STOP_STR " " |
||||
|
||||
/*
|
||||
* PCI stuff |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
/*
|
||||
* PCI identification |
||||
*/ |
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH |
||||
#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */ |
||||
#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC |
||||
#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST |
||||
|
||||
#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH |
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH |
||||
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */ |
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */ |
||||
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ |
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
||||
/*
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */ |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
||||
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0xfe000000 |
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) |
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
||||
|
||||
/*
|
||||
* Environment in EEPROM setup |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 |
||||
#define CONFIG_ENV_OFFSET 0x100 |
||||
#define CONFIG_ENV_SIZE 0x700 |
||||
|
||||
/*
|
||||
* I2C EEPROM (24W16) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CONFIG_SYS_EEPROM_WREN 1 |
||||
|
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40 |
||||
#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20 |
||||
|
||||
/*
|
||||
* RTC |
||||
*/ |
||||
#define CONFIG_RTC_RX8025 |
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup |
||||
* (max. 55MHZ EBC clock) |
||||
*/ |
||||
/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x03017200 |
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000) |
||||
|
||||
/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */ |
||||
#define CONFIG_SYS_CPLD_BASE 0xef000000 |
||||
#define CONFIG_SYS_EBC_PB1AP 0x00800000 |
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000) |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
/* inside SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
||||
/* End of used area in RAM */ |
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes res. for initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ |
||||
CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* GPIO Configuration |
||||
*/ |
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \ |
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
||||
} \
|
||||
} |
||||
|
||||
#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */ |
||||
#define CONFIG_SYS_GPIO_HWREV_SHIFT 27 |
||||
#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */ |
||||
#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */ |
||||
#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */ |
||||
#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */ |
||||
#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */ |
||||
#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */ |
||||
#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */ |
||||
#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */ |
||||
|
||||
/*
|
||||
* Default speed selection (cpu_plb_opb_ebc) in mhz. |
||||
* This value will be set if iic boot eprom is disabled. |
||||
*/ |
||||
#undef CONFIG_SYS_FCPU333MHZ |
||||
#define CONFIG_SYS_FCPU266MHZ |
||||
#undef CONFIG_SYS_FCPU133MHZ |
||||
|
||||
#if defined(CONFIG_SYS_FCPU333MHZ) |
||||
/*
|
||||
* CPU: 333MHz |
||||
* PLB/SDRAM/MAL: 111MHz |
||||
* OPB: 55MHz |
||||
* EBC: 55MHz |
||||
* PCI: 55MHz (111MHz on M66EN=1) |
||||
*/ |
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2) |
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \ |
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_FCPU266MHZ) |
||||
/*
|
||||
* CPU: 266MHz |
||||
* PLB/SDRAM/MAL: 133MHz |
||||
* OPB: 66MHz |
||||
* EBC: 44MHz |
||||
* PCI: 44MHz (66MHz on M66EN=1) |
||||
*/ |
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3) |
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \ |
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
||||
#endif |
||||
|
||||
#if defined(CONFIG_SYS_FCPU133MHZ) |
||||
/*
|
||||
* CPU: 133MHz |
||||
* PLB/SDRAM/MAL: 133MHz |
||||
* OPB: 66MHz |
||||
* EBC: 44MHz |
||||
* PCI: 44MHz (66MHz on M66EN=1) |
||||
*/ |
||||
#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3) |
||||
#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \ |
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,356 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* config for XPedite1000 from XES Inc. |
||||
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> |
||||
* (C) Copyright 2003 Sandburst Corporation |
||||
* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_XPEDITE1000 1 |
||||
#define CONFIG_SYS_BOARD_NAME "XPedite1000" |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_440 1 |
||||
#define CONFIG_440GX 1 /* 440 GX */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
/*
|
||||
* DDR config |
||||
*/ |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ |
||||
#define CONFIG_VERY_BIG_RAM 1 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ |
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) |
||||
#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) |
||||
|
||||
/*
|
||||
* Diagnostics |
||||
*/ |
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ |
||||
CONFIG_SYS_POST_I2C) |
||||
|
||||
/*
|
||||
* LED support |
||||
*/ |
||||
#define USR_LED0 0x00000080 |
||||
#define USR_LED1 0x00000100 |
||||
#define USR_LED2 0x00000200 |
||||
#define USR_LED3 0x00000400 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long in32(unsigned int); |
||||
extern void out32(unsigned int, unsigned long); |
||||
|
||||
#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0)) |
||||
#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1)) |
||||
#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2)) |
||||
#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3)) |
||||
|
||||
#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0)) |
||||
#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1)) |
||||
#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2)) |
||||
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) |
||||
#endif |
||||
|
||||
/*
|
||||
* Use internal SRAM for initial stack |
||||
*/ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Use the HUSH parser |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/*
|
||||
* NOR flash configuration |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3 |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 } |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST /* MirrorBit flashes are optional */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7f |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
|
||||
/* I2C EEPROM */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/* I2C RTC: STMicro M41T00 */ |
||||
#define CONFIG_RTC_M41T11 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000 |
||||
|
||||
/*
|
||||
* PCI |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ |
||||
|
||||
/*
|
||||
* Networking options |
||||
*/ |
||||
#define CONFIG_PPC4xx_EMAC |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
#define CONFIG_ETHPRIME "ppc_4xx_eth2" |
||||
#define CONFIG_PHY_ADDR 4 /* PHY address phy0 not populated */ |
||||
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ |
||||
#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ |
||||
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ |
||||
#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ |
||||
|
||||
/* BOOTP options */ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command configuration |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVEENV |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
#define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ |
||||
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
#define CONFIG_PREBOOT /* enable preboot variable */ |
||||
#define CONFIG_FIT 1 |
||||
#define CONFIG_FIT_VERBOSE 1 |
||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ |
||||
#define CONFIG_ENV_SIZE 0x8000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) |
||||
|
||||
/*
|
||||
* Flash memory map: |
||||
* fff80000 - ffffffff U-Boot (512 KB) |
||||
* fff40000 - fff7ffff U-Boot Environment (256 KB) |
||||
* fff00000 - fff3ffff FDT (256KB) |
||||
* ffc00000 - ffefffff OS image (3MB) |
||||
* ff000000 - ffbfffff OS Use/Filesystem (12MB) |
||||
*/ |
||||
|
||||
#define CONFIG_UBOOT_ENV_ADDR MK_STR(TEXT_BASE) |
||||
#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000) |
||||
#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000) |
||||
|
||||
#define CONFIG_PROG_UBOOT \ |
||||
"$download_cmd $loadaddr $ubootfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"protect off "CONFIG_UBOOT_ENV_ADDR" +80000; " \
|
||||
"erase "CONFIG_UBOOT_ENV_ADDR" +80000; " \
|
||||
"cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; " \
|
||||
"protect on "CONFIG_UBOOT_ENV_ADDR" +80000; " \
|
||||
"cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo DOWNLOAD FAILED; " \
|
||||
"fi;" |
||||
|
||||
#define CONFIG_BOOT_OS_NET \ |
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"if test -n $fdtaddr; then " \
|
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"bootm $osaddr - $fdtaddr; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"bootm $osaddr; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;" |
||||
|
||||
#define CONFIG_PROG_OS \ |
||||
"$download_cmd $osaddr $osfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_OS_ENV_ADDR" +$filesize; " \
|
||||
"cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo OS PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo OS PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo OS DOWNLOAD FAILED; " \
|
||||
"fi;" |
||||
|
||||
#define CONFIG_PROG_FDT \ |
||||
"$download_cmd $fdtaddr $fdtfile; " \
|
||||
"if test $? -eq 0; then " \
|
||||
"erase "CONFIG_FDT_ENV_ADDR" +$filesize;" \
|
||||
"cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
|
||||
"cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; " \
|
||||
"if test $? -ne 0; then " \
|
||||
"echo FDT PROGRAM FAILED; " \
|
||||
"else; " \
|
||||
"echo FDT PROGRAM SUCCEEDED; " \
|
||||
"fi; " \
|
||||
"else; " \
|
||||
"echo FDT DOWNLOAD FAILED; " \
|
||||
"fi;" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"autoload=yes\0" \
|
||||
"download_cmd=tftp\0" \
|
||||
"console_args=console=ttyS0,115200\0" \
|
||||
"root_args=root=/dev/nfs rw\0" \
|
||||
"misc_args=ip=on\0" \
|
||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
||||
"bootfile=/home/user/file\0" \
|
||||
"osfile=/home/user/uImage-XPedite1000\0" \
|
||||
"fdtfile=/home/user/xpedite1000.dtb\0" \
|
||||
"ubootfile=/home/user/u-boot.bin\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"osaddr=0x1000000\0" \
|
||||
"loadaddr=0x1000000\0" \
|
||||
"prog_uboot="CONFIG_PROG_UBOOT"\0" \
|
||||
"prog_os="CONFIG_PROG_OS"\0" \
|
||||
"prog_fdt="CONFIG_PROG_FDT"\0" \
|
||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
||||
"bootcmd_flash=run set_bootargs; " \
|
||||
"bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0" \
|
||||
"bootcmd=run bootcmd_flash\0" |
||||
#endif /* __CONFIG_H */ |
||||
@ -1,274 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* config for XPedite1000 from XES Inc. |
||||
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> |
||||
* (C) Copyright 2003 Sandburst Corporation |
||||
* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_440 1 |
||||
#define CONFIG_440GX 1 /* 440 GX */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CONFIG_SYS_POST_RTC | \ |
||||
CONFIG_SYS_POST_I2C) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */ |
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) |
||||
#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700) |
||||
|
||||
#define USR_LED0 0x00000080 |
||||
#define USR_LED1 0x00000100 |
||||
#define USR_LED2 0x00000200 |
||||
#define USR_LED3 0x00000400 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long in32(unsigned int); |
||||
extern void out32(unsigned int, unsigned long); |
||||
|
||||
#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0)) |
||||
#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1)) |
||||
#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2)) |
||||
#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3)) |
||||
|
||||
#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0)) |
||||
#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1)) |
||||
#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2)) |
||||
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3)) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC |
||||
* |
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base |
||||
* address for the RTC registers is: |
||||
* |
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE |
||||
* |
||||
*----------------------------------------------------------------------*/ |
||||
/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ |
||||
#define CONFIG_RTC_M41T11 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */ |
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ |
||||
#define CONFIG_VERY_BIG_RAM 1 |
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7f |
||||
#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 |
||||
#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */ |
||||
#define CONFIG_ENV_OFFSET 0x100 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " |
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
||||
#define CONFIG_BOOTDELAY 5 /* disable autoboot */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_PPC4xx_EMAC |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ |
||||
#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ |
||||
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ |
||||
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ |
||||
#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_BEDBUG |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_FAT |
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ |
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,225 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* member of PPC4xx family */ |
||||
#define CONFIG_DLVISION 1 /* on a Neo board */ |
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards |
||||
*/ |
||||
#define CONFIG_HOSTNAME dlvision |
||||
#define CONFIG_IDENT_STRING " dlvision 0.01" |
||||
#include "amcc-common.h" |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R /* call misc_init_r */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
||||
|
||||
/*
|
||||
* Configure PLL |
||||
*/ |
||||
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
||||
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"fdt_addr=fc1e0000\0" \
|
||||
"ramdisk_addr=fc200000\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_PHY_ADDR 4 /* PHY address */ |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ |
||||
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ |
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h |
||||
*/ |
||||
#define CONFIG_CMD_CACHE |
||||
#undef CONFIG_CMD_EEPROM |
||||
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
||||
*/ |
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
|
||||
/* SDRAM timings used in datasheet */ |
||||
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ |
||||
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ |
||||
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ |
||||
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
||||
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ |
||||
|
||||
/*
|
||||
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
||||
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
||||
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. |
||||
* The Linux BASE_BAUD define should match this configuration. |
||||
* baseBaud = cpuClock/(uartDivisor*16) |
||||
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
||||
* set Linux BASE_BAUD to 403200. |
||||
*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CONFIG_SYS_BASE_BAUD 691200 |
||||
|
||||
/*
|
||||
* I2C stuff |
||||
*/ |
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address*/ |
||||
|
||||
/*
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFC000000 |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ |
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*
|
||||
* PPC405 GPIO Configuration |
||||
*/ |
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ |
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
||||
} \
|
||||
} |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480 |
||||
/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ |
||||
#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 |
||||
|
||||
/* Memory Bank 1 (NVRAM) initializatio */ |
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480 |
||||
/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ |
||||
#define CONFIG_SYS_EBC_PB1CR 0xFB858000 |
||||
|
||||
/* Memory Bank 2 (UART) initialization */ |
||||
#define CONFIG_UART_BASE 0x7f100000 |
||||
#define CONFIG_SYS_EBC_PB2AP 0x92015480 |
||||
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */ |
||||
#define CONFIG_SYS_EBC_PB2CR 0x7f118000 |
||||
|
||||
/* Memory Bank 3 (Latches) initialization */ |
||||
#define CONFIG_SYS_LATCH_BASE 0x7f200000 |
||||
#define CONFIG_SYS_EBC_PB3AP 0x92015480 |
||||
/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ |
||||
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue