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@ -40,4 +40,31 @@ |
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#define TCNT0 0xFFD8000C |
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#define TCR0 0xFFD80010 |
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/* PFC */ |
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#define PMMR (0xFFFC0000) |
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#define MODESEL0 (0xFFFC004C) |
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#define MODESEL2 (MODESEL0 + 0x4) |
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#define MODESEL2_INIT (0x00003000) |
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#define IPSR0 (0xFFFC001C) |
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#define IPSR1 (IPSR0 + 0x4) |
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#define IPSR2 (IPSR0 + 0x8) |
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#define IPSR3 (IPSR0 + 0xC) |
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#define IPSR4 (IPSR0 + 0x10) |
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#define IPSR5 (IPSR0 + 0x14) |
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#define IPSR6 (IPSR0 + 0x18) |
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#define IPSR7 (IPSR0 + 0x1C) |
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#define IPSR8 (IPSR0 + 0x20) |
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#define IPSR9 (IPSR0 + 0x24) |
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#define IPSR10 (IPSR0 + 0x28) |
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#define IPSR11 (IPSR0 + 0x2C) |
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#define GPSR0 (0xFFFC0004) |
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#define GPSR1 (GPSR0 + 0x4) |
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#define GPSR2 (GPSR0 + 0x8) |
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#define GPSR3 (GPSR0 + 0xC) |
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#define GPSR4 (GPSR0 + 0x10) |
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#define GPSR5 (GPSR0 + 0x14) |
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#endif /* _ASM_CPU_SH7734_H_ */ |
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