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mpc83xx: USB: Reorganized its support

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The following patch reorganizes/reworks the USB support for mpc83xx
as under:-

  * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
    cpu/mpx83xx/cpu_init.c

  * Board specific usb_phy_type is read from the environment

  * Adds USB EHCI specific structure in include/usb/ehci-fsl.h

  * Copyrights revamped in most of the following files

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
master
Vivek Mahajan 15 years ago committed by Wolfgang Denk
parent ed90d2c871
commit 4ef01010aa
4 changed files with 102 additions and 38 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 19
      cpu/mpc83xx/cpu_init.c
  2. 53
      drivers/usb/host/ehci-fsl.c
  3. 5
      include/asm-ppc/immap_83xx.h
  4. 63
      include/usb/ehci-fsl.h

19
cpu/mpc83xx/cpu_init.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -23,6 +23,10 @@
#include <common.h>
#include <mpc83xx.h>
#include <ioports.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <asm/io.h>
#include <usb/ehci-fsl.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im)
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
#ifdef CONFIG_USB_EHCI_FSL
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
/* Configure interface. */
setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
/* Wait for clock to stabilize */
do {
temp = in_be32((void *)ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
}
int cpu_init_r (void)

53
drivers/usb/host/ehci-fsl.c
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@ -1,4 +1,6 @@
/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
*
* Author: Tor Krill tor@excito.com
@ -22,12 +24,10 @@
#include <common.h>
#include <pci.h>
#include <usb.h>
#include <mpc83xx.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <usb/ehci-fsl.h>
#include "ehci.h"
#include <usb/ehci-fsl.h>
#include "ehci-core.h"
/*
@ -38,50 +38,33 @@
*/
int ehci_hcd_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
uint32_t addr, temp;
struct usb_ehci *ehci;
addr = (uint32_t)&(im->usb[0]);
hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
/* Configure clock */
clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
MPC83XX_SCCR_USB_DRCM_11);
/* Confgure interface. */
temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp
| REFSEL_16MHZ | UTMI_PHY_EN);
/* Wait for clock to stabilize */
do {
temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
/* Set to Host mode */
temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST);
setbits_le32((void *)ehci->usbmode, CM_HOST);
out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB);
out_be32((void *)(addr + FSL_SOC_USB_SNOOP2),
0x80000000 | SNOOP_SIZE_2GB);
out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB);
out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
/* TODO: handle different phys? */
out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
if (!strcmp(getenv("usb_phy_type"), "utmi"))
out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
else
out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
/* Enable interface. */
temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN);
setbits_be32((void *)ehci->control, USB_EN);
out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c);
out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040);
out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001);
out_be32((void *)ehci->prictrl, 0x0000000c);
out_be32((void *)ehci->age_cnt_limit, 0x00000040);
out_be32((void *)ehci->sictrl, 0x00000001);
temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
in_le32((void *)ehci->usbmode);
return 0;
}

5
include/asm-ppc/immap_83xx.h
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@ -1,5 +1,5 @@
/*
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
@ -897,4 +897,7 @@ typedef struct immap {
#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#endif /* __IMMAP_83xx__ */

63
include/usb/ehci-fsl.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2005 freescale semiconductor
* Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
* Copyright (c) 2005 MontaVista Software
* Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
*
@ -22,6 +22,8 @@
#ifndef _EHCI_FSL_H
#define _EHCI_FSL_H
#include <asm/processor.h>
/* Global offsets */
#define FSL_SKIP_PCI 0x100
@ -83,4 +85,63 @@
#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
#if defined(CONFIG_MPC83XX)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
#endif
/*
* USB Registers
*/
struct usb_ehci {
u8 res1[0x100];
u16 caplength; /* 0x100 - Capability Register Length */
u16 hciversion; /* 0x102 - Host Interface Version */
u32 hcsparams; /* 0x104 - Host Structural Parameters */
u32 hccparams; /* 0x108 - Host Capability Parameters */
u8 res2[0x14];
u32 dciversion; /* 0x120 - Device Interface Version */
u32 dciparams; /* 0x124 - Device Controller Params */
u8 res3[0x18];
u32 usbcmd; /* 0x140 - USB Command */
u32 usbsts; /* 0x144 - USB Status */
u32 usbintr; /* 0x148 - USB Interrupt Enable */
u32 frindex; /* 0x14C - USB Frame Index */
u8 res4[0x4];
u32 perlistbase; /* 0x154 - Periodic List Base
- USB Device Address */
u32 ep_list_addr; /* 0x158 - Next Asynchronous List
- End Point Address */
u8 res5[0x4];
u32 burstsize; /* 0x160 - Programmable Burst Size */
u32 txfilltuning; /* 0x164 - Host TT Transmit
pre-buffer packet tuning */
u8 res6[0x8];
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
u8 res7[0xc];
u32 config_flag; /* 0x180 - Configured Flag Register */
u32 portsc; /* 0x184 - Port status/control */
u8 res8[0x20];
u32 usbmode; /* 0x1a8 - USB Device Mode */
u32 epsetupstat; /* 0x1ac - End Point Setup Status */
u32 epprime; /* 0x1b0 - End Point Init Status */
u32 epflush; /* 0x1b4 - End Point De-initlialize */
u32 epstatus; /* 0x1b8 - End Point Status */
u32 epcomplete; /* 0x1bc - End Point Complete */
u32 epctrl0; /* 0x1c0 - End Point Control 0 */
u32 epctrl1; /* 0x1c4 - End Point Control 1 */
u32 epctrl2; /* 0x1c8 - End Point Control 2 */
u32 epctrl3; /* 0x1cc - End Point Control 3 */
u32 epctrl4; /* 0x1d0 - End Point Control 4 */
u32 epctrl5; /* 0x1d4 - End Point Control 5 */
u8 res9[0x228];
u32 snoop1; /* 0x400 - Snoop 1 */
u32 snoop2; /* 0x404 - Snoop 2 */
u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
u32 prictrl; /* 0x40c - Priority Control */
u32 sictrl; /* 0x410 - System Interface Control */
u8 res10[0xEC];
u32 control; /* 0x500 - Control */
u8 res11[0xafc];
};
#endif /* _EHCI_FSL_H */

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