commit
4f58002013
@ -1,12 +0,0 @@ |
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if TARGET_MPC8540ADS |
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|
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config SYS_BOARD |
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default "mpc8540ads" |
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|
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config SYS_VENDOR |
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default "freescale" |
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|
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config SYS_CONFIG_NAME |
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default "MPC8540ADS" |
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|
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endif |
@ -1,6 +0,0 @@ |
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MPC8540ADS BOARD |
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#M: Kumar Gala <kumar.gala@freescale.com> |
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S: Orphan (since 2014-06) |
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F: board/freescale/mpc8540ads/ |
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F: include/configs/MPC8540ADS.h |
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F: configs/MPC8540ADS_defconfig |
@ -1,11 +0,0 @@ |
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#
|
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# (C) Copyright 2001-2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y += mpc8540ads.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -1,44 +0,0 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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|
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#include <fsl_ddr_sdram.h> |
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#include <fsl_ddr_dimm_params.h> |
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|
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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/*
|
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* Factors to consider for CPO: |
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* - frequency |
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* - ddr1 vs. ddr2 |
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*/ |
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popts->cpo_override = 0; |
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|
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/*
|
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* Factors to consider for write data delay: |
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* - number of DIMMs |
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* |
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* 1 = 1/4 clock delay |
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* 2 = 1/2 clock delay |
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* 3 = 3/4 clock delay |
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* 4 = 1 clock delay |
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* 5 = 5/4 clock delay |
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* 6 = 3/2 clock delay |
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*/ |
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popts->write_data_delay = 3; |
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|
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/* 2T timing enable */ |
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popts->twot_en = 1; |
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|
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/*
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* Factors to consider for half-strength driver enable: |
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* - number of DIMMs installed |
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*/ |
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popts->half_strength_driver_enable = 0; |
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} |
@ -1,42 +0,0 @@ |
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/*
|
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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|
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/*
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xc000_0000 0xdfff_ffff RapidIO 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
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* 0xf800_0000 0xf80f_ffff BCSR 1M |
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* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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*/ |
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|
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struct law_entry law_table[] = { |
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#ifndef CONFIG_SPD_EEPROM |
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
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#endif |
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
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/* This is not so much the SDRAM map as it is the whole localbus map. */ |
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
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SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
@ -1,242 +0,0 @@ |
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/*
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* Copyright 2004 Freescale Semiconductor. |
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* (C) Copyright 2002,2003, Motorola Inc. |
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* Xianghua Xiao, (X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/mmu.h> |
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#include <asm/immap_85xx.h> |
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#include <fsl_ddr_sdram.h> |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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|
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void local_bus_init(void); |
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int checkboard (void) |
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{ |
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puts("Board: ADS\n"); |
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#ifdef CONFIG_PCI |
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printf("PCI1: 32 bit, %d MHz (compiled)\n", |
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CONFIG_SYS_CLK_FREQ / 1000000); |
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#else |
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printf("PCI1: disabled\n"); |
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#endif |
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|
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/*
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* Initialize local bus. |
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*/ |
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local_bus_init(); |
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return 0; |
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} |
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|
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/*
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* Initialize Local Bus |
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*/ |
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void |
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local_bus_init(void) |
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{ |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
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uint clkdiv; |
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uint lbc_hz; |
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sys_info_t sysinfo; |
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/*
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* Errata LBC11. |
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* Fix Local Bus clock glitch when DLL is enabled. |
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* |
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* If localbus freq is < 66MHz, DLL bypass mode must be used. |
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* If localbus freq is > 133MHz, DLL can be safely enabled. |
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* Between 66 and 133, the DLL is enabled with an override workaround. |
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*/ |
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get_sys_info(&sysinfo); |
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clkdiv = lbc->lcrr & LCRR_CLKDIV; |
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lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; |
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if (lbc_hz < 66) { |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
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} else if (lbc_hz >= 133) { |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
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} else { |
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/*
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* On REV1 boards, need to change CLKDIV before enable DLL. |
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* Default CLKDIV is 8, change it to 4 temporarily. |
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*/ |
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uint pvr = get_pvr(); |
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uint temp_lbcdll = 0; |
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if (pvr == PVR_85xx_REV1) { |
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/* FIXME: Justify the high bit here. */ |
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lbc->lcrr = 0x10000004; |
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} |
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lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
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udelay(200); |
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/*
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* Sample LBC DLL ctrl reg, upshift it to set the |
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* override bits. |
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*/ |
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temp_lbcdll = gur->lbcdllcr; |
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gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
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asm("sync;isync;msync"); |
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} |
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} |
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|
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|
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/*
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* Initialize SDRAM memory on the Local Bus. |
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*/ |
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void lbc_sdram_init(void) |
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{ |
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
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puts("LBC SDRAM: "); |
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print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, |
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"\n "); |
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/*
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* Setup SDRAM Base and Option Registers |
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*/ |
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); |
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); |
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lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
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asm("msync"); |
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lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
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asm("sync"); |
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/*
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* Configure the SDRAM controller. |
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*/ |
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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ppcDcbf((unsigned long) sdram_addr); |
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udelay(100); |
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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ppcDcbf((unsigned long) sdram_addr); |
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udelay(100); |
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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ppcDcbf((unsigned long) sdram_addr); |
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udelay(100); |
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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ppcDcbf((unsigned long) sdram_addr); |
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udelay(100); |
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; |
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asm("sync"); |
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*sdram_addr = 0xff; |
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ppcDcbf((unsigned long) sdram_addr); |
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udelay(100); |
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} |
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|
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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phys_size_t fixed_sdram(void) |
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{ |
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#ifndef CONFIG_SYS_RAMBOOT |
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struct ccsr_ddr __iomem *ddr = |
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(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); |
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|
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
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#if defined (CONFIG_DDR_ECC) |
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ddr->err_disable = 0x0000000D; |
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ddr->err_sbe = 0x00ff0000; |
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#endif |
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asm("sync;isync;msync"); |
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udelay(500); |
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#if defined (CONFIG_DDR_ECC) |
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/* Enable ECC checking */ |
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ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
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#else |
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
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#endif |
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asm("sync; isync; msync"); |
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udelay(500); |
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#endif |
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
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} |
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#endif /* !defined(CONFIG_SPD_EEPROM) */ |
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|
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|
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#if defined(CONFIG_PCI) |
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/*
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* Initialize PCI Devices, report devices found. |
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*/ |
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|
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|
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static struct pci_controller hose; |
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|
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#endif /* CONFIG_PCI */ |
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|
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|
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void |
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pci_init_board(void) |
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{ |
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#ifdef CONFIG_PCI |
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pci_mpc85xx_init(&hose); |
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#endif /* CONFIG_PCI */ |
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} |
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|
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|
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#if defined(CONFIG_OF_BOARD_SETUP) |
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int ft_board_setup(void *blob, bd_t *bd) |
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{ |
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int node, tmp[2]; |
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const char *path; |
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|
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ft_cpu_setup(blob, bd); |
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|
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node = fdt_path_offset(blob, "/aliases"); |
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tmp[0] = 0; |
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if (node >= 0) { |
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#ifdef CONFIG_PCI |
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path = fdt_getprop(blob, node, "pci0", NULL); |
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if (path) { |
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tmp[1] = hose.last_busno - hose.first_busno; |
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do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
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} |
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#endif |
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} |
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|
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return 0; |
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} |
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#endif |
@ -1,95 +0,0 @@ |
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/*
|
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* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
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#include <common.h> |
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#include <asm/mmu.h> |
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|
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struct fsl_e_tlb_entry tlb_table[] = { |
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/* TLB 0 - for temp stack in cache */ |
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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|
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/*
|
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* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
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* Out of reset this entry is only 4K. |
||||
*/ |
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
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/*
|
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* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
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/*
|
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* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
@ -1,12 +0,0 @@ |
||||
if TARGET_MPC8560ADS |
||||
|
||||
config SYS_BOARD |
||||
default "mpc8560ads" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "MPC8560ADS" |
||||
|
||||
endif |
@ -1,6 +0,0 @@ |
||||
MPC8560ADS BOARD |
||||
#M: Kumar Gala <kumar.gala@freescale.com> |
||||
S: Orphan (since 2014-06) |
||||
F: board/freescale/mpc8560ads/ |
||||
F: include/configs/MPC8560ADS.h |
||||
F: configs/MPC8560ADS_defconfig |
@ -1,11 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += mpc8560ads.o
|
||||
obj-y += ddr.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
@ -1,44 +0,0 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
/*
|
||||
* Factors to consider for CPO: |
||||
* - frequency |
||||
* - ddr1 vs. ddr2 |
||||
*/ |
||||
popts->cpo_override = 0; |
||||
|
||||
/*
|
||||
* Factors to consider for write data delay: |
||||
* - number of DIMMs |
||||
* |
||||
* 1 = 1/4 clock delay |
||||
* 2 = 1/2 clock delay |
||||
* 3 = 3/4 clock delay |
||||
* 4 = 1 clock delay |
||||
* 5 = 5/4 clock delay |
||||
* 6 = 3/2 clock delay |
||||
*/ |
||||
popts->write_data_delay = 3; |
||||
|
||||
/* 2T timing enable */ |
||||
popts->twot_en = 1; |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
} |
@ -1,42 +0,0 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
@ -1,462 +0,0 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <ioports.h> |
||||
#include <spd_sdram.h> |
||||
#include <miiphy.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_lbc.h> |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
extern void ddr_enable_ecc(unsigned int dram_size); |
||||
#endif |
||||
|
||||
|
||||
void local_bus_init(void); |
||||
|
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
||||
/* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
||||
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
||||
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ |
||||
/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ |
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
|
||||
/*
|
||||
* MPC8560ADS Board Status & Control Registers |
||||
*/ |
||||
typedef struct bcsr_ { |
||||
volatile unsigned char bcsr0; |
||||
volatile unsigned char bcsr1; |
||||
volatile unsigned char bcsr2; |
||||
volatile unsigned char bcsr3; |
||||
volatile unsigned char bcsr4; |
||||
volatile unsigned char bcsr5; |
||||
} bcsr_t; |
||||
|
||||
void reset_phy (void) |
||||
{ |
||||
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ |
||||
volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; |
||||
#endif |
||||
/* reset Giga bit Ethernet port if needed here */ |
||||
|
||||
/* reset the CPM FEC port */ |
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
bcsr->bcsr2 &= ~FETH2_RST; |
||||
udelay(2); |
||||
bcsr->bcsr2 |= FETH2_RST; |
||||
udelay(1000); |
||||
#elif (CONFIG_ETHER_INDEX == 3) |
||||
bcsr->bcsr3 &= ~FETH3_RST; |
||||
udelay(2); |
||||
bcsr->bcsr3 |= FETH3_RST; |
||||
udelay(1000); |
||||
#endif |
||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) |
||||
/* reset PHY */ |
||||
miiphy_reset("FCC1", 0x0); |
||||
|
||||
/* change PHY address to 0x02 */ |
||||
bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); |
||||
|
||||
bb_miiphy_write(NULL, 0x02, MII_BMCR, |
||||
BMCR_ANENABLE | BMCR_ANRESTART); |
||||
#endif /* CONFIG_MII */ |
||||
} |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts("Board: ADS\n"); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
printf("PCI1: 32 bit, %d MHz (compiled)\n", |
||||
CONFIG_SYS_CLK_FREQ / 1000000); |
||||
#else |
||||
printf("PCI1: disabled\n"); |
||||
#endif |
||||
|
||||
/*
|
||||
* Initialize local bus. |
||||
*/ |
||||
local_bus_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
|
||||
void |
||||
local_bus_init(void) |
||||
{ |
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
||||
|
||||
uint clkdiv; |
||||
uint lbc_hz; |
||||
sys_info_t sysinfo; |
||||
|
||||
/*
|
||||
* Errata LBC11. |
||||
* Fix Local Bus clock glitch when DLL is enabled. |
||||
* |
||||
* If localbus freq is < 66MHz, DLL bypass mode must be used. |
||||
* If localbus freq is > 133MHz, DLL can be safely enabled. |
||||
* Between 66 and 133, the DLL is enabled with an override workaround. |
||||
*/ |
||||
|
||||
get_sys_info(&sysinfo); |
||||
clkdiv = lbc->lcrr & LCRR_CLKDIV; |
||||
lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; |
||||
|
||||
if (lbc_hz < 66) { |
||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ |
||||
|
||||
} else if (lbc_hz >= 133) { |
||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ |
||||
|
||||
} else { |
||||
/*
|
||||
* On REV1 boards, need to change CLKDIV before enable DLL. |
||||
* Default CLKDIV is 8, change it to 4 temporarily. |
||||
*/ |
||||
uint pvr = get_pvr(); |
||||
uint temp_lbcdll = 0; |
||||
|
||||
if (pvr == PVR_85xx_REV1) { |
||||
/* FIXME: Justify the high bit here. */ |
||||
lbc->lcrr = 0x10000004; |
||||
} |
||||
|
||||
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */ |
||||
udelay(200); |
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the |
||||
* override bits. |
||||
*/ |
||||
temp_lbcdll = gur->lbcdllcr; |
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); |
||||
asm("sync;isync;msync"); |
||||
} |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
void lbc_sdram_init(void) |
||||
{ |
||||
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
||||
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; |
||||
|
||||
puts("LBC SDRAM: "); |
||||
print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, |
||||
"\n "); |
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers |
||||
*/ |
||||
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); |
||||
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); |
||||
lbc->lbcr = CONFIG_SYS_LBC_LBCR; |
||||
asm("msync"); |
||||
|
||||
lbc->lsrt = CONFIG_SYS_LBC_LSRT; |
||||
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; |
||||
asm("sync"); |
||||
|
||||
/*
|
||||
* Configure the SDRAM controller. |
||||
*/ |
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; |
||||
asm("sync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
} |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
phys_size_t fixed_sdram(void) |
||||
{ |
||||
#ifndef CONFIG_SYS_RAMBOOT |
||||
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); |
||||
|
||||
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
||||
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
||||
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
||||
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
||||
ddr->sdram_mode = CONFIG_SYS_DDR_MODE; |
||||
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
||||
#if defined (CONFIG_DDR_ECC) |
||||
ddr->err_disable = 0x0000000D; |
||||
ddr->err_sbe = 0x00ff0000; |
||||
#endif |
||||
asm("sync;isync;msync"); |
||||
udelay(500); |
||||
#if defined (CONFIG_DDR_ECC) |
||||
/* Enable ECC checking */ |
||||
ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); |
||||
#else |
||||
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
||||
#endif |
||||
asm("sync; isync; msync"); |
||||
udelay(500); |
||||
#endif |
||||
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
|
||||
#if defined(CONFIG_PCI) |
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc85xxads_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
||||
} }, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
|
||||
static struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_mpc85xxads_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
pci_mpc85xx_init(&hose); |
||||
#endif /* CONFIG_PCI */ |
||||
} |
||||
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP) |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
int node, tmp[2]; |
||||
const char *path; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
node = fdt_path_offset(blob, "/aliases"); |
||||
tmp[0] = 0; |
||||
if (node >= 0) { |
||||
#ifdef CONFIG_PCI |
||||
path = fdt_getprop(blob, node, "pci0", NULL); |
||||
if (path) { |
||||
tmp[1] = hose.last_busno - hose.first_busno; |
||||
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); |
||||
} |
||||
#endif |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
@ -1,95 +0,0 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
@ -1,15 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
# CONFIG_CMD_ERRATA is not set |
||||
CONFIG_TARGET_MPC8540ADS=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_PING=y |
||||
# CONFIG_CMD_HASH is not set |
||||
# CONFIG_MMC is not set |
||||
CONFIG_MTD_NOR_FLASH=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_OF_LIBFDT=y |
@ -1,14 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
# CONFIG_CMD_ERRATA is not set |
||||
CONFIG_TARGET_MPC8560ADS=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_PING=y |
||||
# CONFIG_CMD_HASH is not set |
||||
# CONFIG_MMC is not set |
||||
CONFIG_MTD_NOR_FLASH=y |
||||
CONFIG_OF_LIBFDT=y |
@ -1,301 +0,0 @@ |
||||
Motorola MPC8540ADS and MPC8560ADS board |
||||
|
||||
Created 10/15/03 Xianghua Xiao |
||||
Updated 13-July-2004 Jon Loeliger |
||||
----------------------------------------- |
||||
|
||||
0. Toolchain |
||||
|
||||
The Binutils in current ELDK toolchain will not support MPC85xx |
||||
chip. You need to use binutils-2.14.tar.bz2 (or newer) from |
||||
http://ftp.gnu.org/gnu/binutils. |
||||
|
||||
The 8540/8560 ADS code base is known to compile using: |
||||
gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) |
||||
|
||||
|
||||
1. SWITCH SETTINGS & JUMPERS |
||||
|
||||
1.0 Nomenclature |
||||
|
||||
For some reason, the HW designers describe the switch settings |
||||
in terms of 0 and 1, and then map that to physical switches where |
||||
the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1. |
||||
Luckily, we're SW types and virtual settings are handled daily. |
||||
|
||||
The switches for the Rev A board are numbered differently than |
||||
for the Pilot board. Oh yeah. |
||||
|
||||
Switch bits are numbered 1 through, like, 4 6 8 or 10, but the |
||||
bits may contribute to signals that are numbered based at 0, |
||||
and some of those signals may be high-bit-number-0 too. Heed |
||||
well the names and labels and do not get confused. |
||||
|
||||
"Off" == 1 |
||||
"On" == 0 |
||||
|
||||
SW18 is switch 18 as silk-screened onto the board. |
||||
SW4[8] is the bit labeled 8 on Switch 4. |
||||
SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2 |
||||
SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3 |
||||
|
||||
1.1 For the MPC85xxADS Pilot Board |
||||
|
||||
First, make sure the board default setting is consistent with the document |
||||
shipped with your board. Then apply the following changes: |
||||
SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used) |
||||
SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560) |
||||
SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode) |
||||
SW11[7]='ON' (rev2), 'OFF' (rev1) |
||||
SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector) |
||||
SW22[1-4]="OFF OFF ON OFF" |
||||
SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF" |
||||
J1 = "Enable Prog" (Make sure your flash is programmable for development) |
||||
|
||||
If you want to test PCI functionality with a 33Mhz PCI card, you will |
||||
have to change the system clock from the default 66Mhz to 33Mhz by |
||||
setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need |
||||
double your platform clock(SW6) because the system clock is now only |
||||
half of its original value. For example, if at 66MHz your system |
||||
clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10. |
||||
|
||||
SW17[8] ------+ SW6 |
||||
SW15[1] ----+ | [0:1] |
||||
V V V V |
||||
33MHz 1 1 1 0 |
||||
66MHz 0 0 0 1 |
||||
|
||||
Hmmm... That SW6 setting description is incomplete but it works. |
||||
|
||||
|
||||
1.3 For the MPC85xxADS Rev A Board |
||||
|
||||
As shipped, the board should be a 33MHz PCI bus with a CPU Clock |
||||
rate of 825 +/- fuzz: |
||||
|
||||
Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz |
||||
|
||||
For 33MHz PCI, the switch settings should be like this: |
||||
|
||||
SW18[7:1] = 0100001 = M==33 => 33MHz |
||||
SW18[8] = 1 => PWD Divider == 16 |
||||
SW16[1:2] = 11 => N == 16 as PWD==1 |
||||
|
||||
Use the magical formula: |
||||
Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz |
||||
|
||||
SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk |
||||
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock |
||||
|
||||
|
||||
For 66MHz PCI, the switch settings should be like this: |
||||
|
||||
SW18[7:1] = 0100001 = M==33 => 33MHz |
||||
SW18[8] = 0 => PWD Divider == 1 |
||||
SW16[1:2] = 01 => N == 8 as PWD == 0 |
||||
|
||||
Use the magical formula: |
||||
Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz |
||||
|
||||
SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk |
||||
SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock |
||||
|
||||
In order to use PCI-X (only in the first PCI slot. The one with |
||||
the RIO connector), you need to set SW1[4] (config) to 1 (off). |
||||
Also, configure the board to run PCI at 66 MHz. |
||||
|
||||
2. MEMORY MAP TO WORK WITH LINUX KERNEL |
||||
|
||||
2.1. For the initial bringup, we adopted a consistent memory scheme |
||||
between U-Boot and linux kernel, you can customize it based on your |
||||
system requirements: |
||||
|
||||
0x0000_0000 0x7fff_ffff DDR 2G |
||||
0x8000_0000 0x9fff_ffff PCI MEM 512M |
||||
0xc000_0000 0xdfff_ffff Rapid IO 512M |
||||
0xe000_0000 0xe00f_ffff CCSR 1M |
||||
0xe200_0000 0xe2ff_ffff PCI IO 16M |
||||
0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
0xf800_0000 0xf80f_ffff BCSR 1M |
||||
0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
|
||||
2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You |
||||
can download them from linuxppc-2.4 public source. Please make sure the |
||||
kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two |
||||
default configuration files as your starting points to configure the |
||||
kernel: |
||||
arch/powerpc/configs/mpc8540_ads_defconfig |
||||
arch/powerpc/configs/mpc8560_ads_defconfig |
||||
|
||||
3. DEFINITIONS AND COMPILATION |
||||
|
||||
3.1 Explanation on NEW definitions in: |
||||
include/configs/MPC8540ADS.h |
||||
include/configs/MPC8560ADS.h |
||||
|
||||
CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc) |
||||
CONFIG_E500 BOOKE e500 family(Motorola) |
||||
CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives |
||||
CONFIG_ARCH_MPC8540 MPC8540 specific |
||||
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking |
||||
CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can |
||||
also manual config the DDR after undef this |
||||
definition. |
||||
CONFIG_DDR_ECC only for ECC DDR module |
||||
CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed |
||||
for more stability. |
||||
CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. |
||||
|
||||
Other than the above definitions, the rest in the config files are |
||||
straightforward. |
||||
|
||||
|
||||
3.2 Compilation |
||||
|
||||
Assuming you're using BASH shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix |
||||
cd u-boot |
||||
make distclean |
||||
make MPC8560ADS_config (or make MPC8540ADS_config) |
||||
make |
||||
|
||||
4. Notes: |
||||
|
||||
4.1 When connecting with kermit, the following commands must be present.in |
||||
your .kermrc file. These are especially important when booting as |
||||
MPC8560, as the serial console will not work without them: |
||||
|
||||
set speed 115200 |
||||
set carrier-watch off |
||||
set handshake none |
||||
set flow-control none |
||||
robust |
||||
|
||||
|
||||
4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC |
||||
ethernet. If that happens, you can try the following steps to make |
||||
network work: |
||||
|
||||
MPC8560ADS>tftp 1000000 pImage |
||||
(if it hangs, use Ctrl-C to quit) |
||||
MPC8560ADS>nm fdf24524 |
||||
>0 |
||||
>1 |
||||
>. (to quit this memory operation) |
||||
MPC8560ADS>tftp 1000000 pImage |
||||
|
||||
4.3 If you're one of the early developers using the Rev1 8540/8560 chips, |
||||
please use U-Boot 1.0.0, as the newer silicon will only support Rev2 |
||||
and future revisions of 8540/8560. |
||||
|
||||
|
||||
4.4 Reflash U-Boot Image using U-Boot |
||||
|
||||
tftp 10000 u-boot.bin |
||||
protect off fff80000 ffffffff |
||||
erase fff80000 ffffffff |
||||
cp.b 10000 fff80000 80000 |
||||
|
||||
|
||||
4.5 Reflash U-Boot with a BDI-2000 |
||||
|
||||
BDI> erase 0xFFF80000 0x4000 0x20 |
||||
BDI> prog 0xfff80000 u-boot.bin.8560ads |
||||
BDI> verify |
||||
|
||||
|
||||
5. Screen dump MPC8540ADS board |
||||
|
||||
U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25) |
||||
|
||||
Freescale PowerPC |
||||
Core: E500, Version: 2.0, (0x80200020) |
||||
System: 8540, Version: 2.0, (0x80300020) |
||||
Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz |
||||
L1 D-cache 32KB, L1 I-cache 32KB enabled. |
||||
Board: ADS |
||||
PCI1: 32 bit, 66 MHz (compiled) |
||||
I2C: ready |
||||
DRAM: Initializing |
||||
SDRAM: 64 MB |
||||
DDR: 256 MB |
||||
FLASH: 16 MB |
||||
L2 cache enabled: 256KB |
||||
*** Warning - bad CRC, using default environment |
||||
|
||||
In: serial |
||||
Out: serial |
||||
Err: serial |
||||
Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62) |
||||
MOTO ENET1: PHY is Marvell 88E1011S (1410c62) |
||||
MOTO ENET2: PHY is Davicom DM9161E (181b881) |
||||
MOTO ENET0, MOTO ENET1, MOTO ENET2 |
||||
Hit any key to stop autoboot: 0 |
||||
=> |
||||
=> fli |
||||
|
||||
Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K) |
||||
Size: 16 MB in 64 Sectors |
||||
Sector Start Addresses: |
||||
FF000000 FF040000 FF080000 FF0C0000 FF100000 |
||||
FF140000 FF180000 FF1C0000 FF200000 FF240000 |
||||
FF280000 FF2C0000 FF300000 FF340000 FF380000 |
||||
FF3C0000 FF400000 FF440000 FF480000 FF4C0000 |
||||
FF500000 FF540000 FF580000 FF5C0000 FF600000 |
||||
FF640000 FF680000 FF6C0000 FF700000 FF740000 |
||||
FF780000 FF7C0000 FF800000 FF840000 FF880000 |
||||
FF8C0000 FF900000 FF940000 FF980000 FF9C0000 |
||||
FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 |
||||
FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 |
||||
FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 |
||||
FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 |
||||
FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO) |
||||
|
||||
=> bdinfo |
||||
memstart = 0x00000000 |
||||
memsize = 0x10000000 |
||||
flashstart = 0xFF000000 |
||||
flashsize = 0x01000000 |
||||
flashoffset = 0x00000000 |
||||
sramstart = 0x00000000 |
||||
sramsize = 0x00000000 |
||||
immr_base = 0xE0000000 |
||||
bootflags = 0xE4013F80 |
||||
intfreq = 825 MHz |
||||
busfreq = 330 MHz |
||||
ethaddr = 00:E0:0C:00:00:FD |
||||
eth1addr = 00:E0:0C:00:01:FD |
||||
eth2addr = 00:E0:0C:00:02:FD |
||||
IP addr = 192.168.1.253 |
||||
baudrate = 115200 bps |
||||
|
||||
|
||||
=> printenv |
||||
bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr |
||||
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr |
||||
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr |
||||
bootdelay=10 |
||||
baudrate=115200 |
||||
loads_echo=1 |
||||
ethaddr=00:E0:0C:00:00:FD |
||||
eth1addr=00:E0:0C:00:01:FD |
||||
eth2addr=00:E0:0C:00:02:FD |
||||
ipaddr=192.168.1.253 |
||||
serverip=192.168.1.1 |
||||
rootpath=/nfsroot |
||||
gatewayip=192.168.1.1 |
||||
netmask=255.255.255.0 |
||||
hostname=unknown |
||||
bootfile=your.uImage |
||||
loadaddr=200000 |
||||
netdev=eth0 |
||||
consoledev=ttyS0 |
||||
ramdiskaddr=400000 |
||||
ramdiskfile=your.ramdisk.u-boot |
||||
stdin=serial |
||||
stdout=serial |
||||
stderr=serial |
||||
ethact=MOTO ENET0 |
||||
|
||||
Environment size: 1020/8188 bytes |
Loading…
Reference in new issue