Signed-off-by: Stefano Babic <sbabic@denx.de>master
Stefano Babic
8 years ago
commit
4f66e09bb9
@ -0,0 +1,56 @@ |
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/* |
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* Copyright (c) 2015, Linaro Limited |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <linux/linkage.h> |
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|
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#include <asm/opcodes-sec.h> |
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#include <asm/opcodes-virt.h> |
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|
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#define UNWIND(x...) |
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/* |
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* Wrap c macros in asm macros to delay expansion until after the |
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* SMCCC asm macro is expanded. |
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*/ |
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.macro SMCCC_SMC
|
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__SMC(0) |
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.endm |
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|
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.macro SMCCC_HVC
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__HVC(0) |
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.endm |
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.macro SMCCC instr |
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UNWIND( .fnstart) |
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mov r12, sp |
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push {r4-r7} |
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UNWIND( .save {r4-r7}) |
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ldm r12, {r4-r7} |
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\instr |
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pop {r4-r7} |
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ldr r12, [sp, #(4 * 4)] |
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stm r12, {r0-r3} |
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bx lr |
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UNWIND( .fnend) |
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.endm |
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|
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/* |
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* void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, |
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* unsigned long a3, unsigned long a4, unsigned long a5, |
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res, |
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* struct arm_smccc_quirk *quirk) |
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*/ |
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ENTRY(__arm_smccc_smc) |
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SMCCC SMCCC_SMC |
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ENDPROC(__arm_smccc_smc) |
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|
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/* |
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* void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, |
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* unsigned long a3, unsigned long a4, unsigned long a5, |
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res, |
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* struct arm_smccc_quirk *quirk) |
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*/ |
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ENTRY(__arm_smccc_hvc) |
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SMCCC SMCCC_HVC |
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ENDPROC(__arm_smccc_hvc) |
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@ -0,0 +1,44 @@ |
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/* |
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* Copyright (c) 2015, Linaro Limited |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/arm-smccc.h> |
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#include <generated/asm-offsets.h> |
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|
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.macro SMCCC instr |
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.cfi_startproc |
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\instr #0 |
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ldr x4, [sp] |
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stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] |
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stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] |
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ldr x4, [sp, #8] |
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cbz x4, 1f /* no quirk structure */ |
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ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] |
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cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6 |
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b.ne 1f |
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str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] |
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1: ret |
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.cfi_endproc |
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.endm |
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|
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/* |
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* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, |
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* unsigned long a3, unsigned long a4, unsigned long a5, |
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res, |
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* struct arm_smccc_quirk *quirk) |
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*/ |
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ENTRY(__arm_smccc_smc) |
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SMCCC smc |
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ENDPROC(__arm_smccc_smc) |
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|
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/* |
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* void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, |
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* unsigned long a3, unsigned long a4, unsigned long a5, |
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res, |
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* struct arm_smccc_quirk *quirk) |
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*/ |
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ENTRY(__arm_smccc_hvc) |
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SMCCC hvc |
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ENDPROC(__arm_smccc_hvc) |
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@ -0,0 +1,68 @@ |
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/* |
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* Copyright (C) 2017, Intel Corporation |
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* |
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* based on socfpga_cyclone5_de0_nano_soc.dts |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include "socfpga_cyclone5.dtsi" |
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/ { |
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model = "Terasic DE10-Nano"; |
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compatible = "altr,socfpga-cyclone5", "altr,socfpga"; |
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chosen { |
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bootargs = "console=ttyS0,115200"; |
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}; |
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aliases { |
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ethernet0 = &gmac1; |
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udc0 = &usb1; |
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}; |
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memory { |
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name = "memory"; |
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device_type = "memory"; |
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reg = <0x0 0x40000000>; /* 1GB */ |
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}; |
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|
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soc { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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|
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&gmac1 { |
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status = "okay"; |
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phy-mode = "rgmii"; |
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rxd0-skew-ps = <420>; |
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rxd1-skew-ps = <420>; |
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rxd2-skew-ps = <420>; |
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rxd3-skew-ps = <420>; |
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txen-skew-ps = <0>; |
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txc-skew-ps = <1860>; |
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rxdv-skew-ps = <420>; |
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rxc-skew-ps = <1680>; |
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}; |
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|
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&gpio0 { |
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status = "okay"; |
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}; |
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|
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&gpio1 { |
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status = "okay"; |
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}; |
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|
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&gpio2 { |
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status = "okay"; |
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}; |
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|
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&mmc0 { |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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}; |
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&usb1 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,24 @@ |
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&pinctrl { |
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usart1_pins_a: usart1@0 { |
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u-boot,dm-pre-reloc; |
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pins1 { |
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u-boot,dm-pre-reloc; |
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}; |
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pins2 { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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fmc_pins: fmc@0 { |
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u-boot,dm-pre-reloc; |
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pins |
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{ |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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}; |
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|
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&fmc { |
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bank1: bank@0 { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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@ -0,0 +1,255 @@ |
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/* |
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* Copyright 2016 - Vikas Manocha <vikas.manocha@st.com> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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#include "stm32f746.dtsi" |
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#include <dt-bindings/memory/stm32-sdram.h> |
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/ { |
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model = "STMicroelectronics STM32F769-DISCO board"; |
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compatible = "st,stm32f769-disco", "st,stm32f7"; |
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chosen { |
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bootargs = "root=/dev/ram rdinit=/linuxrc"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory { |
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reg = <0xC0000000 0x1000000>; |
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}; |
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aliases { |
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serial0 = &usart1; |
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spi0 = &qspi; |
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/* Aliases for gpios so as to use sequence */ |
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gpio0 = &gpioa; |
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gpio1 = &gpiob; |
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gpio2 = &gpioc; |
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gpio3 = &gpiod; |
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gpio4 = &gpioe; |
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gpio5 = &gpiof; |
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gpio6 = &gpiog; |
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gpio7 = &gpioh; |
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gpio8 = &gpioi; |
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gpio9 = &gpioj; |
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gpio10 = &gpiok; |
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}; |
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led1 { |
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compatible = "st,led1"; |
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led-gpio = <&gpioj 5 0>; |
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}; |
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button1 { |
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compatible = "st,button1"; |
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button-gpio = <&gpioa 0 0>; |
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}; |
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}; |
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&clk_hse { |
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clock-frequency = <25000000>; |
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}; |
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&pinctrl { |
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usart1_pins_a: usart1@0 { |
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pins1 { |
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pinmux = <STM32F746_PA9_FUNC_USART1_TX>; |
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bias-disable; |
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drive-push-pull; |
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slew-rate = <2>; |
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}; |
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pins2 { |
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pinmux = <STM32F746_PA10_FUNC_USART1_RX>; |
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bias-disable; |
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}; |
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}; |
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ethernet_mii: mii@0 { |
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pins { |
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pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, |
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<STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, |
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<STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, |
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<STM32F746_PA2_FUNC_ETH_MDIO>, |
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<STM32F746_PC1_FUNC_ETH_MDC>, |
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<STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, |
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<STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, |
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<STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, |
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<STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; |
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slew-rate = <2>; |
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}; |
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}; |
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|
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qspi_pins: qspi@0 { |
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pins { |
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pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, |
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<STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, |
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<STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>, |
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<STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>, |
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<STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, |
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<STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; |
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slew-rate = <2>; |
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}; |
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}; |
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|
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fmc_pins: fmc@0 { |
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pins { |
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pinmux = <STM32F746_PI10_FUNC_FMC_D31>, |
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<STM32F746_PI9_FUNC_FMC_D30>, |
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<STM32F746_PI7_FUNC_FMC_D29>, |
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<STM32F746_PI6_FUNC_FMC_D28>, |
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<STM32F746_PI3_FUNC_FMC_D27>, |
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<STM32F746_PI2_FUNC_FMC_D26>, |
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<STM32F746_PI1_FUNC_FMC_D25>, |
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<STM32F746_PI0_FUNC_FMC_D24>, |
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<STM32F746_PH15_FUNC_FMC_D23>, |
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<STM32F746_PH14_FUNC_FMC_D22>, |
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<STM32F746_PH13_FUNC_FMC_D21>, |
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<STM32F746_PH12_FUNC_FMC_D20>, |
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<STM32F746_PH11_FUNC_FMC_D19>, |
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<STM32F746_PH10_FUNC_FMC_D18>, |
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<STM32F746_PH9_FUNC_FMC_D17>, |
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<STM32F746_PH8_FUNC_FMC_D16>, |
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|
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<STM32F746_PD10_FUNC_FMC_D15>, |
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<STM32F746_PD9_FUNC_FMC_D14>, |
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<STM32F746_PD8_FUNC_FMC_D13>, |
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<STM32F746_PE15_FUNC_FMC_D12>, |
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<STM32F746_PE14_FUNC_FMC_D11>, |
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<STM32F746_PE13_FUNC_FMC_D10>, |
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<STM32F746_PE12_FUNC_FMC_D9>, |
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<STM32F746_PE11_FUNC_FMC_D8>, |
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<STM32F746_PE10_FUNC_FMC_D7>, |
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<STM32F746_PE9_FUNC_FMC_D6>, |
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<STM32F746_PE8_FUNC_FMC_D5>, |
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<STM32F746_PE7_FUNC_FMC_D4>, |
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<STM32F746_PD1_FUNC_FMC_D3>, |
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<STM32F746_PD0_FUNC_FMC_D2>, |
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<STM32F746_PD15_FUNC_FMC_D1>, |
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<STM32F746_PD14_FUNC_FMC_D0>, |
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|
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<STM32F746_PI5_FUNC_FMC_NBL3>, |
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<STM32F746_PI4_FUNC_FMC_NBL2>, |
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<STM32F746_PE1_FUNC_FMC_NBL1>, |
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<STM32F746_PE0_FUNC_FMC_NBL0>, |
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|
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<STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, |
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<STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, |
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|
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<STM32F746_PG1_FUNC_FMC_A11>, |
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<STM32F746_PG0_FUNC_FMC_A10>, |
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<STM32F746_PF15_FUNC_FMC_A9>, |
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<STM32F746_PF14_FUNC_FMC_A8>, |
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<STM32F746_PF13_FUNC_FMC_A7>, |
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<STM32F746_PF12_FUNC_FMC_A6>, |
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<STM32F746_PF5_FUNC_FMC_A5>, |
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<STM32F746_PF4_FUNC_FMC_A4>, |
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<STM32F746_PF3_FUNC_FMC_A3>, |
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<STM32F746_PF2_FUNC_FMC_A2>, |
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<STM32F746_PF1_FUNC_FMC_A1>, |
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<STM32F746_PF0_FUNC_FMC_A0>, |
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|
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<STM32F746_PH3_FUNC_FMC_SDNE0>, |
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<STM32F746_PH5_FUNC_FMC_SDNWE>, |
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<STM32F746_PF11_FUNC_FMC_SDNRAS>, |
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<STM32F746_PG15_FUNC_FMC_SDNCAS>, |
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<STM32F746_PH2_FUNC_FMC_SDCKE0>, |
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<STM32F746_PG8_FUNC_FMC_SDCLK>; |
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slew-rate = <2>; |
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}; |
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}; |
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}; |
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|
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&usart1 { |
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pinctrl-0 = <&usart1_pins_a>; |
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pinctrl-names = "default"; |
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status = "okay"; |
||||
}; |
||||
|
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&fmc { |
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pinctrl-0 = <&fmc_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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|
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mr-nbanks = <1>; |
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/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ |
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bank1: bank@0 { |
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4 |
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CAS_3 SDCLK_2 RD_BURST_EN |
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RD_PIPE_DL_0>; |
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st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 |
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TRP_2 TRCD_2>; |
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/* refcount = (64msec/total_row_sdram)*freq - 20 */ |
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st,sdram-refcount = < 1542 >; |
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}; |
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}; |
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|
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&mac { |
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status = "okay"; |
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pinctrl-0 = <ðernet_mii>; |
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phy-mode = "rmii"; |
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phy-handle = <&phy0>; |
||||
|
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mdio0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dwmac-mdio"; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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}; |
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|
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&qspi { |
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pinctrl-0 = <&qspi_pins>; |
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status = "okay"; |
||||
|
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qflash0: n25q128a { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "micron,n25q128a13", "spi-flash"; |
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spi-max-frequency = <108000000>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <1>; |
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memory-map = <0x90000000 0x1000000>; |
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reg = <0>; |
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}; |
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}; |
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@ -0,0 +1,69 @@ |
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/* |
||||
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "sun8i-r40.dtsi" |
||||
|
||||
/ { |
||||
model = "Banana Pi BPI-M2-Ultra"; |
||||
compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&i2c0_pins>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart0_pb_pins>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,183 @@ |
||||
/* |
||||
* Copyright 2016 Chen-Yu Tsai |
||||
* |
||||
* Chen-Yu Tsai <wens@csie.org> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
||||
|
||||
/ { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
interrupt-parent = <&gic>; |
||||
|
||||
aliases { |
||||
}; |
||||
|
||||
chosen { |
||||
}; |
||||
|
||||
clocks { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
osc24M: osc24M_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <24000000>; |
||||
}; |
||||
|
||||
osc32k: osc32k_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32768>; |
||||
clock-output-names = "osc32k"; |
||||
}; |
||||
}; |
||||
|
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
cpu0: cpu@0 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
cpu@1 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <1>; |
||||
}; |
||||
|
||||
cpu@2 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <2>; |
||||
}; |
||||
|
||||
cpu@3 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <3>; |
||||
}; |
||||
}; |
||||
|
||||
memory@40000000 { |
||||
device_type = "memory"; |
||||
reg = <0x40000000 0x80000000>; |
||||
}; |
||||
|
||||
soc { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
pio: pinctrl@1c20800 { |
||||
compatible = "allwinner,sun8i-r40-pinctrl"; |
||||
reg = <0x01c20800 0x400>; |
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
||||
/* apb should be replaced once CCU is implemented */ |
||||
clocks = <&osc24M>, <&osc24M>, <&osc32k>; |
||||
clock-names = "apb", "hosc", "losc"; |
||||
gpio-controller; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
#gpio-cells = <3>; |
||||
|
||||
i2c0_pins: i2c0_pins { |
||||
pins = "PB0", "PB1"; |
||||
function = "i2c0"; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
uart0_pb_pins: uart0_pb_pins { |
||||
pins = "PB22", "PB23"; |
||||
function = "uart0"; |
||||
bias-pull-up; |
||||
}; |
||||
}; |
||||
|
||||
uart0: serial@1c28000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28000 0x400>; |
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&osc24M>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c0: i2c@1c2ac00 { |
||||
compatible = "allwinner,sun6i-a31-i2c"; |
||||
reg = <0x01c2ac00 0x400>; |
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&osc24M>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
gic: interrupt-controller@1c81000 { |
||||
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
||||
reg = <0x01c81000 0x1000>, |
||||
<0x01c82000 0x1000>, |
||||
<0x01c84000 0x2000>, |
||||
<0x01c86000 0x2000>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
}; |
||||
}; |
||||
|
||||
timer { |
||||
compatible = "arm,armv7-timer"; |
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
||||
clock-frequency = <24000000>; |
||||
arm,cpu-registers-not-fw-configured; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,83 @@ |
||||
/* |
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include "sun8i-v3s.dtsi" |
||||
#include "sunxi-common-regulators.dtsi" |
||||
|
||||
/ { |
||||
model = "Lichee Pi Zero"; |
||||
compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; |
||||
|
||||
aliases { |
||||
serial0 = &uart0; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "serial0:115200n8"; |
||||
}; |
||||
}; |
||||
|
||||
&mmc0 { |
||||
pinctrl-0 = <&mmc0_pins_a>; |
||||
pinctrl-names = "default"; |
||||
broken-cd; |
||||
bus-width = <4>; |
||||
vmmc-supply = <®_vcc3v3>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart0 { |
||||
pinctrl-0 = <&uart0_pins_a>; |
||||
pinctrl-names = "default"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb_otg { |
||||
dr_mode = "otg"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbphy { |
||||
usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; |
||||
status = "okay"; |
||||
}; |
||||
@ -0,0 +1,284 @@ |
||||
/* |
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
||||
* |
||||
* This file is dual-licensed: you can use it either under the terms |
||||
* of the GPL or the X11 license, at your option. Note that this dual |
||||
* licensing only applies to this file, and not this project as a |
||||
* whole. |
||||
* |
||||
* a) This file is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of the |
||||
* License, or (at your option) any later version. |
||||
* |
||||
* This file is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* Or, alternatively, |
||||
* |
||||
* b) Permission is hereby granted, free of charge, to any person |
||||
* obtaining a copy of this software and associated documentation |
||||
* files (the "Software"), to deal in the Software without |
||||
* restriction, including without limitation the rights to use, |
||||
* copy, modify, merge, publish, distribute, sublicense, and/or |
||||
* sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following |
||||
* conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be |
||||
* included in all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#include <dt-bindings/clock/sun8i-v3s-ccu.h> |
||||
#include <dt-bindings/reset/sun8i-v3s-ccu.h> |
||||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
||||
#include <dt-bindings/pinctrl/sun4i-a10.h> |
||||
|
||||
/ { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
interrupt-parent = <&gic>; |
||||
|
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
cpu@0 { |
||||
compatible = "arm,cortex-a7"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
clocks = <&ccu CLK_CPU>; |
||||
}; |
||||
}; |
||||
|
||||
timer { |
||||
compatible = "arm,armv7-timer"; |
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
||||
}; |
||||
|
||||
clocks { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
osc24M: osc24M_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <24000000>; |
||||
clock-output-names = "osc24M"; |
||||
}; |
||||
|
||||
osc32k: osc32k_clk { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <32768>; |
||||
clock-output-names = "osc32k"; |
||||
}; |
||||
}; |
||||
|
||||
soc { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
mmc0: mmc@01c0f000 { |
||||
compatible = "allwinner,sun7i-a20-mmc"; |
||||
reg = <0x01c0f000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC0>, |
||||
<&ccu CLK_MMC0>, |
||||
<&ccu CLK_MMC0_OUTPUT>, |
||||
<&ccu CLK_MMC0_SAMPLE>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&ccu RST_BUS_MMC0>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc1: mmc@01c10000 { |
||||
compatible = "allwinner,sun7i-a20-mmc"; |
||||
reg = <0x01c10000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC1>, |
||||
<&ccu CLK_MMC1>, |
||||
<&ccu CLK_MMC1_OUTPUT>, |
||||
<&ccu CLK_MMC1_SAMPLE>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&ccu RST_BUS_MMC1>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
mmc2: mmc@01c11000 { |
||||
compatible = "allwinner,sun7i-a20-mmc"; |
||||
reg = <0x01c11000 0x1000>; |
||||
clocks = <&ccu CLK_BUS_MMC2>, |
||||
<&ccu CLK_MMC2>, |
||||
<&ccu CLK_MMC2_OUTPUT>, |
||||
<&ccu CLK_MMC2_SAMPLE>; |
||||
clock-names = "ahb", |
||||
"mmc", |
||||
"output", |
||||
"sample"; |
||||
resets = <&ccu RST_BUS_MMC2>; |
||||
reset-names = "ahb"; |
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
||||
status = "disabled"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
|
||||
usb_otg: usb@01c19000 { |
||||
compatible = "allwinner,sun8i-h3-musb"; |
||||
reg = <0x01c19000 0x0400>; |
||||
clocks = <&ccu CLK_BUS_OTG>; |
||||
resets = <&ccu RST_BUS_OTG>; |
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
||||
interrupt-names = "mc"; |
||||
phys = <&usbphy 0>; |
||||
phy-names = "usb"; |
||||
extcon = <&usbphy 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
usbphy: phy@01c19400 { |
||||
compatible = "allwinner,sun8i-v3s-usb-phy"; |
||||
reg = <0x01c19400 0x2c>, |
||||
<0x01c1a800 0x4>; |
||||
reg-names = "phy_ctrl", |
||||
"pmu0"; |
||||
clocks = <&ccu CLK_USB_PHY0>; |
||||
clock-names = "usb0_phy"; |
||||
resets = <&ccu RST_USB_PHY0>; |
||||
reset-names = "usb0_reset"; |
||||
status = "disabled"; |
||||
#phy-cells = <1>; |
||||
}; |
||||
|
||||
ccu: clock@01c20000 { |
||||
compatible = "allwinner,sun8i-v3s-ccu"; |
||||
reg = <0x01c20000 0x400>; |
||||
clocks = <&osc24M>, <&osc32k>; |
||||
clock-names = "hosc", "losc"; |
||||
#clock-cells = <1>; |
||||
#reset-cells = <1>; |
||||
}; |
||||
|
||||
rtc: rtc@01c20400 { |
||||
compatible = "allwinner,sun6i-a31-rtc"; |
||||
reg = <0x01c20400 0x54>; |
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
pio: pinctrl@01c20800 { |
||||
compatible = "allwinner,sun8i-v3s-pinctrl"; |
||||
reg = <0x01c20800 0x400>; |
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; |
||||
clock-names = "apb", "hosc", "losc"; |
||||
gpio-controller; |
||||
#gpio-cells = <3>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
|
||||
uart0_pins_a: uart0@0 { |
||||
pins = "PB8", "PB9"; |
||||
function = "uart0"; |
||||
bias-pull-up; |
||||
}; |
||||
|
||||
mmc0_pins_a: mmc0@0 { |
||||
pins = "PF0", "PF1", "PF2", "PF3", |
||||
"PF4", "PF5"; |
||||
function = "mmc0"; |
||||
drive-strength = <30>; |
||||
bias-pull-up; |
||||
}; |
||||
}; |
||||
|
||||
timer@01c20c00 { |
||||
compatible = "allwinner,sun4i-a10-timer"; |
||||
reg = <0x01c20c00 0xa0>; |
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&osc24M>; |
||||
}; |
||||
|
||||
wdt0: watchdog@01c20ca0 { |
||||
compatible = "allwinner,sun6i-a31-wdt"; |
||||
reg = <0x01c20ca0 0x20>; |
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
||||
}; |
||||
|
||||
uart0: serial@01c28000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28000 0x400>; |
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART0>; |
||||
resets = <&ccu RST_BUS_UART0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart1: serial@01c28400 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28400 0x400>; |
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART1>; |
||||
resets = <&ccu RST_BUS_UART1>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@01c28800 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x01c28800 0x400>; |
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <4>; |
||||
clocks = <&ccu CLK_BUS_UART2>; |
||||
resets = <&ccu RST_BUS_UART2>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
gic: interrupt-controller@01c81000 { |
||||
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
||||
reg = <0x01c81000 0x1000>, |
||||
<0x01c82000 0x1000>, |
||||
<0x01c84000 0x2000>, |
||||
<0x01c86000 0x2000>; |
||||
interrupt-controller; |
||||
#interrupt-cells = <3>; |
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* Copyright (c) 2017 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _ASM_ARCH_PERIPH_H |
||||
#define _ASM_ARCH_PERIPH_H |
||||
|
||||
/*
|
||||
* Peripherals supported by the hardware. |
||||
* These are used to specify pinctrl settings. |
||||
*/ |
||||
|
||||
enum periph_id { |
||||
PERIPH_ID_UART1, |
||||
PERIPH_ID_UART2, |
||||
PERIPH_ID_UART3, |
||||
PERIPH_ID_UART4, |
||||
PERIPH_ID_LPC, |
||||
PERIPH_ID_PWM0, |
||||
PERIPH_ID_PWM1, |
||||
PERIPH_ID_PWM2, |
||||
PERIPH_ID_PWM3, |
||||
PERIPH_ID_PWM4, |
||||
PERIPH_ID_PWM5, |
||||
PERIPH_ID_PWM6, |
||||
PERIPH_ID_PWM7, |
||||
PERIPH_ID_PWM8, |
||||
PERIPH_ID_MAC1, |
||||
PERIPH_ID_MAC2, |
||||
PERIPH_ID_VIDEO, |
||||
PERIPH_ID_SPI1, |
||||
PERIPH_ID_SPI2, |
||||
PERIPH_ID_I2C1, |
||||
PERIPH_ID_I2C2, |
||||
PERIPH_ID_I2C3, |
||||
PERIPH_ID_I2C4, |
||||
PERIPH_ID_I2C5, |
||||
PERIPH_ID_I2C6, |
||||
PERIPH_ID_I2C7, |
||||
PERIPH_ID_I2C8, |
||||
PERIPH_ID_I2C9, |
||||
PERIPH_ID_I2C10, |
||||
PERIPH_ID_I2C11, |
||||
PERIPH_ID_I2C12, |
||||
PERIPH_ID_I2C13, |
||||
PERIPH_ID_I2C14, |
||||
PERIPH_ID_SD1, |
||||
PERIPH_ID_SD2, |
||||
}; |
||||
|
||||
#endif /* _ASM_ARCH_SCU_AST2500_H */ |
||||
@ -0,0 +1,124 @@ |
||||
/*
|
||||
* Sunxi platform display controller register and constant defines |
||||
* |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* Based on out of tree Linux DRM driver defines: |
||||
* Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> |
||||
* Copyright (c) 2016 Allwinnertech Co., Ltd. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _SUNXI_DISPLAY2_H |
||||
#define _SUNXI_DISPLAY2_H |
||||
|
||||
/* internal clock settings */ |
||||
struct de_clk { |
||||
u32 gate_cfg; |
||||
u32 bus_cfg; |
||||
u32 rst_cfg; |
||||
u32 div_cfg; |
||||
u32 sel_cfg; |
||||
}; |
||||
|
||||
/* global control */ |
||||
struct de_glb { |
||||
u32 ctl; |
||||
u32 status; |
||||
u32 dbuff; |
||||
u32 size; |
||||
}; |
||||
|
||||
/* alpha blending */ |
||||
struct de_bld { |
||||
u32 fcolor_ctl; |
||||
struct { |
||||
u32 fcolor; |
||||
u32 insize; |
||||
u32 offset; |
||||
u32 dum; |
||||
} attr[4]; |
||||
u32 dum0[15]; |
||||
u32 route; |
||||
u32 premultiply; |
||||
u32 bkcolor; |
||||
u32 output_size; |
||||
u32 bld_mode[4]; |
||||
u32 dum1[4]; |
||||
u32 ck_ctl; |
||||
u32 ck_cfg; |
||||
u32 dum2[2]; |
||||
u32 ck_max[4]; |
||||
u32 dum3[4]; |
||||
u32 ck_min[4]; |
||||
u32 dum4[3]; |
||||
u32 out_ctl; |
||||
}; |
||||
|
||||
/* VI channel */ |
||||
struct de_vi { |
||||
struct { |
||||
u32 attr; |
||||
u32 size; |
||||
u32 coord; |
||||
u32 pitch[3]; |
||||
u32 top_laddr[3]; |
||||
u32 bot_laddr[3]; |
||||
} cfg[4]; |
||||
u32 fcolor[4]; |
||||
u32 top_haddr[3]; |
||||
u32 bot_haddr[3]; |
||||
u32 ovl_size[2]; |
||||
u32 hori[2]; |
||||
u32 vert[2]; |
||||
}; |
||||
|
||||
struct de_ui { |
||||
struct { |
||||
u32 attr; |
||||
u32 size; |
||||
u32 coord; |
||||
u32 pitch; |
||||
u32 top_laddr; |
||||
u32 bot_laddr; |
||||
u32 fcolor; |
||||
u32 dum; |
||||
} cfg[4]; |
||||
u32 top_haddr; |
||||
u32 bot_haddr; |
||||
u32 ovl_size; |
||||
}; |
||||
|
||||
/*
|
||||
* DE register constants. |
||||
*/ |
||||
#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) |
||||
#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) |
||||
|
||||
#define SUNXI_DE2_MUX_GLB_REGS 0x00000 |
||||
#define SUNXI_DE2_MUX_BLD_REGS 0x01000 |
||||
#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 |
||||
#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 |
||||
#define SUNXI_DE2_MUX_VSU_REGS 0x20000 |
||||
#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 |
||||
#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 |
||||
#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 |
||||
#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 |
||||
#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 |
||||
#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 |
||||
#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 |
||||
#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 |
||||
#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 |
||||
#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 |
||||
|
||||
#define SUNXI_DE2_FORMAT_XRGB_8888 4 |
||||
#define SUNXI_DE2_FORMAT_RGB_565 10 |
||||
|
||||
#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) |
||||
#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) |
||||
#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) |
||||
|
||||
#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) |
||||
|
||||
#endif /* _SUNXI_DISPLAY2_H */ |
||||
@ -0,0 +1,128 @@ |
||||
/*
|
||||
* Sunxi platform timing controller register and constant defines |
||||
* |
||||
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> |
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _LCDC_H |
||||
#define _LCDC_H |
||||
|
||||
#include <fdtdec.h> |
||||
|
||||
struct sunxi_lcdc_reg { |
||||
u32 ctrl; /* 0x00 */ |
||||
u32 int0; /* 0x04 */ |
||||
u32 int1; /* 0x08 */ |
||||
u8 res0[0x04]; /* 0x0c */ |
||||
u32 tcon0_frm_ctrl; /* 0x10 */ |
||||
u32 tcon0_frm_seed[6]; /* 0x14 */ |
||||
u32 tcon0_frm_table[4]; /* 0x2c */ |
||||
u8 res1[4]; /* 0x3c */ |
||||
u32 tcon0_ctrl; /* 0x40 */ |
||||
u32 tcon0_dclk; /* 0x44 */ |
||||
u32 tcon0_timing_active; /* 0x48 */ |
||||
u32 tcon0_timing_h; /* 0x4c */ |
||||
u32 tcon0_timing_v; /* 0x50 */ |
||||
u32 tcon0_timing_sync; /* 0x54 */ |
||||
u32 tcon0_hv_intf; /* 0x58 */ |
||||
u8 res2[0x04]; /* 0x5c */ |
||||
u32 tcon0_cpu_intf; /* 0x60 */ |
||||
u32 tcon0_cpu_wr_dat; /* 0x64 */ |
||||
u32 tcon0_cpu_rd_dat0; /* 0x68 */ |
||||
u32 tcon0_cpu_rd_dat1; /* 0x6c */ |
||||
u32 tcon0_ttl_timing0; /* 0x70 */ |
||||
u32 tcon0_ttl_timing1; /* 0x74 */ |
||||
u32 tcon0_ttl_timing2; /* 0x78 */ |
||||
u32 tcon0_ttl_timing3; /* 0x7c */ |
||||
u32 tcon0_ttl_timing4; /* 0x80 */ |
||||
u32 tcon0_lvds_intf; /* 0x84 */ |
||||
u32 tcon0_io_polarity; /* 0x88 */ |
||||
u32 tcon0_io_tristate; /* 0x8c */ |
||||
u32 tcon1_ctrl; /* 0x90 */ |
||||
u32 tcon1_timing_source; /* 0x94 */ |
||||
u32 tcon1_timing_scale; /* 0x98 */ |
||||
u32 tcon1_timing_out; /* 0x9c */ |
||||
u32 tcon1_timing_h; /* 0xa0 */ |
||||
u32 tcon1_timing_v; /* 0xa4 */ |
||||
u32 tcon1_timing_sync; /* 0xa8 */ |
||||
u8 res3[0x44]; /* 0xac */ |
||||
u32 tcon1_io_polarity; /* 0xf0 */ |
||||
u32 tcon1_io_tristate; /* 0xf4 */ |
||||
u8 res4[0x108]; /* 0xf8 */ |
||||
u32 mux_ctrl; /* 0x200 */ |
||||
u8 res5[0x1c]; /* 0x204 */ |
||||
u32 lvds_ana0; /* 0x220 */ |
||||
u32 lvds_ana1; /* 0x224 */ |
||||
}; |
||||
|
||||
/*
|
||||
* LCDC register constants. |
||||
*/ |
||||
#define SUNXI_LCDC_X(x) (((x) - 1) << 16) |
||||
#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) |
||||
#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) |
||||
#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) |
||||
#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) |
||||
#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 |
||||
#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 |
||||
#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) |
||||
#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) |
||||
#else |
||||
#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ |
||||
#endif |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) |
||||
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) |
||||
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) |
||||
#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) |
||||
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) |
||||
#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) |
||||
#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) |
||||
#ifdef CONFIG_SUNXI_GEN_SUN6I |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x40040320 |
||||
#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) |
||||
#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) |
||||
#else |
||||
#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 |
||||
#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) |
||||
#endif |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) |
||||
#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) |
||||
|
||||
void lcdc_init(struct sunxi_lcdc_reg * const lcdc); |
||||
void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); |
||||
void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
int clk_div, bool for_ext_vga_dac, |
||||
int depth, int dclk_phase); |
||||
void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, |
||||
const struct display_timing *mode, |
||||
bool ext_hvsync, bool is_composite); |
||||
|
||||
#endif /* _LCDC_H */ |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* Copyright (C) 2012 ARM Limited |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_OPCODES_SEC_H |
||||
#define __ASM_ARM_OPCODES_SEC_H |
||||
|
||||
#include <asm/opcodes.h> |
||||
|
||||
#define __SMC(imm4) __inst_arm_thumb32( \ |
||||
0xE1600070 | (((imm4) & 0xF) << 0), \
|
||||
0xF7F08000 | (((imm4) & 0xF) << 16) \
|
||||
) |
||||
|
||||
#endif /* __ASM_ARM_OPCODES_SEC_H */ |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* opcodes-virt.h: Opcode definitions for the ARM virtualization extensions |
||||
* Copyright (C) 2012 Linaro Limited |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __ASM_ARM_OPCODES_VIRT_H |
||||
#define __ASM_ARM_OPCODES_VIRT_H |
||||
|
||||
#include <asm/opcodes.h> |
||||
|
||||
#define __HVC(imm16) __inst_arm_thumb32( \ |
||||
0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \
|
||||
0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \
|
||||
) |
||||
|
||||
#define __ERET __inst_arm_thumb32( \ |
||||
0xE160006E, \
|
||||
0xF3DE8F00 \
|
||||
) |
||||
|
||||
#define __MSR_ELR_HYP(regnum) __inst_arm_thumb32( \ |
||||
0xE12EF300 | regnum, \
|
||||
0xF3808E30 | (regnum << 16) \
|
||||
) |
||||
|
||||
#endif /* ! __ASM_ARM_OPCODES_VIRT_H */ |
||||
@ -0,0 +1,229 @@ |
||||
/*
|
||||
* arch/arm/include/asm/opcodes.h |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_OPCODES_H |
||||
#define __ASM_ARM_OPCODES_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#include <linux/linkage.h> |
||||
extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); |
||||
#endif |
||||
|
||||
#define ARM_OPCODE_CONDTEST_FAIL 0 |
||||
#define ARM_OPCODE_CONDTEST_PASS 1 |
||||
#define ARM_OPCODE_CONDTEST_UNCOND 2 |
||||
|
||||
|
||||
/*
|
||||
* Assembler opcode byteswap helpers. |
||||
* These are only intended for use by this header: don't use them directly, |
||||
* because they will be suboptimal in most cases. |
||||
*/ |
||||
#define ___asm_opcode_swab32(x) ( \ |
||||
(((x) << 24) & 0xFF000000) \
|
||||
| (((x) << 8) & 0x00FF0000) \
|
||||
| (((x) >> 8) & 0x0000FF00) \
|
||||
| (((x) >> 24) & 0x000000FF) \
|
||||
) |
||||
#define ___asm_opcode_swab16(x) ( \ |
||||
(((x) << 8) & 0xFF00) \
|
||||
| (((x) >> 8) & 0x00FF) \
|
||||
) |
||||
#define ___asm_opcode_swahb32(x) ( \ |
||||
(((x) << 8) & 0xFF00FF00) \
|
||||
| (((x) >> 8) & 0x00FF00FF) \
|
||||
) |
||||
#define ___asm_opcode_swahw32(x) ( \ |
||||
(((x) << 16) & 0xFFFF0000) \
|
||||
| (((x) >> 16) & 0x0000FFFF) \
|
||||
) |
||||
#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) |
||||
#define ___asm_opcode_identity16(x) ((x) & 0xFFFF) |
||||
|
||||
|
||||
/*
|
||||
* Opcode byteswap helpers |
||||
* |
||||
* These macros help with converting instructions between a canonical integer |
||||
* format and in-memory representation, in an endianness-agnostic manner. |
||||
* |
||||
* __mem_to_opcode_*() convert from in-memory representation to canonical form. |
||||
* __opcode_to_mem_*() convert from canonical form to in-memory representation. |
||||
* |
||||
* |
||||
* Canonical instruction representation: |
||||
* |
||||
* ARM: 0xKKLLMMNN |
||||
* Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 |
||||
* Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 |
||||
* |
||||
* There is no way to distinguish an ARM instruction in canonical representation |
||||
* from a Thumb instruction (just as these cannot be distinguished in memory). |
||||
* Where this distinction is important, it needs to be tracked separately. |
||||
* |
||||
* Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not |
||||
* represent any valid Thumb-2 instruction. For this range, |
||||
* __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. |
||||
* |
||||
* The ___asm variants are intended only for use by this header, in situations |
||||
* involving inline assembler. For .S files, the normal __opcode_*() macros |
||||
* should do the right thing. |
||||
*/ |
||||
#ifdef __ASSEMBLY__ |
||||
|
||||
#define ___opcode_swab32(x) ___asm_opcode_swab32(x) |
||||
#define ___opcode_swab16(x) ___asm_opcode_swab16(x) |
||||
#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x) |
||||
#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x) |
||||
#define ___opcode_identity32(x) ___asm_opcode_identity32(x) |
||||
#define ___opcode_identity16(x) ___asm_opcode_identity16(x) |
||||
|
||||
#else /* ! __ASSEMBLY__ */ |
||||
|
||||
#include <linux/types.h> |
||||
#include <linux/swab.h> |
||||
|
||||
#define ___opcode_swab32(x) swab32(x) |
||||
#define ___opcode_swab16(x) swab16(x) |
||||
#define ___opcode_swahb32(x) swahb32(x) |
||||
#define ___opcode_swahw32(x) swahw32(x) |
||||
#define ___opcode_identity32(x) ((u32)(x)) |
||||
#define ___opcode_identity16(x) ((u16)(x)) |
||||
|
||||
#endif /* ! __ASSEMBLY__ */ |
||||
|
||||
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8 |
||||
|
||||
#define __opcode_to_mem_arm(x) ___opcode_swab32(x) |
||||
#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x) |
||||
#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x) |
||||
#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x) |
||||
#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x) |
||||
#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x) |
||||
|
||||
#else /* ! CONFIG_CPU_ENDIAN_BE8 */ |
||||
|
||||
#define __opcode_to_mem_arm(x) ___opcode_identity32(x) |
||||
#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x) |
||||
#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) |
||||
#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x) |
||||
#ifndef CONFIG_CPU_ENDIAN_BE32 |
||||
/*
|
||||
* On BE32 systems, using 32-bit accesses to store Thumb instructions will not |
||||
* work in all cases, due to alignment constraints. For now, a correct |
||||
* version is not provided for BE32. |
||||
*/ |
||||
#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x) |
||||
#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x) |
||||
#endif |
||||
|
||||
#endif /* ! CONFIG_CPU_ENDIAN_BE8 */ |
||||
|
||||
#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) |
||||
#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) |
||||
#ifndef CONFIG_CPU_ENDIAN_BE32 |
||||
#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) |
||||
#endif |
||||
|
||||
/* Operations specific to Thumb opcodes */ |
||||
|
||||
/* Instruction size checks: */ |
||||
#define __opcode_is_thumb32(x) ( \ |
||||
((x) & 0xF8000000) == 0xE8000000 \
|
||||
|| ((x) & 0xF0000000) == 0xF0000000 \
|
||||
) |
||||
#define __opcode_is_thumb16(x) ( \ |
||||
((x) & 0xFFFF0000) == 0 \
|
||||
&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \
|
||||
) |
||||
|
||||
/* Operations to construct or split 32-bit Thumb instructions: */ |
||||
#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16)) |
||||
#define __opcode_thumb32_second(x) (___opcode_identity16(x)) |
||||
#define __opcode_thumb32_compose(first, second) ( \ |
||||
(___opcode_identity32(___opcode_identity16(first)) << 16) \
|
||||
| ___opcode_identity32(___opcode_identity16(second)) \
|
||||
) |
||||
#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16)) |
||||
#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x)) |
||||
#define ___asm_opcode_thumb32_compose(first, second) ( \ |
||||
(___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
|
||||
| ___asm_opcode_identity32(___asm_opcode_identity16(second)) \
|
||||
) |
||||
|
||||
/*
|
||||
* Opcode injection helpers |
||||
* |
||||
* In rare cases it is necessary to assemble an opcode which the |
||||
* assembler does not support directly, or which would normally be |
||||
* rejected because of the CFLAGS or AFLAGS used to build the affected |
||||
* file. |
||||
* |
||||
* Before using these macros, consider carefully whether it is feasible |
||||
* instead to change the build flags for your file, or whether it really |
||||
* makes sense to support old assembler versions when building that |
||||
* particular kernel feature. |
||||
* |
||||
* The macros defined here should only be used where there is no viable |
||||
* alternative. |
||||
* |
||||
* |
||||
* __inst_arm(x): emit the specified ARM opcode |
||||
* __inst_thumb16(x): emit the specified 16-bit Thumb opcode |
||||
* __inst_thumb32(x): emit the specified 32-bit Thumb opcode |
||||
* |
||||
* __inst_arm_thumb16(arm, thumb): emit either the specified arm or |
||||
* 16-bit Thumb opcode, depending on whether an ARM or Thumb-2 |
||||
* kernel is being built |
||||
* |
||||
* __inst_arm_thumb32(arm, thumb): emit either the specified arm or |
||||
* 32-bit Thumb opcode, depending on whether an ARM or Thumb-2 |
||||
* kernel is being built |
||||
* |
||||
* |
||||
* Note that using these macros directly is poor practice. Instead, you |
||||
* should use them to define human-readable wrapper macros to encode the |
||||
* instructions that you care about. In code which might run on ARMv7 or |
||||
* above, you can usually use the __inst_arm_thumb{16,32} macros to |
||||
* specify the ARM and Thumb alternatives at the same time. This ensures |
||||
* that the correct opcode gets emitted depending on the instruction set |
||||
* used for the kernel build. |
||||
* |
||||
* Look at opcodes-virt.h for an example of how to use these macros. |
||||
*/ |
||||
#include <linux/stringify.h> |
||||
|
||||
#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) |
||||
#define __inst_thumb32(x) ___inst_thumb32( \ |
||||
___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)), \
|
||||
___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x)) \
|
||||
) |
||||
#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x)) |
||||
|
||||
#ifdef CONFIG_THUMB2_KERNEL |
||||
#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \ |
||||
__inst_thumb16(thumb_opcode) |
||||
#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \ |
||||
__inst_thumb32(thumb_opcode) |
||||
#else |
||||
#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) |
||||
#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) |
||||
#endif |
||||
|
||||
/* Helpers for the helpers. Don't use these directly. */ |
||||
#ifdef __ASSEMBLY__ |
||||
#define ___inst_arm(x) .long x |
||||
#define ___inst_thumb16(x) .short x |
||||
#define ___inst_thumb32(first, second) .short first, second |
||||
#else |
||||
#define ___inst_arm(x) ".long " __stringify(x) "\n\t" |
||||
#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t" |
||||
#define ___inst_thumb32(first, second) \ |
||||
".short " __stringify(first) ", " __stringify(second) "\n\t" |
||||
#endif |
||||
|
||||
#endif /* __ASM_ARM_OPCODES_H */ |
||||
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Reference in new issue