parent
03d3bfb008
commit
50752790bc
@ -0,0 +1,57 @@ |
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#
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# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
|
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#
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# See file CREDITS for list of people who contributed to this
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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COBJS-y += ebi.o
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COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
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COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
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COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
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COBJS-y += gpio.o
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COBJS-y += top.o
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COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
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COBJS := $(sort $(COBJS-y))
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,170 @@ |
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/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering |
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* |
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* Copyright (C) 2006 Micronas GmbH |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef _BCU_H |
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#define _BCU_H |
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enum bcu_tags { |
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BCU_VBV1 = 0, |
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BCU_VBV2 = 1, |
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BCU_BSS1 = 2, |
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BCU_BSS2 = 3, |
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BCU_TSD_TXT = 4, |
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BCU_TSD_SUBTITLES = 5, |
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BCU_TSD_PES_0 = 6, |
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BCU_TSD_PES_1 = 7, |
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BCU_TSD_PES_2 = 8, |
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BCU_TSD_PES_3 = 9, |
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BCU_TSIO_RECORD_0 = 10, |
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BCU_TSIO_RECORD_1 = 11, |
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BCU_TSIO_PLAYBACK_0 = 12, |
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BCU_TSIO_PLAYBACK_1 = 13, |
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BCU_SECURE_BUFFER = 14, |
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BCU_PCM1 = 15, |
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BCU_PCM2 = 16, |
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BCU_BSS_COPY = 17, |
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BCU_BSS_EXT1 = 18, |
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BCU_BSS_EXT2 = 19, |
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BCU_PCM_JINGLE = 20, |
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BCU_EBI_CPU_BUFFER = 21, |
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BCU_PCM_DELAY = 22, |
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BCU_FH_BUFFER_0 = 23, |
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BCU_FH_BUFFER_1 = 24, |
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BCU_TSD_SECTION_0 = 25, |
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BCU_TSD_SECTION_1 = 26, |
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BCU_TSD_SECTION_2 = 27, |
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BCU_TSD_SECTION_3 = 28, |
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BCU_TSD_SECTION_4 = 29, |
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BCU_TSD_SECTION_5 = 30, |
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BCU_TSD_SECTION_6 = 31, |
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BCU_TSD_SECTION_7 = 32, |
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BCU_TSD_SECTION_8 = 33, |
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BCU_TSD_SECTION_9 = 34, |
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BCU_TSD_SECTION_10 = 35, |
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BCU_TSD_SECTION_11 = 36, |
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BCU_TSD_SECTION_12 = 37, |
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BCU_TSD_SECTION_13 = 38, |
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BCU_TSD_SECTION_14 = 39, |
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BCU_TSD_SECTION_15 = 40, |
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BCU_TSD_SECTION_16 = 41, |
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BCU_TSD_SECTION_17 = 42, |
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BCU_TSD_SECTION_18 = 43, |
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BCU_TSD_SECTION_19 = 44, |
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BCU_TSD_SECTION_20 = 45, |
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BCU_TSD_SECTION_21 = 46, |
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BCU_TSD_SECTION_22 = 47, |
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BCU_TSD_SECTION_23 = 48, |
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BCU_TSD_SECTION_24 = 49, |
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BCU_TSD_SECTION_25 = 50, |
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BCU_TSD_SECTION_26 = 51, |
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BCU_TSD_SECTION_27 = 52, |
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BCU_TSD_SECTION_28 = 53, |
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BCU_TSD_SECTION_29 = 54, |
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BCU_TSD_SECTION_30 = 55, |
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BCU_TSD_SECTION_31 = 56, |
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BCU_TSD_SECTION_32 = 57, |
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BCU_TSD_SECTION_33 = 58, |
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BCU_TSD_SECTION_34 = 59, |
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BCU_TSD_SECTION_35 = 60, |
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BCU_TSD_SECTION_36 = 61, |
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BCU_TSD_SECTION_37 = 62, |
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BCU_TSD_SECTION_38 = 63, |
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BCU_TSD_SECTION_39 = 64, |
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BCU_TSD_SECTION_40 = 65, |
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BCU_TSD_SECTION_41 = 66, |
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BCU_TSD_SECTION_42 = 67, |
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BCU_TSD_SECTION_43 = 68, |
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BCU_TSD_SECTION_44 = 69, |
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BCU_TSD_SECTION_45 = 70, |
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BCU_TSD_SECTION_46 = 71, |
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BCU_TSD_SECTION_47 = 72, |
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BCU_TSD_SECTION_48 = 73, |
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BCU_TSD_SECTION_49 = 74, |
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BCU_TSD_SECTION_50 = 75, |
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BCU_TSD_SECTION_51 = 76, |
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BCU_TSD_SECTION_52 = 77, |
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BCU_TSD_SECTION_53 = 78, |
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BCU_TSIO_RECORD_2 = 79, |
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BCU_TSIO_RECORD_3 = 80, |
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BCU_TSIO_RECORD_4 = 81, |
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BCU_TSIO_RECORD_5 = 82, |
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BCU_TSIO_RECORD_6 = 83, |
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BCU_TSIO_RECORD_7 = 84, |
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BCU_TSIO_RECORD_8 = 85, |
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BCU_TSIO_RECORD_9 = 86, |
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BCU_PCM_DELAY_LINEAR = 87, |
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BCU_VD_MASTER_USER_DATA = 88, |
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BCU_VD_SLAVE_USER_DATA = 89, |
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BCU_VD_MASTER_REF0 = 90, |
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BCU_VD_MASTER_REF1 = 91, |
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BCU_VD_SLAVE_REF0 = 92, |
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BCU_VD_SLAVE_REF1 = 93, |
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BCU_VD_MASTER_DISP0_Y = 94, |
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BCU_VD_MASTER_DISP1_Y = 95, |
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BCU_VD_MASTER_DISP2_Y = 96, |
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BCU_VD_MASTER_DISP0_C = 97, |
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BCU_VD_MASTER_DISP1_C = 98, |
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BCU_VD_MASTER_DISP2_C = 99, |
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BCU_VD_SLAVE_DISP0_Y = 100, |
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BCU_VD_SLAVE_DISP1_Y = 101, |
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BCU_VD_SLAVE_DISP2_Y = 102, |
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BCU_VD_SLAVE_DISP0_C = 103, |
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BCU_VD_SLAVE_DISP1_C = 104, |
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BCU_VD_SLAVE_DISP2_C = 105, |
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BCU_CLUT_BUFFER_0 = 106, |
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BCU_CLUT_BUFFER_1 = 107, |
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BCU_OSD_FRAME_BUFFER_0 = 108, |
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BCU_OSD_FRAME_BUFFER_1 = 109, |
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BCU_GRAPHIC_FRAME_BUFFER0 = 110, |
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BCU_GRAPHIC_FRAME_BUFFER1 = 111, |
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BCU_DVP_VBI_REINSERTION = 112, |
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BCU_DVP_OSD_FRAME_BUFFER0 = 113, |
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BCU_DVP_OSD_FRAME_BUFFER1 = 114, |
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BCU_GAI_BUFFER = 115, |
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BCU_GA_SRC_BUFFER_0 = 116, |
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BCU_GA_SRC_BUFFER_1 = 117, |
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BCU_USB_BUFFER_0 = 118, |
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BCU_USB_BUFFER_1 = 119, |
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BCU_FE_3DCOMB_0 = 120, |
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BCU_FE_3DCOMB_1 = 121, |
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BCU_FE_3DCOMB_2 = 122, |
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BCU_FE_3DCOMB_3 = 123, |
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BCU_TNR_BUFFER_0 = 124, |
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BCU_TNR_BUFFER_1 = 125, |
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BCU_TNR_BUFFER_2 = 126, |
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BCU_MVAL_BUFFER = 127, |
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BCU_RC_BUFFER_0 = 128, |
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BCU_RC_BUFFER_1 = 129, |
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BCU_RC_BUFFER_2 = 130, |
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BCU_RC_BUFFER_3 = 131, |
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BCU_PIP_BUFFER_0 = 132, |
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BCU_PIP_BUFFER_1 = 133, |
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BCU_PIP_BUFFER_2 = 134, |
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BCU_PIP_BUFFER_3 = 135, |
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BCU_EWARP_BUFFER = 136, |
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BCU_OSD_BUFFER_0 = 137, |
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BCU_OSD_BUFFER_1 = 138, |
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BCU_GLOBAL_BUFFER_0 = 139, |
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BCU_GLOBAL_BUFFER_1 = 140, |
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BCU_MAX = 141 |
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}; |
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#endif /* _BCU_H */ |
@ -0,0 +1,31 @@ |
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#
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# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# vct_xxx boards with MIPS 4Kc CPU core
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#
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sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp |
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ifndef TEXT_BASE |
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TEXT_BASE = 0x87000000
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endif |
@ -0,0 +1,258 @@ |
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/*
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* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering |
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* |
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* Original Author Guenter Gebhardt |
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* Copyright (C) 2006 Micronas GmbH |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/errno.h> |
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#include "vct.h" |
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int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup) |
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{ |
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u32 enable; |
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union dcgu_clk_en1 en1; |
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union dcgu_clk_en2 en2; |
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switch (setup) { |
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case DCGU_SWITCH_ON: |
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enable = 1; |
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break; |
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case DCGU_SWITCH_OFF: |
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enable = 0; |
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break; |
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default: |
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printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__, |
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setup); |
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return -EINVAL; |
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} |
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if (module == DCGU_HW_MODULE_CPU) |
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en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); |
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else |
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en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); |
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switch (module) { |
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case DCGU_HW_MODULE_MSMC: |
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en1.bits.en_clkmsmc = enable; |
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break; |
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case DCGU_HW_MODULE_SSI_S: |
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en1.bits.en_clkssi_s = enable; |
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break; |
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case DCGU_HW_MODULE_SSI_M: |
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en1.bits.en_clkssi_m = enable; |
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break; |
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case DCGU_HW_MODULE_SMC: |
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en1.bits.en_clksmc = enable; |
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break; |
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case DCGU_HW_MODULE_EBI: |
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en1.bits.en_clkebi = enable; |
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break; |
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case DCGU_HW_MODULE_USB_PLL: |
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en1.bits.en_usbpll = enable; |
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break; |
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case DCGU_HW_MODULE_USB_60: |
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en1.bits.en_clkusb60 = enable; |
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break; |
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case DCGU_HW_MODULE_USB_24: |
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en1.bits.en_clkusb24 = enable; |
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break; |
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case DCGU_HW_MODULE_UART_2: |
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en1.bits.en_clkuart2 = enable; |
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break; |
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case DCGU_HW_MODULE_UART_1: |
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en1.bits.en_clkuart1 = enable; |
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break; |
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case DCGU_HW_MODULE_PERI: |
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en1.bits.en_clkperi20 = enable; |
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break; |
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case DCGU_HW_MODULE_CPU: |
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en2.bits.en_clkcpu = enable; |
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break; |
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case DCGU_HW_MODULE_I2S: |
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en1.bits.en_clk_i2s_dly = enable; |
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break; |
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case DCGU_HW_MODULE_ABP_SCC: |
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en1.bits.en_clk_scc_abp = enable; |
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break; |
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case DCGU_HW_MODULE_SPDIF: |
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en1.bits.en_clk_dtv_spdo = enable; |
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break; |
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case DCGU_HW_MODULE_AD: |
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en1.bits.en_clkad = enable; |
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break; |
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case DCGU_HW_MODULE_MVD: |
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en1.bits.en_clkmvd = enable; |
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break; |
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case DCGU_HW_MODULE_TSD: |
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en1.bits.en_clktsd = enable; |
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break; |
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case DCGU_HW_MODULE_GA: |
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en1.bits.en_clkga = enable; |
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break; |
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case DCGU_HW_MODULE_DVP: |
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en1.bits.en_clkdvp = enable; |
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break; |
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case DCGU_HW_MODULE_MR2: |
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en1.bits.en_clkmr2 = enable; |
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break; |
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case DCGU_HW_MODULE_MR1: |
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en1.bits.en_clkmr1 = enable; |
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break; |
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default: |
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printf("%s:%i:Invalid hardware module: %i\n", __FILE__, |
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__LINE__, module); |
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return -EINVAL; |
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} |
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|
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/*
|
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* The reg_read() following the reg_write() below forces the write to |
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* be really done on the bus. |
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* Otherwise the clock may not be switched on when this API function |
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* returns, which may cause an bus error if a registers of the hardware |
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* module connected to the clock is accessed. |
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*/ |
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if (module == DCGU_HW_MODULE_CPU) { |
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reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg); |
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en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); |
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} else { |
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reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); |
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en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); |
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} |
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|
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return 0; |
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} |
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|
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int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup) |
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{ |
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union dcgu_reset_unit1 val; |
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u32 enable; |
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|
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switch (setup) { |
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case DCGU_SWITCH_ON: |
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enable = 1; |
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break; |
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case DCGU_SWITCH_OFF: |
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enable = 0; |
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break; |
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default: |
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printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__, |
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setup); |
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return -EINVAL; |
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} |
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|
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val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); |
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switch (module) { |
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case DCGU_HW_MODULE_MSMC: |
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val.bits.swreset_clkmsmc = enable; |
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break; |
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case DCGU_HW_MODULE_SSI_S: |
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val.bits.swreset_clkssi_s = enable; |
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break; |
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case DCGU_HW_MODULE_SSI_M: |
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val.bits.swreset_clkssi_m = enable; |
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break; |
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case DCGU_HW_MODULE_SMC: |
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val.bits.swreset_clksmc = enable; |
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break; |
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case DCGU_HW_MODULE_EBI: |
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val.bits.swreset_clkebi = enable; |
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break; |
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case DCGU_HW_MODULE_USB_60: |
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val.bits.swreset_clkusb60 = enable; |
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break; |
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case DCGU_HW_MODULE_USB_24: |
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val.bits.swreset_clkusb24 = enable; |
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break; |
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case DCGU_HW_MODULE_UART_2: |
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val.bits.swreset_clkuart2 = enable; |
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break; |
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case DCGU_HW_MODULE_UART_1: |
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val.bits.swreset_clkuart1 = enable; |
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break; |
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case DCGU_HW_MODULE_PWM: |
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val.bits.swreset_pwm = enable; |
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break; |
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case DCGU_HW_MODULE_GPT: |
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val.bits.swreset_gpt = enable; |
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break; |
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case DCGU_HW_MODULE_I2C2: |
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val.bits.swreset_i2c2 = enable; |
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break; |
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case DCGU_HW_MODULE_I2C1: |
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val.bits.swreset_i2c1 = enable; |
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break; |
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case DCGU_HW_MODULE_GPIO2: |
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val.bits.swreset_gpio2 = enable; |
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break; |
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case DCGU_HW_MODULE_GPIO1: |
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val.bits.swreset_gpio1 = enable; |
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break; |
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case DCGU_HW_MODULE_CPU: |
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val.bits.swreset_clkcpu = enable; |
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break; |
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case DCGU_HW_MODULE_I2S: |
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val.bits.swreset_clk_i2s_dly = enable; |
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break; |
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case DCGU_HW_MODULE_ABP_SCC: |
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val.bits.swreset_clk_scc_abp = enable; |
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break; |
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case DCGU_HW_MODULE_SPDIF: |
||||
val.bits.swreset_clk_dtv_spdo = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_AD: |
||||
val.bits.swreset_clkad = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_MVD: |
||||
val.bits.swreset_clkmvd = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_TSD: |
||||
val.bits.swreset_clktsd = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_TSIO: |
||||
val.bits.swreset_clktsio = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_GA: |
||||
val.bits.swreset_clkga = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_MPC: |
||||
val.bits.swreset_clkmpc = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_CVE: |
||||
val.bits.swreset_clkcve = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_DVP: |
||||
val.bits.swreset_clkdvp = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_MR2: |
||||
val.bits.swreset_clkmr2 = enable; |
||||
break; |
||||
case DCGU_HW_MODULE_MR1: |
||||
val.bits.swreset_clkmr1 = enable; |
||||
break; |
||||
default: |
||||
printf("%s:%i:Invalid hardware module: %i\n", __FILE__, |
||||
__LINE__, module); |
||||
return -EINVAL; |
||||
} |
||||
reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,179 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* Copyright (C) 2006 Micronas GmbH |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _DCGU_H |
||||
#define _DCGU_H |
||||
|
||||
enum dcgu_switch { |
||||
DCGU_SWITCH_OFF, /* Switch off */ |
||||
DCGU_SWITCH_ON /* Switch on */ |
||||
}; |
||||
|
||||
enum dcgu_hw_module { |
||||
DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ |
||||
|
||||
DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ |
||||
DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ |
||||
|
||||
DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ |
||||
DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ |
||||
DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ |
||||
DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ |
||||
DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ |
||||
DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ |
||||
|
||||
DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ |
||||
DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ |
||||
|
||||
DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ |
||||
DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ |
||||
|
||||
DCGU_HW_MODULE_UART_1, /* Selects first UART module */ |
||||
DCGU_HW_MODULE_UART_2, /* Selects second UART module */ |
||||
|
||||
DCGU_HW_MODULE_AD, /* Selects audio decoder module */ |
||||
DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ |
||||
DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ |
||||
DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ |
||||
|
||||
DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ |
||||
DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ |
||||
DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ |
||||
|
||||
DCGU_HW_MODULE_USBH, /* Selects USB hub module */ |
||||
DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ |
||||
DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ |
||||
DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ |
||||
|
||||
DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ |
||||
DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ |
||||
DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ |
||||
DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ |
||||
DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ |
||||
DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ |
||||
|
||||
DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ |
||||
DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ |
||||
|
||||
DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ |
||||
DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ |
||||
|
||||
DCGU_HW_MODULE_COM, /* Selects COM unit module */ |
||||
DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ |
||||
DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ |
||||
|
||||
DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ |
||||
DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ |
||||
DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ |
||||
DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ |
||||
|
||||
DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ |
||||
DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ |
||||
DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ |
||||
DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ |
||||
DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ |
||||
DCGU_HW_MODULE_SCC, /* Selects SCC module */ |
||||
DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ |
||||
DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ |
||||
DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ |
||||
DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ |
||||
DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ |
||||
DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ |
||||
}; |
||||
|
||||
union dcgu_clk_en1 { |
||||
u32 reg; |
||||
struct { |
||||
u32 res1:8; /* reserved */ |
||||
u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ |
||||
u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ |
||||
u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ |
||||
u32 en_clksmc:1; /* Enable bit for clksmc (#) */ |
||||
u32 en_clkebi:1; /* Enable bit for clkebi (#) */ |
||||
u32 en_usbpll:1; /* Enable bit for the USB PLL */ |
||||
u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ |
||||
u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ |
||||
u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ |
||||
u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ |
||||
u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ |
||||
u32 res2:3; /* reserved */ |
||||
u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ |
||||
u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ |
||||
u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ |
||||
u32 en_clkad:1; /* Enable bit for clkad (#) */ |
||||
u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ |
||||
u32 en_clktsd:1; /* Enable bit for clktsd (#) */ |
||||
u32 en_clkga:1; /* Enable bit for clkga (#) */ |
||||
u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ |
||||
u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ |
||||
u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ |
||||
} bits; |
||||
}; |
||||
|
||||
union dcgu_clk_en2 { |
||||
u32 reg; |
||||
struct { |
||||
u32 res1:31; /* reserved */ |
||||
u32 en_clkcpu:1; /* Enable bit for clkcpu */ |
||||
} bits; |
||||
}; |
||||
|
||||
union dcgu_reset_unit1 { |
||||
u32 reg; |
||||
struct { |
||||
u32 res1:1; |
||||
u32 swreset_clkmsmc:1; |
||||
u32 swreset_clkssi_s:1; |
||||
u32 swreset_clkssi_m:1; |
||||
u32 swreset_clksmc:1; |
||||
u32 swreset_clkebi:1; |
||||
u32 swreset_clkusb60:1; |
||||
u32 swreset_clkusb24:1; |
||||
u32 swreset_clkuart2:1; |
||||
u32 swreset_clkuart1:1; |
||||
u32 swreset_pwm:1; |
||||
u32 swreset_gpt:1; |
||||
u32 swreset_i2c2:1; |
||||
u32 swreset_i2c1:1; |
||||
u32 swreset_gpio2:1; |
||||
u32 swreset_gpio1:1; |
||||
u32 swreset_clkcpu:1; |
||||
u32 res2:2; |
||||
u32 swreset_clk_i2s_dly:1; |
||||
u32 swreset_clk_scc_abp:1; |
||||
u32 swreset_clk_dtv_spdo:1; |
||||
u32 swreset_clkad:1; |
||||
u32 swreset_clkmvd:1; |
||||
u32 swreset_clktsd:1; |
||||
u32 swreset_clktsio:1; |
||||
u32 swreset_clkga:1; |
||||
u32 swreset_clkmpc:1; |
||||
u32 swreset_clkcve:1; |
||||
u32 swreset_clkdvp:1; |
||||
u32 swreset_clkmr2:1; |
||||
u32 swreset_clkmr1:1; |
||||
} bits; |
||||
}; |
||||
|
||||
int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); |
||||
int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); |
||||
|
||||
#endif /* _DCGU_H */ |
@ -0,0 +1,48 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* Copyright (C) 2006 Micronas GmbH |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include "vct.h" |
||||
|
||||
int ebi_initialize(void) |
||||
{ |
||||
#if defined(CONFIG_VCT_NOR) |
||||
if (ebi_init_nor_flash()) |
||||
return -1; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_VCT_ONENAND) |
||||
if (ebi_init_onenand()) |
||||
return -1; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DRIVER_SMC911X) |
||||
if (ebi_init_smc911x()) |
||||
return -1; |
||||
#endif |
||||
|
||||
reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); |
||||
|
||||
ebi_wait(); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __EBI__ |
||||
#define __EBI__ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include "vct.h" |
||||
|
||||
#define EXT_DEVICE_CHANNEL_3 (0x30000000) |
||||
#define EXT_DEVICE_CHANNEL_2 (0x20000000) |
||||
#define EXT_DEVICE_CHANNEL_1 (0x10000000) |
||||
#define EXT_CPU_ACCESS_ACTIVE (0x00000001) |
||||
#define EXT_DMA_ACCESS_ACTIVE (1 << 14) |
||||
#define EXT_CPU_IORDY_SL (0x00000001) |
||||
|
||||
#define EBI_CPU_WRITE (1 << 31) |
||||
#define EBI_CPU_ID_SHIFT (28) |
||||
#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) |
||||
|
||||
/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ |
||||
#define ADDR_LATCH_ENABLE 0 |
||||
#define ADDR_ACTIVATION 4 |
||||
#define CHIP_SELECT_START 8 |
||||
#define OUTPUT_ENABLE_START 12 |
||||
#define WAIT_TIME 28 |
||||
#define READ_DURATION 20 |
||||
|
||||
/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ |
||||
#define OUTPUT_ENABLE_END 0 |
||||
#define CHIP_SELECT_END 4 |
||||
#define ADDR_DEACTIVATION 8 |
||||
#define RECOVER_TIME 12 |
||||
#define ACK_TIME 20 |
||||
|
||||
/* various bits in configuration register EBI_DEV[01]_CONFIG1 */ |
||||
#define EBI_EXTERNAL_DATA_8 (1 << 8) |
||||
#define EBI_EXT_ADDR_SHIFT (1 << 22) |
||||
#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT |
||||
#define EBI_CHIP_SELECT_1 0x2 |
||||
#define EBI_CHIP_SELECT_2 0x4 |
||||
#define EBI_BUSY_EN_RD (1 << 12) |
||||
#define DIR_ACCESS_WRITE (1 << 20) |
||||
#define DIR_ACCESS_MASK (1 << 20) |
||||
|
||||
/* various bits in configuration register EBI_DEV[01]_CONFIG2 */ |
||||
#define ADDRESS_INCREMENT_ON 0x0 |
||||
#define ADDRESS_INCREMENT_OFF 0x100 |
||||
#define QUEUE_LENGTH_1 0x40 |
||||
#define QUEUE_LENGTH_2 0x80 |
||||
#define QUEUE_LENGTH_3 0xC0 |
||||
#define QUEUE_LENGTH_4 0 |
||||
#define CPU_TRANSFER_SIZE_32 0 |
||||
#define CPU_TRANSFER_SIZE_16 0x10 |
||||
#define CPU_TRANSFER_SIZE_8 0x20 |
||||
#define READ_ENDIANNESS_ABCD 0 |
||||
#define READ_ENDIANNESS_DCBA 0x4 |
||||
#define READ_ENDIANNESS_BADC 0x8 |
||||
#define READ_ENDIANNESS_CDAB 0xC |
||||
#define WRITE_ENDIANNESS_ABCD 0 |
||||
#define WRITE_ENDIANNESS_DCBA 0x1 |
||||
#define WRITE_ENDIANNESS_BADC 0x2 |
||||
#define WRITE_ENDIANNESS_CDAB 0x3 |
||||
|
||||
/* various bits in configuration register EBI_CTRL_SIG_ACTLV */ |
||||
#define IORDY_ACTIVELEVEL_HIGH (1 << 14) |
||||
#define ALE_ACTIVELEVEL_HIGH (1 << 8) |
||||
|
||||
/* bits in register EBI_SIG_LEVEL */ |
||||
#define IORDY_LEVEL_MASK 1 |
||||
|
||||
static inline void ebi_wait(void) |
||||
{ |
||||
while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) |
||||
; /* wait */ |
||||
} |
||||
|
||||
#endif |
@ -0,0 +1,131 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include "vct.h" |
||||
|
||||
static u32 ebi_read(u32 addr) |
||||
{ |
||||
addr &= ~0xFC000000; |
||||
|
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); |
||||
ebi_wait(); |
||||
|
||||
return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); |
||||
} |
||||
|
||||
static int ebi_write_u16(u32 addr, u32 data, int fetchIO) |
||||
{ |
||||
u32 val = (data << 16); |
||||
|
||||
addr &= ~0xFC000000; |
||||
|
||||
ebi_wait(); |
||||
|
||||
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), |
||||
EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr); |
||||
ebi_wait(); |
||||
|
||||
if (fetchIO) { |
||||
u32 counter = 0; |
||||
while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { |
||||
if (counter++ > 0xFFFFFF) |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static u16 ebi_read_u16(u32 addr) |
||||
{ |
||||
return ((ebi_read(addr) >> 16) & 0xFFFF); |
||||
} |
||||
|
||||
static u8 ebi_read_u8(u32 addr) |
||||
{ |
||||
u32 val = ebi_read(addr) >> 16; |
||||
|
||||
if (addr & 0x1) |
||||
return val & 0xff; |
||||
else |
||||
return (val >> 8) & 0xff; |
||||
} |
||||
|
||||
/*
|
||||
* EBI initialization for NOR FLASH access |
||||
*/ |
||||
int ebi_init_nor_flash(void) |
||||
{ |
||||
reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); |
||||
|
||||
reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); |
||||
reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); |
||||
|
||||
reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); |
||||
reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); |
||||
reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); |
||||
reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); |
||||
reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Accessor functions replacing the "weak" functions in |
||||
* drivers/mtd/cfi_flash.c |
||||
*/ |
||||
void flash_write8(u8 value, void *addr) |
||||
{ |
||||
ebi_write_u16((u32)addr, value, 0); |
||||
} |
||||
|
||||
void flash_write16(u16 value, void *addr) |
||||
{ |
||||
ebi_write_u16((u32)addr, value, 0); |
||||
} |
||||
|
||||
u8 flash_read8(void *addr) |
||||
{ |
||||
return ebi_read_u8((u32)addr); |
||||
} |
||||
|
||||
u16 flash_read16(void *addr) |
||||
{ |
||||
return ebi_read_u16((u32)addr); |
||||
} |
||||
|
||||
u32 flash_read32(void *addr) |
||||
{ |
||||
return ((u32)ebi_read_u16((u32)addr) << 16) | |
||||
ebi_read_u16((u32)addr + 2); |
||||
} |
||||
|
||||
void *board_flash_read_memcpy(void *dest, const void *src, size_t count) |
||||
{ |
||||
u16 *tmp = (u16 *)dest, *s = (u16 *)src; |
||||
int i; |
||||
|
||||
for (i = 0; i < count; i += 2) |
||||
*tmp++ = flash_read16(s++); |
||||
|
||||
return dest; |
||||
} |
@ -0,0 +1,198 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <linux/mtd/mtd.h> |
||||
#include <linux/mtd/onenand.h> |
||||
#include "vct.h" |
||||
|
||||
#define BURST_SIZE_WORDS 4 |
||||
|
||||
static u16 ebi_nand_read_word(void __iomem *addr) |
||||
{ |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); |
||||
ebi_wait(); |
||||
|
||||
return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; |
||||
} |
||||
|
||||
static void ebi_nand_write_word(u16 data, void __iomem * addr) |
||||
{ |
||||
ebi_wait(); |
||||
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), |
||||
EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); |
||||
ebi_wait(); |
||||
} |
||||
|
||||
/*
|
||||
* EBI initialization for OneNAND FLASH access |
||||
*/ |
||||
int ebi_init_onenand(void) |
||||
{ |
||||
reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); |
||||
|
||||
reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); |
||||
reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); |
||||
|
||||
reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); |
||||
reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ |
||||
|
||||
reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); |
||||
reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); |
||||
reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); |
||||
reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); |
||||
reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); |
||||
reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); |
||||
reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); |
||||
reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); |
||||
|
||||
reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); |
||||
reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); |
||||
|
||||
reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); |
||||
reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); |
||||
|
||||
/* prepare DMA configuration for EBI */ |
||||
reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); |
||||
|
||||
/* READ only no byte order change, TAG 1 used */ |
||||
reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); |
||||
|
||||
reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ |
||||
reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); |
||||
reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); |
||||
reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) |
||||
{ |
||||
void *ret = dst; |
||||
u16 *d = dst; |
||||
u16 *s = (u16 *)src; |
||||
|
||||
len >>= 1; |
||||
while (len-- > 0) |
||||
*d++ = ebi_nand_read_word(s++); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len) |
||||
{ |
||||
void *ret = dst; |
||||
u32 *d = (u32 *)dst; |
||||
u32 s = (u32)src; |
||||
u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int); |
||||
u32 n_blocks = len / bytes_per_block; |
||||
u32 block = 0; |
||||
u32 burst_word; |
||||
|
||||
for (block = 0; block < n_blocks; block++) { |
||||
/* Trigger read channel 3 */ |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), |
||||
(EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block)))); |
||||
/* Poll status to see whether read has finished */ |
||||
ebi_wait(); |
||||
|
||||
/* Squirrel the data away in a safe place */ |
||||
for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++) |
||||
*d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) |
||||
{ |
||||
void *ret = dst; |
||||
u16 *d = dst; |
||||
u16 *s = (u16 *)src; |
||||
|
||||
len >>= 1; |
||||
while (len-- > 0) |
||||
ebi_nand_write_word(*s++, d++); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) |
||||
{ |
||||
struct onenand_chip *this = mtd->priv; |
||||
|
||||
if (ONENAND_CURRENT_BUFFERRAM(this)) { |
||||
if (area == ONENAND_DATARAM) |
||||
return mtd->writesize; |
||||
if (area == ONENAND_SPARERAM) |
||||
return mtd->oobsize; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, |
||||
unsigned char *buffer, int offset, |
||||
size_t count) |
||||
{ |
||||
struct onenand_chip *this = mtd->priv; |
||||
void __iomem *bufferram; |
||||
|
||||
bufferram = this->base + area; |
||||
bufferram += onenand_bufferram_offset(mtd, area); |
||||
|
||||
if (count < 4) |
||||
memcpy_16_from_onenand(buffer, bufferram + offset, count); |
||||
else |
||||
memcpy_32_from_onenand(buffer, bufferram + offset, count); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, |
||||
const unsigned char *buffer, int offset, |
||||
size_t count) |
||||
{ |
||||
struct onenand_chip *this = mtd->priv; |
||||
void __iomem *bufferram; |
||||
|
||||
bufferram = this->base + area; |
||||
bufferram += onenand_bufferram_offset(mtd, area); |
||||
|
||||
memcpy_16_to_onenand(bufferram + offset, buffer, count); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void onenand_board_init(struct mtd_info *mtd) |
||||
{ |
||||
struct onenand_chip *chip = mtd->priv; |
||||
|
||||
/*
|
||||
* Insert board specific OneNAND access functions |
||||
*/ |
||||
chip->read_word = ebi_nand_read_word; |
||||
chip->write_word = ebi_nand_write_word; |
||||
|
||||
chip->read_bufferram = ebi_read_bufferram; |
||||
chip->read_spareram = ebi_read_bufferram; |
||||
chip->write_bufferram = ebi_write_bufferram; |
||||
} |
@ -0,0 +1,94 @@ |
||||
/*
|
||||
* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include "vct.h" |
||||
|
||||
/*
|
||||
* EBI initialization for SMC911x access |
||||
*/ |
||||
int ebi_init_smc911x(void) |
||||
{ |
||||
reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); |
||||
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); |
||||
|
||||
reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); |
||||
reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); |
||||
|
||||
reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); |
||||
reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); |
||||
|
||||
reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); |
||||
reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Accessor functions replacing the "weak" functions in |
||||
* drivers/net/smc911x.c |
||||
*/ |
||||
u32 smc911x_reg_read(u32 addr) |
||||
{ |
||||
volatile u32 data; |
||||
|
||||
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); |
||||
ebi_wait(); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); |
||||
ebi_wait(); |
||||
data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); |
||||
|
||||
return (data); |
||||
} |
||||
|
||||
void smc911x_reg_write(u32 addr, u32 data) |
||||
{ |
||||
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); |
||||
ebi_wait(); |
||||
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), |
||||
EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); |
||||
ebi_wait(); |
||||
} |
||||
|
||||
void pkt_data_push(u32 addr, u32 data) |
||||
{ |
||||
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); |
||||
ebi_wait(); |
||||
reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), |
||||
EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); |
||||
ebi_wait(); |
||||
|
||||
return; |
||||
} |
||||
|
||||
u32 pkt_data_pull(u32 addr) |
||||
{ |
||||
volatile u32 data; |
||||
|
||||
reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); |
||||
ebi_wait(); |
||||
reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); |
||||
ebi_wait(); |
||||
data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); |
||||
|
||||
return data; |
||||
} |
Loading…
Reference in new issue