This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>master
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <timer.h> |
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#include <asm/io.h> |
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/* Timer control1 register */ |
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#define CR1_CEN BIT(0) |
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#define CR1_ARPE BIT(7) |
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/* Event Generation Register register */ |
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#define EGR_UG BIT(0) |
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/* Auto reload register for free running config */ |
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#define GPT_FREE_RUNNING 0xFFFFFFFF |
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struct stm32_timer_regs { |
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u32 cr1; |
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u32 cr2; |
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u32 smcr; |
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u32 dier; |
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u32 sr; |
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u32 egr; |
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u32 ccmr1; |
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u32 ccmr2; |
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u32 ccer; |
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u32 cnt; |
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u32 psc; |
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u32 arr; |
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u32 reserved; |
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u32 ccr1; |
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u32 ccr2; |
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u32 ccr3; |
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u32 ccr4; |
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u32 reserved1; |
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u32 dcr; |
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u32 dmar; |
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u32 tim2_5_or; |
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}; |
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struct stm32_timer_priv { |
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struct stm32_timer_regs *base; |
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}; |
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static int stm32_timer_get_count(struct udevice *dev, u64 *count) |
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{ |
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struct stm32_timer_priv *priv = dev_get_priv(dev); |
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struct stm32_timer_regs *regs = priv->base; |
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*count = readl(®s->cnt); |
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return 0; |
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} |
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static int stm32_timer_probe(struct udevice *dev) |
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{ |
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
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struct stm32_timer_priv *priv = dev_get_priv(dev); |
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struct stm32_timer_regs *regs; |
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struct clk clk; |
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fdt_addr_t addr; |
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int ret; |
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u32 rate, psc; |
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addr = dev_read_addr(dev); |
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if (addr == FDT_ADDR_T_NONE) |
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return -EINVAL; |
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priv->base = (struct stm32_timer_regs *)addr; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret < 0) |
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return ret; |
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ret = clk_enable(&clk); |
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if (ret) { |
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dev_err(dev, "failed to enable clock\n"); |
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return ret; |
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} |
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regs = priv->base; |
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/* Stop the timer */ |
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clrbits_le32(®s->cr1, CR1_CEN); |
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/* get timer clock */ |
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rate = clk_get_rate(&clk); |
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/* we set timer prescaler to obtain a 1MHz timer counter frequency */ |
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psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; |
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writel(psc, ®s->psc); |
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/* Set timer frequency to 1MHz */ |
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uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; |
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/* Configure timer for auto-reload */ |
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setbits_le32(®s->cr1, CR1_ARPE); |
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/* load value for auto reload */ |
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writel(GPT_FREE_RUNNING, ®s->arr); |
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/* start timer */ |
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setbits_le32(®s->cr1, CR1_CEN); |
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/* Update generation */ |
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setbits_le32(®s->egr, EGR_UG); |
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return 0; |
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} |
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static const struct timer_ops stm32_timer_ops = { |
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.get_count = stm32_timer_get_count, |
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}; |
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static const struct udevice_id stm32_timer_ids[] = { |
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{ .compatible = "st,stm32-timer" }, |
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{} |
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}; |
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U_BOOT_DRIVER(stm32_timer) = { |
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.name = "stm32_timer", |
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.id = UCLASS_TIMER, |
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.of_match = stm32_timer_ids, |
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.priv_auto_alloc_size = sizeof(struct stm32_timer_priv), |
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.probe = stm32_timer_probe, |
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.ops = &stm32_timer_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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