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@ -26,46 +26,46 @@ |
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#ifndef __IMMAP_5329__ |
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#define __IMMAP_5329__ |
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#define MMAP_SCM1 0xEC000000 |
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#define MMAP_MDHA 0xEC080000 |
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#define MMAP_SKHA 0xEC084000 |
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#define MMAP_RNG 0xEC088000 |
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#define MMAP_SCM2 0xFC000000 |
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#define MMAP_XBS 0xFC004000 |
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#define MMAP_FBCS 0xFC008000 |
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#define MMAP_CAN 0xFC020000 |
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#define MMAP_FEC 0xFC030000 |
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#define MMAP_SCM3 0xFC040000 |
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#define MMAP_EDMA 0xFC044000 |
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#define MMAP_TCD 0xFC045000 |
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#define MMAP_INTC0 0xFC048000 |
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#define MMAP_INTC1 0xFC04C000 |
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#define MMAP_INTCACK 0xFC054000 |
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#define MMAP_I2C 0xFC058000 |
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#define MMAP_QSPI 0xFC05C000 |
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#define MMAP_UART0 0xFC060000 |
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#define MMAP_UART1 0xFC064000 |
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#define MMAP_UART2 0xFC068000 |
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#define MMAP_DTMR0 0xFC070000 |
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#define MMAP_DTMR1 0xFC074000 |
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#define MMAP_DTMR2 0xFC078000 |
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#define MMAP_DTMR3 0xFC07C000 |
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#define MMAP_PIT0 0xFC080000 |
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#define MMAP_PIT1 0xFC084000 |
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#define MMAP_PIT2 0xFC088000 |
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#define MMAP_PIT3 0xFC08C000 |
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#define MMAP_PWM 0xFC090000 |
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#define MMAP_EPORT 0xFC094000 |
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#define MMAP_WDOG 0xFC098000 |
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#define MMAP_CCM 0xFC0A0000 |
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#define MMAP_GPIO 0xFC0A4000 |
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#define MMAP_RTC 0xFC0A8000 |
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#define MMAP_LCDC 0xFC0AC000 |
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#define MMAP_USBOTG 0xFC0B0000 |
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#define MMAP_USBH 0xFC0B4000 |
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#define MMAP_SDRAM 0xFC0B8000 |
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#define MMAP_SSI 0xFC0BC000 |
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#define MMAP_PLL 0xFC0C0000 |
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#define MMAP_SCM1 0xEC000000 |
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#define MMAP_MDHA 0xEC080000 |
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#define MMAP_SKHA 0xEC084000 |
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#define MMAP_RNG 0xEC088000 |
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#define MMAP_SCM2 0xFC000000 |
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#define MMAP_XBS 0xFC004000 |
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#define MMAP_FBCS 0xFC008000 |
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#define MMAP_CAN 0xFC020000 |
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#define MMAP_FEC 0xFC030000 |
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#define MMAP_SCM3 0xFC040000 |
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#define MMAP_EDMA 0xFC044000 |
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#define MMAP_TCD 0xFC045000 |
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#define MMAP_INTC0 0xFC048000 |
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#define MMAP_INTC1 0xFC04C000 |
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#define MMAP_INTCACK 0xFC054000 |
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#define MMAP_I2C 0xFC058000 |
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#define MMAP_QSPI 0xFC05C000 |
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#define MMAP_UART0 0xFC060000 |
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#define MMAP_UART1 0xFC064000 |
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#define MMAP_UART2 0xFC068000 |
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#define MMAP_DTMR0 0xFC070000 |
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#define MMAP_DTMR1 0xFC074000 |
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#define MMAP_DTMR2 0xFC078000 |
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#define MMAP_DTMR3 0xFC07C000 |
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#define MMAP_PIT0 0xFC080000 |
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#define MMAP_PIT1 0xFC084000 |
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#define MMAP_PIT2 0xFC088000 |
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#define MMAP_PIT3 0xFC08C000 |
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#define MMAP_PWM 0xFC090000 |
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#define MMAP_EPORT 0xFC094000 |
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#define MMAP_WDOG 0xFC098000 |
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#define MMAP_CCM 0xFC0A0000 |
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#define MMAP_GPIO 0xFC0A4000 |
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#define MMAP_RTC 0xFC0A8000 |
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#define MMAP_LCDC 0xFC0AC000 |
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#define MMAP_USBOTG 0xFC0B0000 |
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#define MMAP_USBH 0xFC0B4000 |
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#define MMAP_SDRAM 0xFC0B8000 |
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#define MMAP_SSI 0xFC0BC000 |
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#define MMAP_PLL 0xFC0C0000 |
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/* System control module registers */ |
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typedef struct scm1_ctrl { |
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