CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000 and CMPC885 which are respectively based on MPC866 and MPC885 processors. This patch adds support for the first board. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>master
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BOARDS from CS Systemes d'Information |
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M: Christophe Leroy <christophe.leroy@c-s.fr> |
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S: Maintained |
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F: board/cssi/ |
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F: include/configs/MCR3000.h |
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F: configs/MCR3000_defconfig |
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if TARGET_MCR3000 |
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config SYS_BOARD |
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default "MCR3000" |
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config SYS_VENDOR |
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default "cssi" |
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config SYS_CONFIG_NAME |
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default "MCR3000" |
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config SYS_TEXT_BASE |
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default 0x04000000 |
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endif |
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/*
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* Copyright (C) 2010-2017 CS Systemes d'Information |
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* Florent Trinh Thai <florent.trinh-thai@c-s.fr> |
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* Christophe Leroy <christophe.leroy@c-s.fr> |
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* |
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* Board specific routines for the MCR3000 board |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <hwconfig.h> |
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#include <mpc8xx.h> |
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#include <fdt_support.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const uint cs1_dram_table_66[] = { |
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/* DRAM - single read. (offset 0 in upm RAM) */ |
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0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400, |
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0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/* DRAM - burst read. (offset 8 in upm RAM) */ |
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0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00, |
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0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/* DRAM - single write. (offset 18 in upm RAM) */ |
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0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804, |
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0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, |
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/* DRAM - burst write. (offset 20 in upm RAM) */ |
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0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00, |
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0x00FFFC00, 0x00FFFC04, 0x0FFEF804, 0x0FFDF404, |
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0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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/* refresh (offset 30 in upm RAM) */ |
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0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04, |
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0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF, |
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/* init */ |
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0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF, |
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/* exception. (offset 3c in upm RAM) */ |
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0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
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}; |
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int ft_board_setup(void *blob, bd_t *bd) |
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{ |
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const char *sync = "receive"; |
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ft_cpu_setup(blob, bd); |
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/* BRG */ |
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do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency", |
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bd->bi_busfreq, 1); |
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/* MAC addr */ |
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fdt_fixup_ethernet(blob); |
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/* Bus Frequency for CPM */ |
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do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1); |
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/* E1 interface - Set data rate */ |
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do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1); |
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/* E1 interface - Set channel phase to 0 */ |
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do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1); |
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/* E1 interface - rising edge sync pulse transmit */ |
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do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse", |
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sync, strlen(sync), 1); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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serial_puts("BOARD: MCR3000 CSSI\n"); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
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memctl8xx_t __iomem *memctl = &immap->im_memctl; |
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printf("UPMA init for SDRAM (CAS latency 2), "); |
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printf("init address 0x%08x, size ", (int)dram_init); |
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/* Configure UPMA for cs1 */ |
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upmconfig(UPMA, (uint *)cs1_dram_table_66, |
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sizeof(cs1_dram_table_66) / sizeof(uint)); |
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udelay(10); |
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out_be16(&memctl->memc_mptpr, 0x0200); |
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out_be32(&memctl->memc_mamr, 0x14904000); |
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udelay(10); |
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM); |
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out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM); |
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udelay(10); |
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out_be32(&memctl->memc_mcr, 0x80002830); |
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out_be32(&memctl->memc_mar, 0x00000088); |
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out_be32(&memctl->memc_mcr, 0x80002038); |
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udelay(200); |
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, |
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SDRAM_MAX_SIZE); |
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return 0; |
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} |
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int misc_init_r(void) |
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{ |
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
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iop8xx_t __iomem *iop = &immr->im_ioport; |
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/* Set port C13 as GPIO (BTN_ACQ_AL) */ |
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clrbits_be16(&iop->iop_pcpar, 0x4); |
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clrbits_be16(&iop->iop_pcdir, 0x4); |
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/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */ |
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if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0) |
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setenv("bootdelay", "60"); |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
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/*
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* Erase FPGA(s) for reboot |
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*/ |
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clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */ |
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setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */ |
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udelay(1); /* Wait more than 300ns */ |
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setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */ |
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return 0; |
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} |
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#
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# Copyright (C) 2010-2017 CS Systemes d'Information
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# Christophe Leroy <christophe.leroy@c-s.fr>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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obj-y += MCR3000.o
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obj-$(CONFIG_CMD_NAND) += nand.o
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/*
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* Copyright (C) 2010-2017 CS Systemes d'Information |
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* Florent Trinh Thai <florent.trinh-thai@c-s.fr> |
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* Christophe Leroy <christophe.leroy@c-s.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <nand.h> |
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#include <asm/io.h> |
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#define BIT_CLE ((unsigned short)0x0800) |
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#define BIT_ALE ((unsigned short)0x0400) |
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#define BIT_NCE ((unsigned short)0x1000) |
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
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unsigned short pddat = 0; |
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/* The hardware control change */ |
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if (ctrl & NAND_CTRL_CHANGE) { |
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pddat = in_be16(&immr->im_ioport.iop_pddat); |
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/* Clearing ALE and CLE */ |
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pddat &= ~(BIT_CLE | BIT_ALE); |
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/* Driving NCE pin */ |
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if (ctrl & NAND_NCE) |
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pddat &= ~BIT_NCE; |
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else |
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pddat |= BIT_NCE; |
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/* Driving CLE and ALE pin */ |
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if (ctrl & NAND_CLE) |
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pddat |= BIT_CLE; |
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if (ctrl & NAND_ALE) |
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pddat |= BIT_ALE; |
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out_be16(&immr->im_ioport.iop_pddat, pddat); |
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} |
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/* Writing the command */ |
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if (cmd != NAND_CMD_NONE) |
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out_8(this->IO_ADDR_W, cmd); |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
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/* Set GPIO Port */ |
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setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); |
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clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00); |
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clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000); |
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nand->chip_delay = 60; |
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nand->ecc.mode = NAND_ECC_SOFT; |
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nand->cmd_ctrl = nand_hwcontrol; |
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return 0; |
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} |
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/* |
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* Copyright (C) 2010-2017 CS Systemes d'Information |
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* Christophe Leroy <christophe.leroy@c-s.fr> |
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* |
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* (C) Copyright 2001-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Modified by Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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arch/powerpc/cpu/mpc8xx/start.o (.text) |
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arch/powerpc/cpu/mpc8xx/start.o (.text*) |
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arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
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arch/powerpc/cpu/mpc8xx/built-in.o (.text*) |
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arch/powerpc/lib/built-in.o (.text*) |
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board/cssi/MCR3000/built-in.o (.text*) |
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disk/built-in.o (.text*) |
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drivers/net/built-in.o (.text*) |
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*(.text) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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KEEP(*(.got)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(4096); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(4096); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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} |
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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ENTRY(_start) |
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CONFIG_PPC=y |
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CONFIG_8xx=y |
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CONFIG_TARGET_MCR3000=y |
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CONFIG_BOOTDELAY=5 |
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CONFIG_HUSH_PARSER=y |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_CMD_NET=y |
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CONFIG_CMD_DHCP=y |
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# CONFIG_LED_STATUS_BOARD_SPECIFIC is not set |
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# CONFIG_MMC is not set |
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CONFIG_MTD_NOR_FLASH=y |
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# CONFIG_PCI is not set |
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CONFIG_OF_LIBFDT=y |
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CONFIG_SYS_PROMPT="S3K> " |
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CONFIG_NETDEVICES=y |
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CONFIG_MPC8XX_FEC=y |
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CONFIG_CMD_SAVEENV=y |
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CONFIG_CMD_FLASH=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_ASKENV=y |
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CONFIG_CMD_MTDPARTS=y |
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CONFIG_CMD_NAND=y |
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# CONFIG_CMD_BDI is not set |
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# CONFIG_CMD_ECHO is not set |
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# CONFIG_CMD_FPGA is not set |
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# CONFIG_CMD_IMI is not set |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_ITEST is not set |
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# CONFIG_CMD_CONSOLE is not set |
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# CONFIG_CMD_LOADB is not set |
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# CONFIG_CMD_LOADS is not set |
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# CONFIG_CMD_MD5SUM is not set |
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# CONFIG_CMD_MISC is not set |
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# CONFIG_CMD_SETGETDCR is not set |
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# CONFIG_CMD_SHA1 is not set |
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# CONFIG_CMD_SOURCE is not set |
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CONFIG_CMD_IMMAP=y |
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CONFIG_SYS_IMMR=0xFF000000 |
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CONFIG_SYS_OR0_PRELIM=0xFFC00926 |
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CONFIG_SYS_BR0_PRELIM=0x04000801 |
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CONFIG_SYS_BR1_PRELIM_BOOL=y |
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CONFIG_SYS_BR1_PRELIM=0x00000081 |
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CONFIG_SYS_OR1_PRELIM=0xFE000E00 |
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CONFIG_SYS_BR2_PRELIM_BOOL=y |
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CONFIG_SYS_BR2_PRELIM=0x08000801 |
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CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A |
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CONFIG_SYS_BR3_PRELIM_BOOL=y |
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CONFIG_SYS_BR3_PRELIM=0x0C000401 |
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CONFIG_SYS_OR3_PRELIM=0xFFFF8142 |
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CONFIG_SYS_BR4_PRELIM_BOOL=y |
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CONFIG_SYS_BR4_PRELIM=0x10000801 |
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CONFIG_SYS_OR4_PRELIM=0xFFFF8D08 |
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CONFIG_SYS_BR5_PRELIM_BOOL=y |
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CONFIG_SYS_BR5_PRELIM=0x14000801 |
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CONFIG_SYS_OR5_PRELIM=0xFFFF8916 |
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CONFIG_SYS_BR6_PRELIM_BOOL=y |
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CONFIG_SYS_BR6_PRELIM=0x18000801 |
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CONFIG_SYS_OR6_PRELIM=0xFFFF0908 |
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CONFIG_SYS_BR7_PRELIM_BOOL=y |
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CONFIG_SYS_BR7_PRELIM=0x1C000001 |
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CONFIG_SYS_OR7_PRELIM=0xFFFF810A |
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CONFIG_8xx_GCLK_FREQ=132000000 |
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CONFIG_SYS_SYPCR=0xFFFFFF8F |
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CONFIG_SYS_SIUMCR=0x00600400 |
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CONFIG_SYS_TBSCR=0x00C3 |
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CONFIG_SYS_PISCR=0x0000 |
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CONFIG_SYS_PLPRCR_BOOL=y |
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CONFIG_SYS_PLPRCR=0x00460004 |
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CONFIG_SYS_SCCR_MASK=0x60000000 |
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CONFIG_SYS_SCCR=0x00C20000 |
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CONFIG_SYS_DER=0x2002000F |
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CONFIG_AUTOBOOT=y |
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CONFIG_AUTOBOOT_KEYED=y |
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CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n" |
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CONFIG_AUTOBOOT_DELAY_STR="root" |
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CONFIG_OF_BOARD_SETUP=y |
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CONFIG_LZMA=y |
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CONFIG_SHA256=y |
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@ -0,0 +1,158 @@ |
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/*
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* Copyright (C) 2010-2017 CS Systemes d'Information |
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* Christophe Leroy <christophe.leroy@c-s.fr> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/* High Level Configuration Options */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"sdram_type=SDRAM\0" \
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"flash_type=AM29LV160DB\0" \
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"loadaddr=0x400000\0" \
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"filename=uImage.lzma\0" \
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"nfsroot=/opt/ofs\0" \
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"dhcp_ip=ip=:::::eth0:dhcp\0" \
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"console_args=console=ttyCPM0,115200N8\0" \
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"flashboot=setenv bootargs " \
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"${console_args} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
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"mcr3k:eth0:off;" \
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"${ofl_args}; " \
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"bootm 0x04060000 - 0x04050000\0" \
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"tftpboot=setenv bootargs " \
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"${console_args} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
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"mcr3k:eth0:off " \
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"${ofl_args}; " \
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"tftp ${loadaddr} ${filename};" \
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"tftp 0xf00000 mcr3000.dtb;" \
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"bootm ${loadaddr} - 0xf00000\0" \
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"netboot=dhcp ${loadaddr} ${filename};" \
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"tftp 0xf00000 mcr3000.dtb;" \
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"setenv bootargs " \
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"root=/dev/nfs rw " \
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"${console_args} " \
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"${dhcp_ip};" \
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"bootm ${loadaddr} - 0xf00000\0" \
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"nfsboot=setenv bootargs " \
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"root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
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"${console_args} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
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"mcr3k:eth0:off;" \
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"bootm 0x04060000 - 0x04050000\0" \
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"dhcpboot=dhcp ${loadaddr} ${filename};" \
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"tftp 0xf00000 mcr3000.dtb;" \
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"setenv bootargs " \
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"${console_args} " \
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"${dhcp_ip} " \
|
||||
"${ofl_args}; " \
|
||||
"bootm ${loadaddr} - 0xf00000\0" |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
#define CONFIG_IPADDR 192.168.0.3 |
||||
#define CONFIG_SERVERIP 192.168.0.1 |
||||
#define CONFIG_NETMASK 255.0.0.0 |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flashboot" |
||||
#define CONFIG_BOOTARGS "ubi.mtd=4 root=ubi0:rootfs rw " \ |
||||
"rootfstype=ubifs rootflags=sync " \
|
||||
"console=ttyCPM0,115200N8 " \
|
||||
"ip=${ipaddr}:::${netmask}:mcr3k:eth0:off" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CONFIG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
#ifdef CONFIG_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "S3K> " |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00002000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x200000 |
||||
|
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Definitions for initial stack pointer and data area (in DPRAM) */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 64 |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define SDRAM_MAX_SIZE (32 * 1024 * 1024) |
||||
|
||||
/* FLASH organization */ |
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_FLASH_CFI 1 |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 35 |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) |
||||
|
||||
/* Environment Configuration */ |
||||
|
||||
/* environment is in FLASH */ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024) |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/* Cache Configuration */ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 |
||||
|
||||
/* Ethernet configuration part */ |
||||
#define CONFIG_SYS_DISCOVER_PHY 1 |
||||
#ifdef CONFIG_MPC8XX_FEC |
||||
#define CONFIG_MII_INIT 1 |
||||
#endif |
||||
|
||||
/* NAND configuration part */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x0C000000 |
||||
|
||||
/* Internal Definitions */ |
||||
|
||||
/* Boot Flags*/ |
||||
#define BOOTFLAG_COLD 0x01 |
||||
#define BOOTFLAG_WARM 0x02 |
||||
|
||||
/* Misc Settings */ |
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue