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/*
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* (C) Copyright 2007 Michal Simek |
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* |
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* Michal SIMEK <monstr@monstr.eu> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Based on Xilinx drivers |
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* |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <net.h> |
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#include <asm/io.h> |
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#include <asm/asm.h> |
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#include "xilinx_emac.h" |
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#ifdef XILINX_EMAC |
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#undef DEBUG |
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#define ENET_MAX_MTU PKTSIZE |
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#define ENET_ADDR_LENGTH 6 |
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static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ |
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static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; |
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static XEmac Emac; |
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void eth_halt(void) |
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{ |
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return; |
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} |
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int eth_init(bd_t * bis) |
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{ |
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u32 HelpReg; |
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#ifdef DEBUG |
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printf("EMAC Initialization Started\n\r"); |
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#endif |
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if (Emac.IsStarted) { |
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puts("Emac is started\n"); |
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return 0; |
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} |
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memset (&Emac, 0, sizeof (XEmac)); |
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Emac.BaseAddress = XILINX_EMAC_BASEADDR; |
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/* Setting up FIFOs */ |
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Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress + |
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XEM_PFIFO_RXREG_OFFSET; |
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Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress + |
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XEM_PFIFO_RXDATA_OFFSET; |
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out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); |
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Emac.SendFifo.RegBaseAddress = Emac.BaseAddress + |
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XEM_PFIFO_TXREG_OFFSET; |
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Emac.SendFifo.DataBaseAddress = Emac.BaseAddress + |
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XEM_PFIFO_TXDATA_OFFSET; |
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out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); |
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/* Reset the entire IPIF */ |
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out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET, |
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XIIF_V123B_RESET_MASK); |
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/* Stopping EMAC for setting up MAC */ |
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HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); |
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HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); |
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out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); |
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if (!getenv("ethaddr")) { |
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memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH); |
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} |
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/* Set the device station address high and low registers */ |
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HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1]; |
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out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg); |
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HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) | |
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(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5]; |
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out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg); |
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HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | |
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XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | |
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XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; |
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out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); |
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Emac.IsStarted = 1; |
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/* Enable the transmitter, and receiver */ |
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HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET); |
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HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); |
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HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); |
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out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg); |
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printf("EMAC Initialization complete\n\r"); |
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return 0; |
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} |
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int eth_send(volatile void *ptr, int len) |
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{ |
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u32 IntrStatus; |
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u32 XmitStatus; |
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u32 FifoCount; |
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u32 WordCount; |
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u32 ExtraByteCount; |
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u32 *WordBuffer = (u32 *) ptr; |
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if (len > ENET_MAX_MTU) |
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len = ENET_MAX_MTU; |
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/*
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* Check for overruns and underruns for the transmit status and length |
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* FIFOs and make sure the send packet FIFO is not deadlocked. |
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* Any of these conditions is bad enough that we do not want to |
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* continue. The upper layer software should reset the device to resolve |
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* the error. |
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*/ |
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IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); |
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if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | |
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XEM_EIR_XMIT_LFIFO_OVER_MASK)) { |
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#ifdef DEBUG |
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puts ("Transmitting overrun error\n"); |
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#endif |
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return 0; |
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} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | |
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XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { |
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#ifdef DEBUG |
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puts ("Transmitting underrun error\n"); |
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#endif |
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return 0; |
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} else if (in_be32 (Emac.SendFifo.RegBaseAddress + |
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { |
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#ifdef DEBUG |
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puts("Transmitting fifo error\n"); |
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#endif |
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return 0; |
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} |
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/*
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* Before writing to the data FIFO, make sure the length FIFO is not |
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* full. The data FIFO might not be full yet even though the length FIFO |
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* is. This avoids an overrun condition on the length FIFO and keeps the |
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* FIFOs in sync. |
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* |
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* Clear the latched LFIFO_FULL bit so next time around the most |
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* current status is represented |
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*/ |
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if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { |
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out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus |
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& XEM_EIR_XMIT_LFIFO_FULL_MASK); |
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#ifdef DEBUG |
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puts ("Fifo is full\n"); |
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#endif |
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return 0; |
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} |
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/* get the count of how many words may be inserted into the FIFO */ |
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FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress + |
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; |
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WordCount = len >> 2; |
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ExtraByteCount = len & 0x3; |
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if (FifoCount < WordCount) { |
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#ifdef DEBUG |
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puts ("Sending packet is larger then size of FIFO\n"); |
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#endif |
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return 0; |
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} |
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for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { |
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out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]); |
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} |
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if (ExtraByteCount > 0) { |
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u32 LastWord = 0; |
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u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount); |
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if (ExtraByteCount == 1) { |
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LastWord = ExtraBytesBuffer[0] << 24; |
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} else if (ExtraByteCount == 2) { |
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LastWord = ExtraBytesBuffer[0] << 24 | |
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ExtraBytesBuffer[1] << 16; |
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} else if (ExtraByteCount == 3) { |
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LastWord = ExtraBytesBuffer[0] << 24 | |
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ExtraBytesBuffer[1] << 16 | |
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ExtraBytesBuffer[2] << 8; |
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} |
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out_be32 (Emac.SendFifo.DataBaseAddress, LastWord); |
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} |
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/* Loop on the MAC's status to wait for any pause to complete */ |
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IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); |
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while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { |
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IntrStatus = in_be32 ((Emac.BaseAddress) + |
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XIIF_V123B_IISR_OFFSET); |
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/* Clear the pause status from the transmit status register */ |
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out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, |
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IntrStatus & XEM_EIR_XMIT_PAUSE_MASK); |
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} |
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/*
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* Set the MAC's transmit packet length register to tell it to transmit |
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*/ |
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out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len); |
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/*
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* Loop on the MAC's status to wait for the transmit to complete. |
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* The transmit status is in the FIFO when the XMIT_DONE bit is set. |
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*/ |
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do { |
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IntrStatus = in_be32 ((Emac.BaseAddress) + |
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XIIF_V123B_IISR_OFFSET); |
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} |
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while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); |
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XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET); |
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if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | |
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XEM_EIR_XMIT_LFIFO_OVER_MASK)) { |
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#ifdef DEBUG |
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puts ("Transmitting overrun error\n"); |
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#endif |
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return 0; |
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} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | |
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XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { |
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#ifdef DEBUG |
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puts ("Transmitting underrun error\n"); |
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#endif |
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return 0; |
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} |
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/* Clear the interrupt status register of transmit statuses */ |
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out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, |
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IntrStatus & XEM_EIR_XMIT_ALL_MASK); |
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/*
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* Collision errors are stored in the transmit status register |
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* instead of the interrupt status register |
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*/ |
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if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || |
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(XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) { |
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#ifdef DEBUG |
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puts ("Transmitting collision error\n"); |
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#endif |
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return 0; |
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} |
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return 1; |
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} |
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int eth_rx(void) |
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{ |
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u32 PktLength; |
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u32 IntrStatus; |
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u32 FifoCount; |
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u32 WordCount; |
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u32 ExtraByteCount; |
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u32 LastWord; |
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u8 *ExtraBytesBuffer; |
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if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) |
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& XPF_DEADLOCK_MASK) { |
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out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK); |
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#ifdef DEBUG |
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puts ("Receiving FIFO deadlock\n"); |
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#endif |
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return 0; |
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} |
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/*
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* Get the interrupt status to know what happened (whether an error occurred |
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* and/or whether frames have been received successfully). When clearing the |
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* intr status register, clear only statuses that pertain to receive. |
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*/ |
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IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET); |
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/*
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* Before reading from the length FIFO, make sure the length FIFO is not |
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* empty. We could cause an underrun error if we try to read from an |
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* empty FIFO. |
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*/ |
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if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) { |
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#ifdef DEBUG |
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/* puts("Receiving FIFO is empty\n"); */ |
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#endif |
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return 0; |
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} |
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/*
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* Determine, from the MAC, the length of the next packet available |
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* in the data FIFO (there should be a non-zero length here) |
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*/ |
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PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET); |
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if (!PktLength) { |
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return 0; |
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} |
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/*
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* Write the RECV_DONE bit in the status register to clear it. This bit |
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* indicates the RPLR is non-empty, and we know it's set at this point. |
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* We clear it so that subsequent entry into this routine will reflect |
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* the current status. This is done because the non-empty bit is latched |
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* in the IPIF, which means it may indicate a non-empty condition even |
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* though there is something in the FIFO. |
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*/ |
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out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, |
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XEM_EIR_RECV_DONE_MASK); |
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FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress + |
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XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; |
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if ((FifoCount * 4) < PktLength) { |
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#ifdef DEBUG |
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puts ("Receiving FIFO is smaller than packet size.\n"); |
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#endif |
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return 0; |
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} |
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WordCount = PktLength >> 2; |
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ExtraByteCount = PktLength & 0x3; |
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for (FifoCount = 0; FifoCount < WordCount; FifoCount++) { |
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etherrxbuff[FifoCount] = |
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in_be32 (Emac.RecvFifo.DataBaseAddress); |
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} |
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/*
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* if there are extra bytes to handle, read the last word from the FIFO |
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* and insert the extra bytes into the buffer |
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*/ |
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if (ExtraByteCount > 0) { |
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ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount); |
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LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress); |
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/*
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* one extra byte in the last word, put the byte into the next |
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* location of the buffer, bytes in a word of the FIFO are |
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* ordered from most significant byte to least |
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*/ |
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if (ExtraByteCount == 1) { |
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ExtraBytesBuffer[0] = (u8) (LastWord >> 24); |
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} else if (ExtraByteCount == 2) { |
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ExtraBytesBuffer[0] = (u8) (LastWord >> 24); |
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ExtraBytesBuffer[1] = (u8) (LastWord >> 16); |
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} else if (ExtraByteCount == 3) { |
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ExtraBytesBuffer[0] = (u8) (LastWord >> 24); |
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ExtraBytesBuffer[1] = (u8) (LastWord >> 16); |
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ExtraBytesBuffer[2] = (u8) (LastWord >> 8); |
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} |
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} |
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NetReceive((uchar *)etherrxbuff, PktLength); |
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return 1; |
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} |
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#endif |
@ -0,0 +1,128 @@ |
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/*
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* (C) Copyright 2007 Michal Simek |
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* |
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* Michal SIMEK <monstr@monstr.eu> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Based on Xilinx drivers |
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* |
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*/ |
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typedef struct { |
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u32 RegBaseAddress; /* Base address of registers */ |
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u32 DataBaseAddress; /* Base address of data for FIFOs */ |
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} XPacketFifoV100b; |
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typedef struct { |
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u32 BaseAddress; /* Base address (of IPIF) */ |
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u32 IsStarted; /* Device is currently started 0-no, 1-yes */ |
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XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */ |
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XPacketFifoV100b SendFifo; /* FIFO used to send frames */ |
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} XEmac; |
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ |
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#define XIIF_V123B_RESET_MASK 0xAUL |
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ |
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/* This constant is used with the Reset Register */ |
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#define XPF_RESET_FIFO_MASK 0x0000000A |
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#define XPF_COUNT_STATUS_REG_OFFSET 4UL |
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/* * These constants are used with the Occupancy/Vacancy Count Register. This
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* register also contains FIFO status */ |
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#define XPF_COUNT_MASK 0x0000FFFF |
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#define XPF_DEADLOCK_MASK 0x20000000 |
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/* Offset of the MAC registers from the IPIF base address */ |
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#define XEM_REG_OFFSET 0x1100UL |
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/*
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* Register offsets for the Ethernet MAC. Each register is 32 bits. |
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*/ |
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ |
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ |
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ |
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ |
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ |
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ |
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#define XEM_PFIFO_OFFSET 0x2000UL |
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#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */ |
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#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */ |
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#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */ |
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#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */ |
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/*
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* EMAC Interrupt Registers (Status and Enable) masks. These registers are |
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* part of the IPIF IP Interrupt registers |
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*/ |
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/* A mask for all transmit interrupts, used in polled mode */ |
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK | \ |
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK | \
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XEM_EIR_XMIT_LFIFO_FULL_MASK) |
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */ |
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */ |
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */ |
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */ |
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */ |
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */ |
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */ |
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo |
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* overrun */ |
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo |
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* underrun */ |
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo |
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* overrun */ |
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo |
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* underrun */ |
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo |
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* overrun */ |
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo |
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* underrun */ |
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt |
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* received */ |
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|
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/*
|
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* EMAC Control Register (ECR) |
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*/ |
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#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */ |
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#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */ |
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#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */ |
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#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */ |
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#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */ |
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#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */ |
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#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad |
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* insert */ |
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#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS |
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* insert */ |
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#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast |
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* addr */ |
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#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast |
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* addr */ |
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|
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/* Transmit Status Register (TSR) */ |
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */ |
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */ |
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Reference in new issue