Wolfgang Denk
18 years ago
commit
541d41b2f2
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o lcd.o update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,257 @@ |
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/*
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <command.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#define LCD_CMD_ADDR 0x50100002 |
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#define LCD_DATA_ADDR 0x50100003 |
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#define LCD_BLK_CTRL CPLD_REG1_ADDR |
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static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT"; |
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static int addr_flag = 0x80; |
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static void lcd_bl_ctrl(char val) |
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{ |
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out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val); |
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} |
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static void lcd_putc(int val) |
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{ |
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int i = 100; |
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char addr; |
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while (i--) { |
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ |
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udelay(50); |
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break; |
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} |
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udelay(50); |
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} |
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { |
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printf("LCD is busy\n"); |
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return; |
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} |
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addr = in_8((u8 *) LCD_CMD_ADDR); |
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udelay(50); |
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if ((addr != 0) && (addr % 0x10 == 0)) { |
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addr_flag ^= 0x40; |
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out_8((u8 *) LCD_CMD_ADDR, addr_flag); |
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} |
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udelay(50); |
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out_8((u8 *) LCD_DATA_ADDR, val); |
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udelay(50); |
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} |
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static void lcd_puts(char *s) |
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{ |
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char *p = s; |
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int i = 100; |
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while (i--) { |
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ |
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udelay(50); |
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break; |
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} |
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udelay(50); |
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} |
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { |
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printf("LCD is busy\n"); |
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return; |
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} |
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while (*p) |
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lcd_putc(*p++); |
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} |
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static void lcd_put_logo(void) |
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{ |
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int i = 100; |
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char *p = amcc_logo; |
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while (i--) { |
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ |
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udelay(50); |
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break; |
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} |
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udelay(50); |
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} |
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { |
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printf("LCD is busy\n"); |
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return; |
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} |
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out_8((u8 *) LCD_CMD_ADDR, 0x80); |
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while (*p) |
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lcd_putc(*p++); |
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} |
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int lcd_init(void) |
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{ |
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puts("LCD: "); |
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out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */ |
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udelay(50); |
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out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */ |
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udelay(50); |
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out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */ |
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udelay(2000); |
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out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */ |
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udelay(50); |
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lcd_bl_ctrl(0x02); /* set backlight on */ |
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lcd_put_logo(); |
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puts("ready\n"); |
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return 0; |
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} |
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static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
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{ |
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out_8((u8 *) LCD_CMD_ADDR, 0x01); |
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udelay(2000); |
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return 0; |
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} |
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static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
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{ |
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if (argc < 2) { |
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printf("%s", cmdtp->usage); |
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return 1; |
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} |
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lcd_puts(argv[1]); |
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return 0; |
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} |
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static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
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{ |
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if (argc < 2) { |
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printf("%s", cmdtp->usage); |
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return 1; |
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} |
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lcd_putc((char)argv[1][0]); |
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return 0; |
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} |
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static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
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{ |
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ulong count; |
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ulong dir; |
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char cur_addr; |
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if (argc < 3) { |
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printf("%s", cmdtp->usage); |
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return 1; |
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} |
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count = simple_strtoul(argv[1], NULL, 16); |
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if (count > 31) { |
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printf("unable to shift > 0x20\n"); |
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count = 0; |
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} |
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dir = simple_strtoul(argv[2], NULL, 16); |
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cur_addr = in_8((u8 *) LCD_CMD_ADDR); |
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udelay(50); |
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if (dir == 0x0) { |
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if (addr_flag == 0x80) { |
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if (count >= (cur_addr & 0xf)) { |
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out_8((u8 *) LCD_CMD_ADDR, 0x80); |
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udelay(50); |
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count = 0; |
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} |
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} else { |
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if (count >= ((cur_addr & 0x0f) + 0x0f)) { |
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out_8((u8 *) LCD_CMD_ADDR, 0x80); |
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addr_flag = 0x80; |
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udelay(50); |
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count = 0x0; |
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} else if (count >= ( cur_addr & 0xf)) { |
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count -= cur_addr & 0xf ; |
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out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf); |
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addr_flag = 0x80; |
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udelay(50); |
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} |
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} |
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} else { |
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if (addr_flag == 0x80) { |
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if (count >= (0x1f - (cur_addr & 0xf))) { |
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count = 0x0; |
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addr_flag = 0xc0; |
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out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf); |
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udelay(50); |
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} else if ((count + (cur_addr & 0xf ))>= 0x0f) { |
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count = count + (cur_addr & 0xf) - 0x0f; |
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addr_flag = 0xc0; |
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out_8((u8 *) LCD_CMD_ADDR, 0xc0); |
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udelay(50); |
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} |
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} else if ((count + (cur_addr & 0xf )) >= 0x0f) { |
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count = 0x0; |
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out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F); |
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udelay(50); |
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} |
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} |
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while (count--) { |
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if (dir == 0) |
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out_8((u8 *) LCD_CMD_ADDR, 0x10); |
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else |
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out_8((u8 *) LCD_CMD_ADDR, 0x14); |
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udelay(50); |
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} |
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return 0; |
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} |
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U_BOOT_CMD( |
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lcd_cls, 1, 1, do_lcd_clear, |
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"lcd_cls - lcd clear display\n", |
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NULL |
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); |
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U_BOOT_CMD( |
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lcd_puts, 2, 1, do_lcd_puts, |
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"lcd_puts - display string on lcd\n", |
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"<string> - <string> to be displayed\n" |
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); |
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U_BOOT_CMD( |
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lcd_putc, 2, 1, do_lcd_putc, |
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"lcd_putc - display char on lcd\n", |
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"<char> - <char> to be displayed\n" |
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); |
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U_BOOT_CMD( |
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lcd_cur, 3, 1, do_lcd_cur, |
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"lcd_cur - shift cursor on lcd\n", |
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"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n" |
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" <count> - 0..31\n" |
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" <dir> - 0=backward 1=forward\n" |
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); |
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@ -0,0 +1,240 @@ |
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/*
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* (C) Copyright 2000-2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2005-2007 |
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <spi.h> |
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#include <asm/gpio.h> |
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extern int lcd_init(void); |
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/*
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* board_early_init_f |
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*/ |
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int board_early_init_f(void) |
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{ |
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lcd_init(); |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); |
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mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ |
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mtdcr(uictr, 0x00000000); /* set int trigger levels */ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
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mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ |
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mtebc(pb3cr, CFG_EBC_PB3CR); |
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/*
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* Configure CPC0_PCI to enable PerWE as output |
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* and enable the internal PCI arbiter |
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*/ |
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mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); |
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return 0; |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard(void) |
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{ |
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char *s = getenv("serial#"); |
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puts("Board: Taihu - AMCC PPC405EP Evaluation Board"); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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putc('\n'); |
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return 0; |
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} |
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/*************************************************************************
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* long int initdram |
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* |
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************************************************************************/ |
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long int initdram(int board) |
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{ |
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return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */ |
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} |
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static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) |
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{ |
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char stat; |
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int i; |
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stat = in_8((u8 *) CPLD_REG0_ADDR); |
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printf("SW2 status: "); |
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for (i=0; i<4; i++) /* 4-position */ |
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printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); |
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printf("\n"); |
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return 0; |
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} |
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U_BOOT_CMD ( |
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sw2_stat, 1, 1, do_sw_stat, |
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"sw2_stat - show status of switch 2\n", |
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NULL |
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); |
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|
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static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) |
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{ |
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int led_no; |
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|
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if (argc != 3) { |
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printf("%s", cmd_tp->usage); |
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return -1; |
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} |
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led_no = simple_strtoul(argv[1], NULL, 16); |
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if (led_no != 1 && led_no != 2) { |
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printf("%s", cmd_tp->usage); |
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return -1; |
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} |
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|
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if (strcmp(argv[2],"off") == 0x0) { |
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if (led_no == 1) |
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gpio_write_bit(30, 1); |
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else |
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gpio_write_bit(31, 1); |
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} else if (strcmp(argv[2],"on") == 0x0) { |
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if (led_no == 1) |
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gpio_write_bit(30, 0); |
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else |
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gpio_write_bit(31, 0); |
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} else { |
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printf("%s", cmd_tp->usage); |
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return -1; |
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} |
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|
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return 0; |
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} |
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|
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U_BOOT_CMD ( |
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led_ctl, 3, 1, do_led_ctl, |
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"led_ctl - make led 1 or 2 on or off\n", |
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"<led_no> <on/off> - make led <led_no> on/off,\n" |
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"\tled_no is 1 or 2\t" |
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); |
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|
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#define SPI_CS_GPIO0 0 |
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#define SPI_SCLK_GPIO14 14 |
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#define SPI_DIN_GPIO15 15 |
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#define SPI_DOUT_GPIO16 16 |
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|
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void spi_scl(int bit) |
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{ |
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gpio_write_bit(SPI_SCLK_GPIO14, bit); |
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} |
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|
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void spi_sda(int bit) |
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{ |
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gpio_write_bit(SPI_DOUT_GPIO16, bit); |
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} |
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|
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unsigned char spi_read(void) |
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{ |
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return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15); |
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} |
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|
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void taihu_spi_chipsel(int cs) |
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{ |
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gpio_write_bit(SPI_CS_GPIO0, cs); |
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} |
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|
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spi_chipsel_type spi_chipsel[]= { |
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taihu_spi_chipsel |
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}; |
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|
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int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); |
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|
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#ifdef CONFIG_PCI |
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static unsigned char int_lines[32] = { |
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29, 30, 27, 28, 29, 30, 25, 27, |
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29, 30, 27, 28, 29, 30, 27, 28, |
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29, 30, 27, 28, 29, 30, 27, 28, |
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29, 30, 27, 28, 29, 30, 27, 28}; |
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|
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static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
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{ |
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unsigned char int_line = int_lines[PCI_DEV(dev) & 31]; |
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|
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); |
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} |
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|
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int pci_pre_init(struct pci_controller *hose) |
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{ |
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hose->fixup_irq = taihu_pci_fixup_irq; |
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return 1; |
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} |
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#endif /* CONFIG_PCI */ |
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|
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#ifdef CFG_DRAM_TEST |
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int testdram(void) |
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{ |
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unsigned long *mem = (unsigned long *)0; |
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const unsigned long kend = (1024 / sizeof(unsigned long)); |
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unsigned long k, n; |
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unsigned long msr; |
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unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024; |
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|
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msr = mfmsr(); |
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mtmsr(msr & ~(MSR_EE)); |
||||
|
||||
for (k = 0; k < total_kbytes ; |
||||
++k, mem += (1024 / sizeof(unsigned long))) { |
||||
if ((k & 1023) == 0) |
||||
printf("%3d MB\r", k / 1024); |
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0xaaaaaaaa) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
memset(mem, 0x55555555, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0x55555555) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
} |
||||
printf("SDRAM test passes\n"); |
||||
mtmsr(msr); |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CFG_DRAM_TEST */ |
||||
@ -0,0 +1,150 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,132 @@ |
||||
/*
|
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <i2c.h> |
||||
|
||||
#define PCI_M66EN 0x10 |
||||
|
||||
static uchar buf_33[] = |
||||
{ |
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ |
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/ |
||||
0x14, |
||||
0x00, /* 0x0f~0x10:device id 0x0000*/ |
||||
0x00, |
||||
0x00, /* 0x11:revision 0x00 */ |
||||
0x00, /* 0x12~0x14:class 0x000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x10, /* 0x15~0x16:subsystem vendor id */ |
||||
0xe8, |
||||
0x00, /* 0x17~0x18:subsystem device id */ |
||||
0x00, |
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ |
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ |
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ |
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ |
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */ |
||||
0x00, |
||||
0x00 |
||||
}; |
||||
|
||||
static uchar buf_66[] = |
||||
{ |
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/ |
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/ |
||||
0x14, |
||||
0x00, /* 0x0f~0x10:device id 0x0000*/ |
||||
0x00, |
||||
0x00, /* 0x11:revision 0x00 */ |
||||
0x00, /* 0x12~0x14:class 0x000000 */ |
||||
0x00, |
||||
0x00, |
||||
0x10, /* 0x15~0x16:subsystem vendor id */ |
||||
0xe8, |
||||
0x00, /* 0x17~0x18:subsystem device id */ |
||||
0x00, |
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */ |
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */ |
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */ |
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */ |
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */ |
||||
0x00, |
||||
0x00 |
||||
}; |
||||
|
||||
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
ulong len = 0x20; |
||||
uchar chip = CFG_I2C_EEPROM_ADDR; |
||||
uchar *pbuf; |
||||
uchar base; |
||||
int i; |
||||
|
||||
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) { |
||||
pbuf = buf_33; |
||||
base = 0x00; |
||||
} else { |
||||
pbuf = buf_66; |
||||
base = 0x40; |
||||
} |
||||
|
||||
for (i = 0; i< len; i++, base++) { |
||||
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) { |
||||
printf("i2c_write fail\n"); |
||||
return 1; |
||||
} |
||||
udelay(11000); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD ( |
||||
update_boot_eeprom, 1, 1, update_boot_eeprom, |
||||
"update_boot_eeprom - update boot eeprom content\n", |
||||
NULL |
||||
); |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,528 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Modified 4/5/2001 |
||||
* Wait for completion of each sector erase command issued |
||||
* 4/5/2001 |
||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com |
||||
* |
||||
* Modified 6/6/2007 |
||||
* Added isync |
||||
* Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#if CFG_MAX_FLASH_BANKS != 1 |
||||
#error "CFG_MAX_FLASH_BANKS must be 1" |
||||
#endif |
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
||||
static int write_word (flash_info_t * info, ulong dest, ulong data); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
|
||||
#define ADDR0 0x5555 |
||||
#define ADDR1 0x2aaa |
||||
#define FLASH_WORD_SIZE unsigned char |
||||
|
||||
/*-----------------------------------------------------------------------*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
unsigned long size_b0; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
flash_info[0].flash_id = FLASH_UNKNOWN; |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, |
||||
&flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n", |
||||
size_b0, size_b0 << 20); |
||||
} |
||||
|
||||
/* Only one bank */ |
||||
/* Setup offsets */ |
||||
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
(void) flash_protect (FLAG_PROTECT_SET, |
||||
FLASH_BASE0_PRELIM, |
||||
FLASH_BASE0_PRELIM + monitor_flash_len - 1, |
||||
&flash_info[0]); |
||||
flash_info[0].size = size_b0; |
||||
|
||||
return size_b0; |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/ |
||||
/*
|
||||
* This implementation assumes that the flash chips are uniform sector |
||||
* devices. This is true for all likely flash devices on a HCUx. |
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t * info) |
||||
{ |
||||
unsigned idx; |
||||
unsigned long sector_size = info->size / info->sector_count; |
||||
|
||||
for (idx = 0; idx < info->sector_count; idx += 1) { |
||||
info->start[idx] = base + (idx * sector_size); |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------*/ |
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
int k; |
||||
int size; |
||||
int erased; |
||||
volatile unsigned long *flash; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: |
||||
printf ("AMD "); |
||||
break; |
||||
case FLASH_MAN_FUJ: |
||||
printf ("FUJITSU "); |
||||
break; |
||||
case FLASH_MAN_SST: |
||||
printf ("SST "); |
||||
break; |
||||
case FLASH_MAN_STM: |
||||
printf ("ST Micro "); |
||||
break; |
||||
default: |
||||
printf ("Unknown Vendor "); |
||||
break; |
||||
} |
||||
|
||||
/* (Reduced table of only parts expected in HCUx boards.) */ |
||||
switch (info->flash_id) { |
||||
case FLASH_MAN_AMD | FLASH_AM040: |
||||
printf ("AM29F040 (512 Kbit, uniform sector size)\n"); |
||||
break; |
||||
case FLASH_MAN_STM | FLASH_AM040: |
||||
printf ("MM29W040W (512 Kbit, uniform sector size)\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n", |
||||
info->size >> 10, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; ++i) { |
||||
/*
|
||||
* Check if whole sector is erased |
||||
*/ |
||||
if (i != (info->sector_count - 1)) |
||||
size = info->start[i + 1] - info->start[i]; |
||||
else |
||||
size = info->start[0] + info->size - info->start[i]; |
||||
erased = 1; |
||||
flash = (volatile unsigned long *) info->start[i]; |
||||
size = size >> 2; /* divide by 4 for longword access */ |
||||
for (k = 0; k < size; k++) { |
||||
if (*flash++ != 0xffffffff) { |
||||
erased = 0; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s%s", |
||||
info->start[i], |
||||
erased ? " E" : " ", info->protect[i] ? "RO " : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info) |
||||
{ |
||||
short i; |
||||
FLASH_WORD_SIZE value; |
||||
ulong base = (ulong) addr; |
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
asm("isync"); |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
asm("isync"); |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
asm("isync"); |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; |
||||
asm("isync"); |
||||
|
||||
value = addr2[0]; |
||||
asm("isync"); |
||||
|
||||
switch (value) { |
||||
case (FLASH_WORD_SIZE) AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case (FLASH_WORD_SIZE) FUJ_MANUFACT: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
case (FLASH_WORD_SIZE) SST_MANUFACT: |
||||
info->flash_id = FLASH_MAN_SST; |
||||
break; |
||||
case (FLASH_WORD_SIZE)STM_MANUFACT: |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
printf("Unknown flash manufacturer code: 0x%x at %p\n", |
||||
value, addr); |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
value = addr2[1]; /* device ID */ |
||||
|
||||
switch (value) { |
||||
case (FLASH_WORD_SIZE) AMD_ID_F040B: |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x0080000; /* => 512 ko */ |
||||
break; |
||||
case (FLASH_WORD_SIZE) AMD_ID_LV040B: |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x0080000; /* => 512 ko */ |
||||
break; |
||||
case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */ |
||||
info->flash_id += FLASH_AM040; |
||||
info->sector_count = 8; |
||||
info->size = 0x0080000; /* => 512 ko */ |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
/* Calculate the sector offsets (Use HCUx Optimized code). */ |
||||
flash_get_offsets(base, info); |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address,
|
||||
*(A7 .. A0) = 0x02 |
||||
* D0 = 1 if protected |
||||
*/ |
||||
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); |
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) |
||||
info->protect[i] = 0; |
||||
else |
||||
info->protect[i] = addr2[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
addr2 = (FLASH_WORD_SIZE *) info->start[0]; |
||||
*addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
int wait_for_DQ7 (flash_info_t * info, int sect) |
||||
{ |
||||
ulong start, now, last; |
||||
volatile FLASH_WORD_SIZE *addr = |
||||
(FLASH_WORD_SIZE *) (info->start[sect]); |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != |
||||
(FLASH_WORD_SIZE) 0x00800080) { |
||||
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return -1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------*/ |
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); |
||||
volatile FLASH_WORD_SIZE *addr2; |
||||
int flag, prot, sect, l_sect; |
||||
int i; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("Can't erase unknown flash type - aborted\n"); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect = s_first; sect <= s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors not erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect <= s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); |
||||
printf ("Erasing sector %p\n", addr2); /* CLH */ |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == |
||||
FLASH_MAN_SST) { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
/* block erase */ |
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; |
||||
for (i = 0; i < 50; i++) udelay (1000); |
||||
} else { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
/* sector erase */ |
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; |
||||
} |
||||
l_sect = sect; |
||||
/*
|
||||
* Wait for each sector to complete, it's more |
||||
* reliable. According to AMD Spec, you must |
||||
* issue all erase commands within a specified |
||||
* timeout. This has been seen to fail, especially |
||||
* if printf()s are included (for debug)!! |
||||
*/ |
||||
wait_for_DQ7 (info, sect); |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
#if 0 |
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
wait_for_DQ7 (info, l_sect); |
||||
|
||||
DONE: |
||||
#endif |
||||
/* reset to read mode */ |
||||
addr = (FLASH_WORD_SIZE *) info->start[0]; |
||||
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
for (; i < 4 && cnt > 0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt == 0 && i < 4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
if ((rc = write_word (info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i = 0; i < 4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word (info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i < 4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *) cp); |
||||
} |
||||
|
||||
return (write_word (info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t * info, ulong dest, ulong data) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr2 = |
||||
(FLASH_WORD_SIZE *) (info->start[0]); |
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; |
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; |
||||
ulong start; |
||||
int i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) & |
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { |
||||
return (2); |
||||
} |
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { |
||||
int flag; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; |
||||
|
||||
dest2[i] = data2[i]; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != |
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { |
||||
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
@ -0,0 +1,41 @@ |
||||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* |
||||
* This source code is free software; you can redistribute it |
||||
* and/or modify it in source code form under the terms of the GNU |
||||
* General Public License as published by the Free Software |
||||
* Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
|
||||
#ifdef CONFIG_CMD_BSP |
||||
/*
|
||||
* Command nm_bsp: Netstal Maschinen BSP specific command |
||||
*/ |
||||
int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__, |
||||
flag, argc, argv[0]); |
||||
printf("Netstal Maschinen BSP specific command. None at the moment.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
nm_bsp, 1, 1, nm_bsp, |
||||
"nm_bsp - Netstal Maschinen BSP specific command. \n", |
||||
"Help for Netstal Maschinen BSP specific command.\n" |
||||
); |
||||
#endif |
||||
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2007 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
vpath flash.c ../common |
||||
COBJS = $(BOARD).o flash.o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,59 @@ |
||||
HCU4 Configuration Details |
||||
|
||||
Memory Bank 0 -- Flash chip |
||||
--------------------------- |
||||
|
||||
0xfff00000 - 0xffffffff |
||||
|
||||
The flash chip is really only 512Kbytes, but the high address bit of |
||||
the 1Meg region is ignored, so the flash is replicated through the |
||||
region. Thus, this is consistent with a flash base address 0xfff80000. |
||||
|
||||
The placement at the end is to be consistent with reset behavior, |
||||
where the processor itself initially uses this bus to load the branch |
||||
vector and start running. |
||||
|
||||
On-Chip Memory |
||||
-------------- |
||||
|
||||
0xf4000000 - 0xf4000fff |
||||
|
||||
The 405GPr includes a 4K on-chip memory that can be placed however |
||||
software chooses. I choose to place the memory at this address, to |
||||
keep it out of the cachable areas. |
||||
|
||||
|
||||
Internal Peripherals |
||||
-------------------- |
||||
|
||||
0xef600300 - 0xef6008ff |
||||
|
||||
These are scattered various peripherals internal to the PPC405GPr |
||||
chip. |
||||
|
||||
Chip-Select 2: Flash Memory |
||||
--------------------------- |
||||
|
||||
0x70000000 |
||||
|
||||
Chip-Select 3: CAN Interface |
||||
---------------------------- |
||||
0x7800000 |
||||
|
||||
|
||||
Chip-Select 4: IMC-bus standard |
||||
------------------------------- |
||||
|
||||
Our IO-Bus (slow version) |
||||
|
||||
|
||||
Chip-Select 5: IMC-bus fast (inactive) |
||||
-------------------------------------- |
||||
|
||||
Our IO-Bus (fast, but not yet use) |
||||
|
||||
|
||||
Memory Bank 1 -- SDRAM |
||||
------------------------------------- |
||||
|
||||
0x00000000 - 0x1ffffff # Default 32 MB |
||||
@ -0,0 +1,28 @@ |
||||
#
|
||||
# (C) Copyright 2005 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Netstal Maschinen AG: HCU4 boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFa0000
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG -g
|
||||
endif |
||||
@ -0,0 +1,400 @@ |
||||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* |
||||
* This source code is free software; you can redistribute it |
||||
* and/or modify it in source code form under the terms of the GNU |
||||
* General Public License as published by the Free Software |
||||
* Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ppc4xx.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm-ppc/u-boot.h> |
||||
#include "../common/nm_bsp.c" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000) |
||||
|
||||
#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */ |
||||
|
||||
#define DO_UGLY_SDRAM_WORKAROUND |
||||
|
||||
enum { |
||||
/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */ |
||||
HW_GENERATION_HCU2 = 0x10, |
||||
HW_GENERATION_HCU3 = 0x10, |
||||
HW_GENERATION_HCU4 = 0x20, |
||||
HW_GENERATION_MCU = 0x08, |
||||
HW_GENERATION_MCU20 = 0x0a, |
||||
HW_GENERATION_MCU25 = 0x09, |
||||
}; |
||||
|
||||
void sysLedSet(u32 value); |
||||
long int spd_sdram(int(read_spd)(uint addr)); |
||||
|
||||
#ifdef CONFIG_SPD_EEPROM |
||||
#define DEBUG |
||||
#endif |
||||
|
||||
#if defined(DEBUG) |
||||
void show_sdram_registers(void); |
||||
#endif |
||||
|
||||
/*
|
||||
* This function is run very early, out of flash, and before devices are |
||||
* initialized. It is called by lib_ppc/board.c:board_init_f by virtue |
||||
* of being in the init_sequence array. |
||||
* |
||||
* The SDRAM has been initialized already -- start.S:start called |
||||
* init.S:init_sdram early on -- but it is not yet being used for |
||||
* anything, not even stack. So be careful. |
||||
*/ |
||||
|
||||
#define CPC0_CR0 0xb1 /* Chip control register 0 */ |
||||
#define CPC0_CR1 0xb2 /* Chip control register 1 */ |
||||
/* Attention: If you want 1 microsecs times from the external oscillator
|
||||
* use 0x00804051. But this causes problems with u-boot and linux! |
||||
*/ |
||||
#define CPC0_CR1_VALUE 0x00004051 |
||||
#define CPC0_ECR 0xaa /* Edge condition register */ |
||||
#define EBC0_CFG 0x23 /* External Peripheral Control Register */ |
||||
#define CPC0_EIRR 0xb6 /* External Interrupt Register */ |
||||
|
||||
|
||||
int board_early_init_f (void) |
||||
{ |
||||
/*-------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the HCU4 board. |
||||
| Note: IRQ 0-15 405GP internally generated; high; level sensitive |
||||
| IRQ 16 405GP internally generated; low; level sensitive |
||||
| IRQ 17-24 RESERVED/UNUSED |
||||
| IRQ 31 (EXT IRQ 6) (unused) |
||||
+-------------------------------------------------------------------*/ |
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr (uicer, 0x00000000); /* disable all ints */ |
||||
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ |
||||
mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */ |
||||
mtdcr (uictr, 0x10000000); /* set int trigger levels */ |
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
|
||||
mtdcr(CPC0_CR1, CPC0_CR1_VALUE); |
||||
mtdcr(CPC0_ECR, 0x60606000); |
||||
mtdcr(CPC0_EIRR, 0x7c000000); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_BOARD_PRE_INIT |
||||
int board_pre_init (void) |
||||
{ |
||||
return board_early_init_f (); |
||||
} |
||||
#endif |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
unsigned int j; |
||||
u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER; |
||||
u16 generation = *boardVersReg & 0xf0; |
||||
u16 index = *boardVersReg & 0x0f; |
||||
|
||||
/* Force /RTS to active. The board it not wired quite
|
||||
correctly to use cts/rtc flow control, so just force the |
||||
/RST active and forget about it. */ |
||||
writeb (readb (0xef600404) | 0x03, 0xef600404); |
||||
printf ("\nNetstal Maschinen AG "); |
||||
if (generation == HW_GENERATION_HCU3) |
||||
printf ("HCU3: index %d\n\n", index); |
||||
else if (generation == HW_GENERATION_HCU4) |
||||
printf ("HCU4: index %d\n\n", index); |
||||
/* GPIO here noch nicht richtig initialisert !!! */ |
||||
sysLedSet(0); |
||||
for (j = 0; j < 7; j++) { |
||||
sysLedSet(1 << j); |
||||
udelay(50 * 1000); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 sysLedGet(void) |
||||
{ |
||||
return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff; |
||||
} |
||||
|
||||
void sysLedSet(u32 value /* value to place in LEDs */) |
||||
{ |
||||
u32 tmp = ~value; |
||||
u32 *ledReg; |
||||
|
||||
tmp = (tmp << 23) | 0x7FFFFF; |
||||
ledReg = (u32 *)GPIO0_OR; |
||||
*ledReg = tmp; |
||||
} |
||||
|
||||
/*
|
||||
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram |
||||
* used for HCUx |
||||
*/ |
||||
void sdram_init(void) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
#if defined(DEBUG) |
||||
void show_sdram_registers(void) |
||||
{ |
||||
u32 value; |
||||
|
||||
printf ("SDRAM Controller Registers --\n"); |
||||
mfsdram(mem_mcopt1, value); |
||||
printf (" SDRAM0_CFG : 0x%08x\n", value); |
||||
mfsdram(mem_status, value); |
||||
printf (" SDRAM0_STATUS: 0x%08x\n", value); |
||||
mfsdram(mem_mb0cf, value); |
||||
printf (" SDRAM0_B0CR : 0x%08x\n", value); |
||||
mfsdram(mem_mb1cf, value); |
||||
printf (" SDRAM0_B1CR : 0x%08x\n", value); |
||||
mfsdram(mem_sdtr1, value); |
||||
printf (" SDRAM0_TR : 0x%08x\n", value); |
||||
mfsdram(mem_rtr, value); |
||||
printf (" SDRAM0_RTR : 0x%08x\n", value); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* this is even after checkboard. It returns the size of the SDRAM |
||||
* that we have installed. This function is called by board_init_f |
||||
* in lib_ppc/board.c to initialize the memory and return what I |
||||
* found. These are default value, which will be overridden later. |
||||
*/ |
||||
|
||||
long int fixed_hcu4_sdram (int board_type) |
||||
{ |
||||
#ifdef DEBUG |
||||
printf (__FUNCTION__); |
||||
#endif |
||||
/* disable memory controller */ |
||||
mtdcr (memcfga, mem_mcopt1); |
||||
mtdcr (memcfgd, 0x00000000); |
||||
|
||||
udelay (500); |
||||
|
||||
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ |
||||
mtdcr (memcfga, mem_besra); |
||||
mtdcr (memcfgd, 0xffffffff); |
||||
|
||||
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ |
||||
mtdcr (memcfga, mem_besrb); |
||||
mtdcr (memcfgd, 0xffffffff); |
||||
|
||||
/* Clear SDRAM0_ECCCFG (disable ECC) */ |
||||
mtdcr (memcfga, mem_ecccf); |
||||
mtdcr (memcfgd, 0x00000000); |
||||
|
||||
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ |
||||
mtdcr (memcfga, mem_eccerr); |
||||
mtdcr (memcfgd, 0xffffffff); |
||||
|
||||
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
|
||||
* TODO ngngng |
||||
*/ |
||||
mtdcr (memcfga, mem_sdtr1); |
||||
mtdcr (memcfgd, 0x008a4015); |
||||
|
||||
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
|
||||
* TODO ngngng |
||||
*/ |
||||
mtdcr (memcfga, mem_mb0cf); |
||||
mtdcr (memcfgd, 0x00062001); |
||||
|
||||
/* refresh timer = 0x400 */ |
||||
mtdcr (memcfga, mem_rtr); |
||||
mtdcr (memcfgd, 0x04000000); |
||||
|
||||
/* Power management idle timer set to the default. */ |
||||
mtdcr (memcfga, mem_pmit); |
||||
mtdcr (memcfgd, 0x07c00000); |
||||
|
||||
udelay (500); |
||||
|
||||
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */ |
||||
mtdcr (memcfga, mem_mcopt1); |
||||
mtdcr (memcfgd, 0x90800000); |
||||
|
||||
#ifdef DEBUG |
||||
printf ("%s: done\n", __FUNCTION__); |
||||
#endif |
||||
return SDRAM_LEN; |
||||
} |
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* getSerialNr |
||||
*---------------------------------------------------------------------------*/ |
||||
static u32 getSerialNr(void) |
||||
{ |
||||
u32 *serial = (u32 *)CFG_FLASH_BASE; |
||||
|
||||
if (*serial == 0xffffffff) |
||||
return get_ticks(); |
||||
|
||||
return *serial; |
||||
} |
||||
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* misc_init_r. |
||||
*---------------------------------------------------------------------------*/ |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
char *s = getenv("ethaddr"); |
||||
char *e; |
||||
int i; |
||||
u32 serial = getSerialNr(); |
||||
|
||||
for (i = 0; i < 6; ++i) { |
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0; |
||||
if (s) |
||||
s = (*e) ? e + 1 : e; |
||||
} |
||||
|
||||
if (gd->bd->bi_enetaddr[3] == 0 && |
||||
gd->bd->bi_enetaddr[4] == 0 && |
||||
gd->bd->bi_enetaddr[5] == 0) { |
||||
char ethaddr[22]; |
||||
/* [0..3] Must be in sync with CONFIG_ETHADDR */ |
||||
gd->bd->bi_enetaddr[0] = 0x00; |
||||
gd->bd->bi_enetaddr[1] = 0x60; |
||||
gd->bd->bi_enetaddr[2] = 0x13; |
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; |
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; |
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff; |
||||
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", |
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], |
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], |
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; |
||||
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, |
||||
ethaddr, serial); |
||||
setenv ("ethaddr", ethaddr); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef DO_UGLY_SDRAM_WORKAROUND |
||||
#include "i2c.h" |
||||
|
||||
void set_spd_default_value(unsigned int spd_addr,uchar def_val) |
||||
{ |
||||
uchar value; |
||||
int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ; |
||||
|
||||
if (res == 0 && value == 0xff) { |
||||
res = i2c_write(SPD_EEPROM_ADDRESS, |
||||
spd_addr, 1, &def_val, 1) ; |
||||
#ifdef DEBUG |
||||
printf("%s: Setting spd offset %3d to %3d res %d\n", |
||||
__FUNCTION__, spd_addr, def_val, res); |
||||
#endif |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
dram_size = fixed_hcu4_sdram(); |
||||
#else |
||||
#ifdef DO_UGLY_SDRAM_WORKAROUND |
||||
/* Workaround if you have no working I2C-EEPROM-SPD-configuration */ |
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
set_spd_default_value(2, 4); /* SDRAM Type */ |
||||
set_spd_default_value(7, 0); /* module width, high byte */ |
||||
set_spd_default_value(12, 1); /* Refresh or 0x81 */ |
||||
|
||||
/* Only correct for HCU3 with 32 MB RAM*/ |
||||
/* Number of bytes used by module manufacturer */ |
||||
set_spd_default_value( 0, 128); |
||||
set_spd_default_value( 1, 11 ); /* Total SPD memory size */ |
||||
set_spd_default_value( 2, 4 ); /* Memory type */ |
||||
set_spd_default_value( 3, 12 ); /* Number of row address bits */ |
||||
set_spd_default_value( 4, 9 ); /* Number of column address bits */ |
||||
set_spd_default_value( 5, 1 ); /* Number of module rows */ |
||||
set_spd_default_value( 6, 32 ); /* Module data width, LSB */ |
||||
set_spd_default_value( 7, 0 ); /* Module data width, MSB */ |
||||
set_spd_default_value( 8, 1 ); /* Module interface signal levels */ |
||||
/* SDRAM cycle time for highest CL (Tclk) */ |
||||
set_spd_default_value( 9, 112); |
||||
/* SDRAM access time from clock for highest CL (Tac) */ |
||||
set_spd_default_value(10, 84 ); |
||||
set_spd_default_value(11, 2 ); /* Module configuration type */ |
||||
set_spd_default_value(12, 128); /* Refresh rate/type */ |
||||
set_spd_default_value(13, 16 ); /* Primary SDRAM width */ |
||||
set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */ |
||||
/* SDRAM device attributes, min clock delay for back to back */ |
||||
/*random column addresses (Tccd) */ |
||||
set_spd_default_value(15, 1 ); |
||||
/* SDRAM device attributes, burst lengths supported */ |
||||
set_spd_default_value(16, 143); |
||||
/* SDRAM device attributes, number of banks on SDRAM device */ |
||||
set_spd_default_value(17, 4 ); |
||||
/* SDRAM device attributes, CAS latency */ |
||||
set_spd_default_value(18, 6 ); |
||||
/* SDRAM device attributes, CS latency */ |
||||
set_spd_default_value(19, 1 ); |
||||
/* SDRAM device attributes, WE latency */ |
||||
set_spd_default_value(20, 1 ); |
||||
set_spd_default_value(21, 0 ); /* SDRAM module attributes */ |
||||
/* SDRAM device attributes, general */ |
||||
set_spd_default_value(22, 14 ); |
||||
/* SDRAM cycle time for 2nd highest CL (Tclk) */ |
||||
set_spd_default_value(23, 117); |
||||
/* SDRAM access time from clock for2nd highest CL (Tac) */ |
||||
set_spd_default_value(24, 84 ); |
||||
/* SDRAM cycle time for 3rd highest CL (Tclk) */ |
||||
set_spd_default_value(25, 0 ); |
||||
/* SDRAM access time from clock for3rd highest CL (Tac) */ |
||||
set_spd_default_value(26, 0 ); |
||||
set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */ |
||||
/* Minimum row active to row active delay (Trrd) */ |
||||
set_spd_default_value(28, 14 ); |
||||
set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */ |
||||
set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */ |
||||
set_spd_default_value(31, 8 ); /* Module bank density */ |
||||
/* Command and Address signal input setup time */ |
||||
set_spd_default_value(32, 21 ); |
||||
/* Command and Address signal input hold time */ |
||||
set_spd_default_value(33, 8 ); |
||||
set_spd_default_value(34, 21 ); /* Data signal input setup time */ |
||||
set_spd_default_value(35, 8 ); /* Data signal input hold time */ |
||||
#endif /* DO_UGLY_SDRAM_WORKAROUND */ |
||||
dram_size = spd_sdram(0); |
||||
#endif |
||||
|
||||
#ifdef DEBUG |
||||
show_sdram_registers(); |
||||
#endif |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
bcu4_testdram(dram_size); |
||||
printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024)); |
||||
#endif |
||||
|
||||
return dram_size; |
||||
} |
||||
@ -0,0 +1,140 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : { |
||||
/* The start.o file includes the initial jump vector that |
||||
must be located in the beginning. It is the basic run- |
||||
time function that calls all other functions. */ |
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,49 @@ |
||||
#
|
||||
# (C) Copyright 2007 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
vpath flash.c ../common |
||||
COBJS = $(BOARD).o sdram.o flash.o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,174 @@ |
||||
HCU5 configuration details and startup sequence |
||||
|
||||
(C) Copyright 2007 Netstal Maschinen AG |
||||
Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
|
||||
TODO: |
||||
----- |
||||
- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT ! |
||||
- Does not occur if both EMAC are connected |
||||
- Fix RTS/CTS problem (HW?) |
||||
CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after |
||||
Switching to interrupt driven serial input mode |
||||
- Make vxWorks start from u-boot. Possible reasons |
||||
- Does vxWorks need an entry for the Machine Check interrupt like this |
||||
tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ? |
||||
|
||||
Caveats: |
||||
-------- |
||||
Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c) |
||||
see hcu5.c. |
||||
|
||||
|
||||
Memory Bank 0 -- Flash chip |
||||
--------------------------- |
||||
|
||||
0xfff00000 - 0xffffffff |
||||
|
||||
The flash chip is really only 512Kbytes, but the high address bit of |
||||
the 1Meg region is ignored, so the flash is replicated through the |
||||
region. Thus, this is consistent with a flash base address 0xfff80000. |
||||
|
||||
The placement at the end is to be consistent with reset behavior, |
||||
where the processor itself initially uses this bus to load the branch |
||||
vector and start running. |
||||
|
||||
On-Chip Memory |
||||
-------------- |
||||
|
||||
0xe0010000- 0xe0013fff CFG_OCM_BASE |
||||
The 440EPx includes a 16K on-chip memory that can be placed however |
||||
software chooses. |
||||
|
||||
Internal Peripherals |
||||
-------------------- |
||||
|
||||
0xef600300 - 0xef6008ff |
||||
|
||||
These are scattered various peripherals internal to the PPC440EPX |
||||
chip. |
||||
|
||||
Chip-Select 2: Flash Memory |
||||
--------------------------- |
||||
|
||||
Not used |
||||
|
||||
Chip-Select 3: CAN Interface |
||||
---------------------------- |
||||
0xc800000: 2 Intel 82527 CAN-Controller |
||||
|
||||
|
||||
Chip-Select 4: IMC-bus standard |
||||
------------------------------- |
||||
|
||||
0xcc00000: Netstal specific IO-Bus |
||||
|
||||
|
||||
Chip-Select 5: IMC-bus fast (inactive) |
||||
-------------------------------------- |
||||
|
||||
0xce00000: Netstal specific IO-Bus (fast, but not yet used) |
||||
|
||||
|
||||
Memory Bank 1 -- DDR2 |
||||
------------------------------------- |
||||
|
||||
0x00000000 - 0xfffffff # Default 256 MB |
||||
|
||||
PCI ?? |
||||
|
||||
USB ?? |
||||
Only USB_STORAGE is enabled to load vxWorks |
||||
from a memory stick. |
||||
|
||||
System-LEDs ??? (Analog zu HCU4 ???) |
||||
|
||||
Startup sequence |
||||
---------------- |
||||
|
||||
(cpu/ppc4xx/resetvec.S) |
||||
depending on configs option |
||||
call _start_440 _start_pci oder _start |
||||
|
||||
(cpu/ppc4xx/start.S) |
||||
|
||||
_start_440: |
||||
initialize register like |
||||
CCR0 |
||||
debug |
||||
setup interrupt vectors |
||||
configure cache regions |
||||
clear and setup TLB |
||||
enable internal RAM |
||||
jump start_ram |
||||
which in turn will jump to start |
||||
_start: |
||||
Clear and set up some registers. |
||||
Debug setup |
||||
Setup the internal SRAM |
||||
Setup the stack in internal SRAM |
||||
setup stack pointer (r1) |
||||
setup GOT |
||||
call cpu_init_f /* run low-level CPU init code (from Flash) */ |
||||
|
||||
call cpu_init_f |
||||
board_init_f: (lib_ppc\board.c) |
||||
init_sequence defines a list of function to be called |
||||
board_early_init_f: (board/netstal/hcu5/hcu5.c) |
||||
We are using Bootstrap-Option A |
||||
if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot |
||||
Setup the GPIO pins |
||||
Setup the interrupt controller polarities, triggers, etc. |
||||
Ethernet, PCI, USB enable |
||||
setup BOOT FLASH (Chip timing) |
||||
init_baudrate, |
||||
serial_init |
||||
checkcpu |
||||
misc_init_f #ifdef |
||||
init_func_i2c #ifdef |
||||
post_init_f #ifdef |
||||
init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c |
||||
(EYE function removed!!) |
||||
test_dram call |
||||
|
||||
* Reserve memory at end of RAM for (top down in that order): |
||||
* - kernel log buffer |
||||
* - protected RAM |
||||
* - LCD framebuffer |
||||
* - monitor code |
||||
* - board info struct |
||||
Save local variables to board info struct |
||||
call relocate_code() does not return |
||||
relocate_code: (cpu/ppc4xx/start.S) |
||||
------------------------------------------------------- |
||||
From now on our copy is in RAM and we will run from there, |
||||
starting with board_init_r |
||||
------------------------------------------------------- |
||||
board_init_r: (lib_ppc\board.c) |
||||
setup bd function pointers |
||||
trap_init |
||||
flash_init: (board/netstal/hcu5/flash.c) |
||||
/* setup for u-boot erase, update */ |
||||
setup bd flash info |
||||
cpu_init_r: (cpu/ppc4xx/cpu_init.c) |
||||
peripheral chip select in using defines like |
||||
CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h |
||||
mem_malloc_init |
||||
malloc_bin_reloc |
||||
spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) |
||||
env_relocated |
||||
misc_init_r(bd): (board/netstal/hcu5.c) |
||||
ethaddr mit serial number ergänzen |
||||
Then we will somehow go into the command loop |
||||
|
||||
Most of the HW specific code for the HCU5 may be found in |
||||
include/configs/hcu5.h |
||||
board/netstal/hcu5/* |
||||
cpu/ppc4xx/* |
||||
lib_ppc/* |
||||
include/ppc440.h |
||||
|
||||
Drivers for serial etc are found under drivers/ |
||||
|
||||
Don't ask question if you did not look at the README !! |
||||
Most CFG_* and CONFIG_* switches are mentioned/explained there. |
||||
@ -0,0 +1,30 @@ |
||||
#
|
||||
# (C) Copyright 2005 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Netstal Maschinen AG: HCU5 boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFa0000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1) |
||||
PLATFORM_CPPFLAGS += -DDEBUG -g
|
||||
endif |
||||
@ -0,0 +1,525 @@ |
||||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* |
||||
* This source code is free software; you can redistribute it |
||||
* and/or modify it in source code form under the terms of the GNU |
||||
* General Public License as published by the Free Software |
||||
* Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <ppc440.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void sysLedSet(u32 value); |
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
||||
|
||||
#undef BOOTSTRAP_OPTION_A_ACTIVE |
||||
|
||||
#define SDR0_CP440 0x0180 |
||||
|
||||
#define SYSTEM_RESET 0x30000000 |
||||
#define CHIP_RESET 0x20000000 |
||||
|
||||
#define SDR0_ECID0 0x0080 |
||||
#define SDR0_ECID1 0x0081 |
||||
#define SDR0_ECID2 0x0082 |
||||
#define SDR0_ECID3 0x0083 |
||||
|
||||
#define SYS_IO_ADDRESS 0xcce00000 |
||||
|
||||
#define DEFAULT_ETH_ADDR "ethaddr" |
||||
/* ethaddr for first or etha1ddr for second ethernet */ |
||||
|
||||
enum { |
||||
/* HW_GENERATION_HCU1 is no longer supported */ |
||||
HW_GENERATION_HCU2 = 0x10, |
||||
HW_GENERATION_HCU3 = 0x10, |
||||
HW_GENERATION_HCU4 = 0x20, |
||||
HW_GENERATION_HCU5 = 0x30, |
||||
HW_GENERATION_MCU = 0x08, |
||||
HW_GENERATION_MCU20 = 0x0a, |
||||
HW_GENERATION_MCU25 = 0x09, |
||||
}; |
||||
|
||||
|
||||
/*
|
||||
* This function is run very early, out of flash, and before devices are |
||||
* initialized. It is called by lib_ppc/board.c:board_init_f by virtue |
||||
* of being in the init_sequence array. |
||||
* |
||||
* The SDRAM has been initialized already -- start.S:start called |
||||
* init.S:init_sdram early on -- but it is not yet being used for |
||||
* anything, not even stack. So be careful. |
||||
*/ |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
u32 reg; |
||||
|
||||
#ifdef BOOTSTRAP_OPTION_A_ACTIVE |
||||
/* Booting with Bootstrap Option A
|
||||
* First boot, with CPR0_ICFG_RLI_MASK == 0 |
||||
* no we setup varios boot strapping register, |
||||
* then we do reset the PPC440 using a chip reset |
||||
* Unfortunately, we cannot use this option, as Nto1 is not set |
||||
* with Bootstrap Option A and cannot be changed later on by SW |
||||
* There are no other possible boostrap options with a 8 bit ROM |
||||
* See Errata (Version 1.04) CHIP_9 |
||||
*/ |
||||
|
||||
u32 cpr0icfg; |
||||
u32 dbcr; |
||||
|
||||
mfcpr(CPR0_ICFG, cpr0icfg); |
||||
if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) { |
||||
mtcpr(CPR0_MALD, 0x02000000); |
||||
mtcpr(CPR0_OPBD, 0x02000000); |
||||
mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */ |
||||
mtcpr(CPR0_PLLC, 0x40000238); |
||||
mtcpr(CPR0_PLLD, 0x01010414); |
||||
mtcpr(CPR0_PRIMAD, 0x01000000); |
||||
mtcpr(CPR0_PRIMBD, 0x01000000); |
||||
mtcpr(CPR0_SPCID, 0x03000000); |
||||
mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */ |
||||
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ |
||||
mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK); |
||||
|
||||
/*
|
||||
* Initiate system reset in debug control register DBCR |
||||
*/ |
||||
dbcr = mfspr(dbcr0); |
||||
mtspr(dbcr0, dbcr | CHIP_RESET); |
||||
} |
||||
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ |
||||
#endif |
||||
mtdcr(ebccfga, xbcfg); |
||||
mtdcr(ebccfgd, 0xb8400000); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins |
||||
*-------------------------------------------------------------------*/ |
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */ |
||||
out32(GPIO0_OR, 0x00000000); |
||||
out32(GPIO0_TCR, 0x7C2FF1CF); |
||||
out32(GPIO0_OSRL, 0x40055000); |
||||
out32(GPIO0_OSRH, 0x00000000); |
||||
out32(GPIO0_TSRL, 0x40055000); |
||||
out32(GPIO0_TSRH, 0x00000400); |
||||
out32(GPIO0_ISR1L, 0x40000000); |
||||
out32(GPIO0_ISR1H, 0x00000000); |
||||
out32(GPIO0_ISR2L, 0x00000000); |
||||
out32(GPIO0_ISR2H, 0x00000000); |
||||
out32(GPIO0_ISR3L, 0x00000000); |
||||
out32(GPIO0_ISR3H, 0x00000000); |
||||
|
||||
out32(GPIO1_OR, 0x00000000); |
||||
out32(GPIO1_TCR, 0xC6007FFF); |
||||
out32(GPIO1_OSRL, 0x00140000); |
||||
out32(GPIO1_OSRH, 0x00000000); |
||||
out32(GPIO1_TSRL, 0x00000000); |
||||
out32(GPIO1_TSRH, 0x00000000); |
||||
out32(GPIO1_ISR1L, 0x05415555); |
||||
out32(GPIO1_ISR1H, 0x40000000); |
||||
out32(GPIO1_ISR2L, 0x00000000); |
||||
out32(GPIO1_ISR2H, 0x00000000); |
||||
out32(GPIO1_ISR3L, 0x00000000); |
||||
out32(GPIO1_ISR3H, 0x00000000); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
*-------------------------------------------------------------------*/ |
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic0er, 0x00000000); /* disable all */ |
||||
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ |
||||
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ |
||||
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ |
||||
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic1er, 0x00000000); /* disable all */ |
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
||||
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ |
||||
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */ |
||||
mtdcr(uic2er, 0x00000000); /* disable all */ |
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */ |
||||
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ |
||||
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ |
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */ |
||||
mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ |
||||
mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ |
||||
|
||||
/* PCI arbiter enabled */ |
||||
mfsdr(sdr_pci0, reg); |
||||
mtsdr(sdr_pci0, 0x80000000 | reg); |
||||
|
||||
pci_pre_init(0); |
||||
|
||||
/* setup BOOT FLASH */ |
||||
mtsdr(SDR0_CUST0, 0xC0082350); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_pre_init(void) |
||||
{ |
||||
return board_early_init_f(); |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
unsigned int j; |
||||
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; |
||||
u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER; |
||||
u16 generation = *boardVersReg & 0xf0; |
||||
u16 index = *boardVersReg & 0x0f; |
||||
u32 ecid0, ecid1, ecid2, ecid3; |
||||
|
||||
printf("Netstal Maschinen AG: "); |
||||
if (generation == HW_GENERATION_HCU3) |
||||
printf("HCU3: index %d", index); |
||||
else if (generation == HW_GENERATION_HCU4) |
||||
printf("HCU4: index %d", index); |
||||
else if (generation == HW_GENERATION_HCU5) |
||||
printf("HCU5: index %d", index); |
||||
printf(" HW 0x%02x\n", *hwVersReg & 0xff); |
||||
mfsdr(SDR0_ECID0, ecid0); |
||||
mfsdr(SDR0_ECID1, ecid1); |
||||
mfsdr(SDR0_ECID2, ecid2); |
||||
mfsdr(SDR0_ECID3, ecid3); |
||||
|
||||
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3); |
||||
for (j = 0;j < 6; j++) { |
||||
sysLedSet(1 << j); |
||||
udelay(200 * 1000); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
u32 sysLedGet(void) |
||||
{ |
||||
return in16(SYS_IO_ADDRESS) & 0x3f; |
||||
} |
||||
|
||||
void sysLedSet(u32 value /* value to place in LEDs */) |
||||
{ |
||||
out16(SYS_IO_ADDRESS, value); |
||||
} |
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* getSerialNr |
||||
*---------------------------------------------------------------------------*/ |
||||
static u32 getSerialNr(void) |
||||
{ |
||||
u32 *serial = (u32 *)CFG_FLASH_BASE; |
||||
|
||||
if (*serial == 0xffffffff) |
||||
return get_ticks(); |
||||
|
||||
return *serial; |
||||
} |
||||
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* misc_init_r. |
||||
*---------------------------------------------------------------------------*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
char *s = getenv(DEFAULT_ETH_ADDR); |
||||
char *e; |
||||
int i; |
||||
u32 serial = getSerialNr(); |
||||
unsigned long usb2d0cr = 0; |
||||
unsigned long usb2phy0cr, usb2h0cr = 0; |
||||
unsigned long sdr0_pfc1; |
||||
|
||||
for (i = 0; i < 6; ++i) { |
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0; |
||||
if (s) |
||||
s = (*e) ? e + 1 : e; |
||||
} |
||||
|
||||
if (gd->bd->bi_enetaddr[3] == 0 && |
||||
gd->bd->bi_enetaddr[4] == 0 && |
||||
gd->bd->bi_enetaddr[5] == 0) { |
||||
char ethaddr[22]; |
||||
|
||||
/* Must be in sync with CONFIG_ETHADDR */ |
||||
gd->bd->bi_enetaddr[0] = 0x00; |
||||
gd->bd->bi_enetaddr[1] = 0x60; |
||||
gd->bd->bi_enetaddr[2] = 0x13; |
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff; |
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff; |
||||
/* byte[5].bit 0 must be zero */ |
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe; |
||||
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0", |
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1], |
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3], |
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ; |
||||
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__, |
||||
ethaddr, serial); |
||||
setenv(DEFAULT_ETH_ADDR, ethaddr); |
||||
} |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* Monitor protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
-CFG_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
|
||||
/* Env protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
/*
|
||||
* USB stuff... |
||||
*/ |
||||
|
||||
/* SDR Setting */ |
||||
mfsdr(SDR0_PFC1, sdr0_pfc1); |
||||
mfsdr(SDR0_USB2D0CR, usb2d0cr); |
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
||||
|
||||
/* An 8-bit/60MHz interface is the only possible alternative
|
||||
when connecting the Device to the PHY */ |
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ |
||||
|
||||
/* To enable the USB 2.0 Device function through the UTMI interface */ |
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
||||
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ |
||||
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ |
||||
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1); |
||||
mtsdr(SDR0_USB2D0CR, usb2d0cr); |
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr); |
||||
|
||||
/*clear resets*/ |
||||
udelay(1000); |
||||
mtsdr(SDR0_SRST1, 0x00000000); |
||||
udelay(1000); |
||||
mtsdr(SDR0_SRST0, 0x00000000); |
||||
|
||||
printf("USB: Host(int phy) Device(ext phy)\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int pci_pre_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned long addr; |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. |
||||
* Workaround: Disable write pipelining to DDR SDRAM by setting |
||||
* PLB0_ACR[WRP] = 0. |
||||
*-------------------------------------------------------------------*/ |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0. |
||||
| Set PLB3 arbiter to fair mode. |
||||
+-------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp1, addr); |
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb3_acr); |
||||
/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ |
||||
mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0. |
||||
+-------------------------------------------------------------------*/ |
||||
mfsdr(sdr_amp0, addr); |
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
||||
/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */ |
||||
mtdcr(plb4_acr, addr); /* Sequoia */ |
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode. |
||||
+-------------------------------------------------------------------*/ |
||||
/* Segment0 */ |
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
||||
/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */ |
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */ |
||||
|
||||
/* mtdcr(plb0_acr, addr); */ /* Sequoia */ |
||||
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ |
||||
|
||||
/* Segment1 */ |
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
||||
addr = (addr & ~plb1_acr_wrp_mask) ; |
||||
/* mtdcr(plb1_acr, addr); */ /* Sequoia */ |
||||
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller *hose) |
||||
{ |
||||
/*-------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers |
||||
*-------------------------------------------------------------*/ |
||||
/*-------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration. |
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space. |
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address |
||||
| 0xA0000000-0xDFFFFFFF |
||||
| Use byte reversed out routines to handle endianess. |
||||
| Make this region non-prefetchable. |
||||
+-------------------------------------------------------------*/ |
||||
/* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM0MA, 0x00000000); |
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
||||
/* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); |
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
/* 512M + No prefetching, and enable region */ |
||||
out32r(PCIX0_PMM0MA, 0xE0000001); |
||||
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */ |
||||
out32r(PCIX0_PMM1MA, 0x00000000); |
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
||||
/* PMM0 PCI Low Address */ |
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); |
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
||||
/* 512M + No prefetching, and enable region */ |
||||
out32r(PCIX0_PMM1MA, 0xE0000001); |
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
||||
|
||||
/*------------------------------------------------------------------+
|
||||
* Set up Configuration registers |
||||
*------------------------------------------------------------------*/ |
||||
|
||||
/* Program the board's subsystem id/vendor id */ |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
||||
CFG_PCI_SUBSYS_VENDORID); |
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
||||
|
||||
/* Configure command register as bus master */ |
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
||||
|
||||
/* 240nS PCI clock */ |
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
||||
|
||||
/* No error reporting */ |
||||
pci_write_config_word(0, PCI_ERREN, 0); |
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
||||
void pci_master_init(struct pci_controller *hose) |
||||
{ |
||||
unsigned short temp_short; |
||||
|
||||
/*---------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs. |
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM). |
||||
+--------------------------------------------------------------*/ |
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short); |
||||
pci_write_config_word(0, PCI_COMMAND, |
||||
temp_short | PCI_COMMAND_MASTER | |
||||
PCI_COMMAND_MEMORY); |
||||
} |
||||
#endif |
||||
/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
@ -0,0 +1,79 @@ |
||||
/* |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <config.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/************************************************************************** |
||||
* TLB TABLE |
||||
* |
||||
* This table is used by the cpu boot code to setup the initial tlb |
||||
* entries. Rather than make broad assumptions in the cpu source tree, |
||||
* this table lets each board set things up however they like. |
||||
* |
||||
* Pointer to the table is returned in r1 |
||||
* |
||||
*************************************************************************/ |
||||
.section .bootpg,"ax" |
||||
.globl tlbtab
|
||||
|
||||
tlbtab: |
||||
tlbtab_start |
||||
|
||||
/* vxWorks needs this entry for the Machine Check interrupt, */ |
||||
/* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ |
||||
|
||||
/* |
||||
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the |
||||
* speed up boot process. It is patched after relocation to enable SA_I |
||||
*/ |
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) |
||||
|
||||
/* TLB-entry for PCI Memory */ |
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) |
||||
|
||||
/* TLB-entry for EBC (CFG_CPLD) */ |
||||
/* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */ |
||||
/* CAN */ |
||||
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
/* IMC + CPLD */ |
||||
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
/* IMC-Fast */ |
||||
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
|
||||
/* TLB-entry for Internal Registers & OCM */ |
||||
tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) |
||||
|
||||
/*TLB-entry PCI registers*/ |
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
|
||||
/* TLB-entry for peripherals */ |
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
||||
|
||||
/* TLB for SDRAM will be added by initdram (sdram.c) */ |
||||
|
||||
tlbtab_end |
||||
@ -0,0 +1,302 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* (C) Copyright 2006 |
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com |
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com |
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* define DEBUG for debug output */ |
||||
#undef DEBUG |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/mmu.h> |
||||
#include <ppc440.h> |
||||
|
||||
void sysLedSet(u32 value); |
||||
void dcbz_area(u32 start_address, u32 num_bytes); |
||||
void dflush(void); |
||||
|
||||
#define DDR_DCR_BASE 0x10 |
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ |
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ |
||||
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF |
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000 |
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF |
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 |
||||
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ |
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 |
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 |
||||
|
||||
#define DDR0_22 0x16 |
||||
/* ECC */ |
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000 |
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */ |
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */ |
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/ |
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */ |
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) |
||||
|
||||
#ifdef CFG_ENABLE_SDRAM_CACHE |
||||
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */ |
||||
#else |
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */ |
||||
#endif |
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); |
||||
|
||||
#ifdef CONFIG_ADD_RAM_INFO |
||||
void board_add_ram_info(int use_default) |
||||
{ |
||||
PPC440_SYS_INFO board_cfg; |
||||
u32 val; |
||||
mfsdram(DDR0_22, val); |
||||
val &= DDR0_22_CTRL_RAW_MASK; |
||||
switch (val) { |
||||
case DDR0_22_CTRL_RAW_ECC_DISABLE: |
||||
puts(" (ECC disabled"); |
||||
break; |
||||
case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY: |
||||
puts(" (ECC check only"); |
||||
break; |
||||
case DDR0_22_CTRL_RAW_NO_ECC_RAM: |
||||
puts(" (no ECC ram"); |
||||
break; |
||||
case DDR0_22_CTRL_RAW_ECC_ENABLE: |
||||
puts(" (ECC enabled"); |
||||
break; |
||||
} |
||||
|
||||
get_sys_info(&board_cfg); |
||||
printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000); |
||||
|
||||
mfsdram(DDR0_03, val); |
||||
val = DDR0_03_CASLAT_DECODE(val); |
||||
printf(", CL%d)", val); |
||||
} |
||||
#endif |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* wait_for_dlllock. |
||||
*--------------------------------------------------------------------*/ |
||||
static int wait_for_dlllock(void) |
||||
{ |
||||
unsigned long val; |
||||
int wait = 0; |
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration |
||||
* ----------------------------------------------------------*/ |
||||
mtdcr(ddrcfga, DDR0_17); |
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED; |
||||
|
||||
while (wait != 0xffff) { |
||||
val = mfdcr(ddrcfgd); |
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) == |
||||
DDR0_17_DLLLOCKREG_LOCKED) |
||||
/* dlllockreg bit on */ |
||||
return 0; |
||||
else |
||||
wait++; |
||||
} |
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); |
||||
debug("Waiting for dlllockreg bit to raise\n"); |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
/***********************************************************************
|
||||
* |
||||
* sdram_panic -- Panic if we cannot configure the sdram correctly |
||||
* |
||||
************************************************************************/ |
||||
void sdram_panic(const char *reason) |
||||
{ |
||||
printf("\n%s: reason %s", __FUNCTION__, reason); |
||||
sysLedSet(0xff); |
||||
while (1) { |
||||
} |
||||
/* Never return */ |
||||
} |
||||
|
||||
#ifdef CONFIG_DDR_ECC |
||||
static void blank_string(int size) |
||||
{ |
||||
int i; |
||||
|
||||
for (i=0; i<size; i++) |
||||
putc('\b'); |
||||
for (i=0; i<size; i++) |
||||
putc(' '); |
||||
for (i=0; i<size; i++) |
||||
putc('\b'); |
||||
} |
||||
/*---------------------------------------------------------------------------+
|
||||
* program_ecc. |
||||
*---------------------------------------------------------------------------*/ |
||||
static void program_ecc(unsigned long start_address, unsigned long num_bytes, |
||||
unsigned long tlb_word2_i_value) |
||||
{ |
||||
unsigned long current_address= start_address; |
||||
int loopi = 0; |
||||
u32 val; |
||||
|
||||
char str[] = "ECC generation -"; |
||||
char slash[] = "\\|/-\\|/-"; |
||||
|
||||
sync(); |
||||
eieio(); |
||||
|
||||
puts(str); |
||||
|
||||
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { |
||||
/* ECC bit set method for non-cached memory */ |
||||
/* This takes various seconds */ |
||||
for(current_address = 0; current_address < num_bytes; |
||||
current_address += sizeof(u32)) { |
||||
*(u32 *)current_address = 0; |
||||
if ((current_address % (2 << 20)) == 0) { |
||||
putc('\b'); |
||||
putc(slash[loopi++ % 8]); |
||||
} |
||||
} |
||||
} else { |
||||
/* ECC bit set method for cached memory */ |
||||
/* Fast method, no noticeable delay */ |
||||
dcbz_area(start_address, num_bytes); |
||||
dflush(); |
||||
} |
||||
blank_string(strlen(str)); |
||||
|
||||
/* Clear error status */ |
||||
mfsdram(DDR0_00, val); |
||||
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); |
||||
|
||||
/* Set 'int_mask' parameter to functionnal value */ |
||||
mfsdram(DDR0_01, val); |
||||
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | |
||||
DDR0_01_INT_MASK_ALL_OFF)); |
||||
|
||||
return; |
||||
} |
||||
|
||||
#endif |
||||
|
||||
/***********************************************************************
|
||||
* |
||||
* initdram -- 440EPx's DDR controller is a DENALI Core |
||||
* |
||||
************************************************************************/ |
||||
long int initdram (int board_type) |
||||
{ |
||||
#define HCU_HW_SDRAM_CONFIG_MASK 0x7 |
||||
#define INVALID_HW_CONFIG "Invalid HW-Config" |
||||
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER; |
||||
unsigned int dram_size = 0; |
||||
|
||||
mtsdram(DDR0_02, 0x00000000); |
||||
|
||||
/* Values must be kept in sync with Excel-table <<A0001492.>> ! */ |
||||
mtsdram(DDR0_00, 0x0000190A); |
||||
mtsdram(DDR0_01, 0x01000000); |
||||
mtsdram(DDR0_03, 0x02030602); |
||||
mtsdram(DDR0_04, 0x0A020200); |
||||
mtsdram(DDR0_05, 0x02020307); |
||||
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) { |
||||
case 0: |
||||
dram_size = 128 * 1024 * 1024 ; |
||||
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ |
||||
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ |
||||
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ |
||||
break; |
||||
case 1: |
||||
dram_size = 256 * 1024 * 1024 ; |
||||
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ |
||||
mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ |
||||
mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ |
||||
break; |
||||
default: |
||||
sdram_panic(INVALID_HW_CONFIG); |
||||
break; |
||||
} |
||||
dram_size -= 16 * 1024 * 1024; |
||||
mtsdram(DDR0_07, 0x00090100); |
||||
/*
|
||||
* TCPD=200 cycles of clock input is required to lock the DLL. |
||||
* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); |
||||
*/ |
||||
mtsdram(DDR0_08, 0x02C80001); |
||||
mtsdram(DDR0_09, 0x00011D5F); |
||||
mtsdram(DDR0_10, 0x00000100); |
||||
mtsdram(DDR0_12, 0x00000003); |
||||
mtsdram(DDR0_14, 0x00000000); |
||||
mtsdram(DDR0_17, 0x1D000000); |
||||
mtsdram(DDR0_18, 0x1D1D1D1D); |
||||
mtsdram(DDR0_19, 0x1D1D1D1D); |
||||
mtsdram(DDR0_20, 0x0B0B0B0B); |
||||
mtsdram(DDR0_21, 0x0B0B0B0B); |
||||
#define ECC_RAM 0x03267F0B |
||||
#define NO_ECC_RAM 0x00267F0B |
||||
#ifdef CONFIG_DDR_ECC |
||||
mtsdram(DDR0_22, ECC_RAM); |
||||
#else |
||||
mtsdram(DDR0_22, NO_ECC_RAM); |
||||
#endif |
||||
|
||||
mtsdram(DDR0_23, 0x00000000); |
||||
mtsdram(DDR0_24, 0x01020001); |
||||
mtsdram(DDR0_26, 0x2D930517); |
||||
mtsdram(DDR0_27, 0x00008236); |
||||
mtsdram(DDR0_28, 0x00000000); |
||||
mtsdram(DDR0_31, 0x00000000); |
||||
mtsdram(DDR0_42, 0x01000006); |
||||
mtsdram(DDR0_44, 0x00000003); |
||||
mtsdram(DDR0_02, 0x00000001); |
||||
wait_for_dlllock(); |
||||
mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ |
||||
|
||||
/*
|
||||
* Program tlb entries for this size (dynamic) |
||||
*/ |
||||
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); |
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual |
||||
* address with cache enabled. This is done for fast ECC generation. |
||||
*/ |
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); |
||||
|
||||
#ifdef CONFIG_DDR_ECC |
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits. |
||||
*/ |
||||
program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0); |
||||
#endif |
||||
|
||||
return (dram_size); |
||||
} |
||||
@ -0,0 +1,144 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
|
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); |
||||
|
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,51 @@ |
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o update.o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,24 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
@ -0,0 +1,133 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/ppc4xx/start.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,105 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
#include <i2c.h> |
||||
|
||||
#if defined(CONFIG_ZEUS) |
||||
|
||||
u8 buf_zeus_ce[] = { |
||||
/*00 01 02 03 04 05 06 07 */ |
||||
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*08 09 0a 0b 0c 0d 0e 0f */ |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*10 11 12 13 14 15 16 17 */ |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*18 19 1a 1b 1c 1d 1e 1f */ |
||||
0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 }; |
||||
|
||||
u8 buf_zeus_pe[] = { |
||||
|
||||
/* CPU_CLOCK_DIV 1 = 00
|
||||
CPU_PLB_FREQ_DIV 3 = 10 |
||||
OPB_PLB_FREQ_DIV 2 = 01 |
||||
EBC_PLB_FREQ_DIV 2 = 00 |
||||
MAL_PLB_FREQ_DIV 1 = 00 |
||||
PCI_PLB_FRQ_DIV 3 = 10 |
||||
PLL_PLLOUTA = IS SET |
||||
PLL_OPERATING = IS NOT SET |
||||
PLL_FDB_MUL 10 = 1010 |
||||
PLL_FWD_DIV_A 3 = 101 |
||||
PLL_FWD_DIV_B 3 = 101 |
||||
TUNE = 0x2be */ |
||||
/*00 01 02 03 04 05 06 07 */ |
||||
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*08 09 0a 0b 0c 0d 0e 0f */ |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*10 11 12 13 14 15 16 17 */ |
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
||||
/*18 19 1a 1b 1c 1d 1e 1f */ |
||||
0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 }; |
||||
|
||||
static int update_boot_eeprom(void) |
||||
{ |
||||
u32 len = 0x20; |
||||
u8 chip = CFG_I2C_EEPROM_ADDR; |
||||
u8 *pbuf; |
||||
u8 base; |
||||
int i; |
||||
|
||||
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) { |
||||
pbuf = buf_zeus_pe; |
||||
base = 0x40; |
||||
} else { |
||||
pbuf = buf_zeus_ce; |
||||
base = 0x00; |
||||
} |
||||
|
||||
for (i = 0; i < len; i++, base++) { |
||||
if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) { |
||||
printf("i2c_write fail\n"); |
||||
return 1; |
||||
} |
||||
udelay(11000); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) |
||||
{ |
||||
return update_boot_eeprom(); |
||||
} |
||||
|
||||
U_BOOT_CMD ( |
||||
update_boot_eeprom, 1, 1, do_update_boot_eeprom, |
||||
"update_boot_eeprom - update boot eeprom content\n", |
||||
NULL |
||||
); |
||||
|
||||
#endif |
||||
@ -0,0 +1,511 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <malloc.h> |
||||
#include <environment.h> |
||||
#include <logbuff.h> |
||||
#include <post.h> |
||||
|
||||
#include <asm/processor.h> |
||||
#include <asm/io.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define REBOOT_MAGIC 0x07081967 |
||||
#define REBOOT_NOP 0x00000000 |
||||
#define REBOOT_DO_POST 0x00000001 |
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
extern env_t *env_ptr; |
||||
extern uchar default_environment[]; |
||||
|
||||
ulong flash_get_size(ulong base, int banknum); |
||||
void env_crc_update(void); |
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
||||
|
||||
static u32 start_time; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr(uicer, 0x00000000); /* disable all ints */ |
||||
mtdcr(uiccr, 0x00000000); |
||||
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */ |
||||
mtdcr(uictr, 0x00000000); /* set int trigger levels */ |
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
||||
|
||||
/*
|
||||
* Configure CPC0_PCI to enable PerWE as output |
||||
*/ |
||||
mtdcr(cpc0_pci, CPC0_PCI_SPE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
u32 pbcr; |
||||
int size_val = 0; |
||||
u32 post_magic; |
||||
u32 post_val; |
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC); |
||||
post_val = in_be32((void *)CFG_POST_VAL); |
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) { |
||||
/*
|
||||
* Set special bootline bootparameter to pass this POST boot |
||||
* mode to Linux to reset the username/password |
||||
*/ |
||||
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes"); |
||||
|
||||
/*
|
||||
* Normally don't run POST tests, only when enabled |
||||
* via the sw-reset button. So disable further tests |
||||
* upon next bootup here. |
||||
*/ |
||||
out_be32((void *)CFG_POST_VAL, REBOOT_NOP); |
||||
} else { |
||||
/*
|
||||
* Only run POST when initiated via the sw-reset button mechanism |
||||
*/ |
||||
post_word_store(0); |
||||
} |
||||
|
||||
/*
|
||||
* Get current time |
||||
*/ |
||||
start_time = get_timer(0); |
||||
|
||||
/*
|
||||
* FLASH stuff... |
||||
*/ |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
|
||||
/* adjust flash start and offset */ |
||||
mfebc(pb0cr, pbcr); |
||||
switch (gd->bd->bi_flashsize) { |
||||
case 1 << 20: |
||||
size_val = 0; |
||||
break; |
||||
case 2 << 20: |
||||
size_val = 1; |
||||
break; |
||||
case 4 << 20: |
||||
size_val = 2; |
||||
break; |
||||
case 8 << 20: |
||||
size_val = 3; |
||||
break; |
||||
case 16 << 20: |
||||
size_val = 4; |
||||
break; |
||||
case 32 << 20: |
||||
size_val = 5; |
||||
break; |
||||
case 64 << 20: |
||||
size_val = 6; |
||||
break; |
||||
case 128 << 20: |
||||
size_val = 7; |
||||
break; |
||||
} |
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
||||
mtebc(pb0cr, pbcr); |
||||
|
||||
/*
|
||||
* Re-check to get correct base address |
||||
*/ |
||||
flash_get_size(gd->bd->bi_flashstart, 0); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
-CFG_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
|
||||
/* Env protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
int checkboard(void) |
||||
{ |
||||
char *s = getenv("serial#"); |
||||
|
||||
puts("Board: Zeus-"); |
||||
|
||||
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) |
||||
puts("PE"); |
||||
else |
||||
puts("CE"); |
||||
|
||||
puts(" of BulletEndPoint"); |
||||
|
||||
if (s != NULL) { |
||||
puts(", serial# "); |
||||
puts(s); |
||||
} |
||||
putc('\n'); |
||||
|
||||
/* both LED's off */ |
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0); |
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0); |
||||
udelay(10000); |
||||
/* and on again */ |
||||
gpio_write_bit(CFG_GPIO_LED_RED, 1); |
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 1); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
static u32 detect_sdram_size(void) |
||||
{ |
||||
u32 val; |
||||
u32 size; |
||||
|
||||
mfsdram(mem_mb0cf, val); |
||||
size = (4 << 20) << ((val & 0x000e0000) >> 17); |
||||
|
||||
/*
|
||||
* Check if 2nd bank is enabled too |
||||
*/ |
||||
mfsdram(mem_mb1cf, val); |
||||
if (val & 1) |
||||
size += (4 << 20) << ((val & 0x000e0000) >> 17); |
||||
|
||||
return size; |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
return detect_sdram_size(); |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram(void) |
||||
{ |
||||
unsigned long *mem = (unsigned long *)0; |
||||
const unsigned long kend = (1024 / sizeof(unsigned long)); |
||||
unsigned long k, n; |
||||
unsigned long msr; |
||||
unsigned long total_kbytes; |
||||
|
||||
total_kbytes = detect_sdram_size(); |
||||
|
||||
msr = mfmsr(); |
||||
mtmsr(msr & ~(MSR_EE)); |
||||
|
||||
for (k = 0; k < total_kbytes ; |
||||
++k, mem += (1024 / sizeof(unsigned long))) { |
||||
if ((k & 1023) == 0) { |
||||
printf("%3d MB\r", k / 1024); |
||||
} |
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0xaaaaaaaa) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
memset(mem, 0x55555555, 1024); |
||||
for (n = 0; n < kend; ++n) { |
||||
if (mem[n] != 0x55555555) { |
||||
printf("SDRAM test fails at: %08x\n", |
||||
(uint) & mem[n]); |
||||
return 1; |
||||
} |
||||
} |
||||
} |
||||
printf("SDRAM test passes\n"); |
||||
mtmsr(msr); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
static int default_env_var(char *buf, char *var) |
||||
{ |
||||
char *ptr; |
||||
char *val; |
||||
|
||||
/*
|
||||
* Find env variable |
||||
*/ |
||||
ptr = strstr(buf + 4, var); |
||||
if (ptr == NULL) { |
||||
printf("ERROR: %s not found!\n", var); |
||||
return -1; |
||||
} |
||||
ptr += strlen(var) + 1; |
||||
|
||||
/*
|
||||
* Now the ethaddr needs to be updated in the "normal" |
||||
* environment storage -> redundant flash. |
||||
*/ |
||||
val = ptr; |
||||
setenv(var, val); |
||||
printf("Updated %s from eeprom to %s!\n", var, val); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int restore_default(void) |
||||
{ |
||||
char *buf; |
||||
char *buf_save; |
||||
u32 crc; |
||||
|
||||
/*
|
||||
* Unprotect and erase environment area |
||||
*/ |
||||
flash_protect(FLAG_PROTECT_CLEAR, |
||||
CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, |
||||
&flash_info[0]); |
||||
|
||||
flash_sect_erase(CFG_ENV_ADDR_REDUND, |
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1); |
||||
|
||||
/*
|
||||
* Now restore default environment from U-Boot image |
||||
* -> ipaddr, serverip... |
||||
*/ |
||||
memset(env_ptr, 0, sizeof(env_t)); |
||||
memcpy(env_ptr->data, default_environment, ENV_SIZE); |
||||
#ifdef CFG_REDUNDAND_ENVIRONMENT |
||||
env_ptr->flags = 0xFF; |
||||
#endif |
||||
env_crc_update(); |
||||
gd->env_valid = 1; |
||||
|
||||
/*
|
||||
* Read board specific values from I2C EEPROM |
||||
* and set env variables accordingly |
||||
* -> ethaddr, eth1addr, serial# |
||||
*/ |
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); |
||||
if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, |
||||
(u8 *)buf, FACTORY_RESET_ENV_SIZE)) { |
||||
puts("\nError reading EEPROM!\n"); |
||||
} else { |
||||
crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4); |
||||
if (crc != *(u32 *)buf) { |
||||
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf); |
||||
return -1; |
||||
} |
||||
|
||||
default_env_var(buf, "ethaddr"); |
||||
buf += 8 + 18; |
||||
default_env_var(buf, "eth1addr"); |
||||
buf += 9 + 18; |
||||
default_env_var(buf, "serial#"); |
||||
} |
||||
|
||||
/*
|
||||
* Finally save updated env variables back to flash |
||||
*/ |
||||
saveenv(); |
||||
|
||||
free(buf_save); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
char *buf; |
||||
char *buf_save; |
||||
char str[32]; |
||||
u32 crc; |
||||
char var[32]; |
||||
|
||||
if (argc < 4) { |
||||
puts("ERROR!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); |
||||
memset(buf, 0, FACTORY_RESET_ENV_SIZE); |
||||
|
||||
strcpy(var, "ethaddr"); |
||||
printf("Setting %s to %s\n", var, argv[1]); |
||||
sprintf(str, "%s=%s", var, argv[1]); |
||||
strcpy(buf + 4, str); |
||||
buf += strlen(str) + 1; |
||||
|
||||
strcpy(var, "eth1addr"); |
||||
printf("Setting %s to %s\n", var, argv[2]); |
||||
sprintf(str, "%s=%s", var, argv[2]); |
||||
strcpy(buf + 4, str); |
||||
buf += strlen(str) + 1; |
||||
|
||||
strcpy(var, "serial#"); |
||||
printf("Setting %s to %s\n", var, argv[3]); |
||||
sprintf(str, "%s=%s", var, argv[3]); |
||||
strcpy(buf + 4, str); |
||||
|
||||
crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4); |
||||
*(u32 *)buf_save = crc; |
||||
|
||||
if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, |
||||
(u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) { |
||||
puts("\nError writing EEPROM!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
free(buf_save); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
setdef, 4, 1, do_set_default, |
||||
"setdef - write board-specific values to EEPROM (ethaddr...)\n", |
||||
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n" |
||||
); |
||||
|
||||
static inline int sw_reset_pressed(void) |
||||
{ |
||||
return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET)); |
||||
} |
||||
|
||||
int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) |
||||
{ |
||||
int delta; |
||||
int count = 0; |
||||
int post = 0; |
||||
int factory_reset = 0; |
||||
|
||||
if (!sw_reset_pressed()) { |
||||
printf("SW-Reset already high (Button released)\n"); |
||||
printf("-> No action taken!\n"); |
||||
return 0; |
||||
} |
||||
|
||||
printf("Waiting for SW-Reset button to be released."); |
||||
|
||||
while (1) { |
||||
delta = get_timer(start_time); |
||||
if (!sw_reset_pressed()) |
||||
break; |
||||
|
||||
if ((delta > CFG_TIME_POST) && !post) { |
||||
printf("\nWhen released now, POST tests will be started."); |
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0); |
||||
post = 1; |
||||
} |
||||
|
||||
if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) { |
||||
printf("\nWhen released now, factory default values" |
||||
" will be restored."); |
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0); |
||||
factory_reset = 1; |
||||
} |
||||
|
||||
udelay(1000); |
||||
if (!(count++ % 1000)) |
||||
printf("."); |
||||
} |
||||
|
||||
|
||||
printf("\nSW-Reset Button released after %d milli-seconds!\n", delta); |
||||
|
||||
if (delta > CFG_TIME_FACTORY_RESET) { |
||||
printf("Starting factory reset value restoration...\n"); |
||||
|
||||
/*
|
||||
* Restore default setting |
||||
*/ |
||||
restore_default(); |
||||
|
||||
/*
|
||||
* Reset the board for default to become valid |
||||
*/ |
||||
do_reset(NULL, 0, 0, NULL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
if (delta > CFG_TIME_POST) { |
||||
printf("Starting POST configuration...\n"); |
||||
|
||||
/*
|
||||
* Enable POST upon next bootup |
||||
*/ |
||||
out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC); |
||||
out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST); |
||||
post_bootmode_init(); |
||||
|
||||
/*
|
||||
* Reset the logbuffer for a clean start |
||||
*/ |
||||
logbuff_reset(); |
||||
|
||||
do_reset(NULL, 0, 0, NULL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD ( |
||||
chkreset, 1, 1, do_chkreset, |
||||
"chkreset- Check for status of SW-reset button and act accordingly\n", |
||||
NULL |
||||
); |
||||
|
||||
#if defined(CONFIG_POST) |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
u32 post_magic; |
||||
u32 post_val; |
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC); |
||||
post_val = in_be32((void *)CFG_POST_VAL); |
||||
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) |
||||
return 1; |
||||
else |
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_POST */ |
||||
@ -0,0 +1,73 @@ |
||||
|
||||
Storage of the board specific values (ethaddr...) |
||||
------------------------------------------------- |
||||
|
||||
The board specific environment variables that should be unique |
||||
for each individual board, can be stored in the I2C EEPROM. This |
||||
will be done from offset 0x80 with the length of 0x80 bytes. The |
||||
following command can be used to store the values here: |
||||
|
||||
=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001 |
||||
|
||||
ethaddr eth1addr serial# |
||||
|
||||
Now those 3 values are stored into the I2C EEPROM. A CRC is added |
||||
to make sure that the values get not corrupted. |
||||
|
||||
|
||||
SW-Reset Pushbutton handling: |
||||
----------------------------- |
||||
|
||||
The SW-reset push button is connected to a GPIO input too. This |
||||
way U-Boot can "see" how long the SW-reset was pressed, and a |
||||
specific action can be taken. Two different actions are supported: |
||||
|
||||
a) Release after more than 5 seconds and less then 10 seconds: |
||||
-> Run POST |
||||
|
||||
Please note, that the POST test will take a while (approx. 1 min |
||||
on the 128MByte board). This is mainly due to the system memory |
||||
test. |
||||
|
||||
b) Release after more than 10 seconds: |
||||
-> Restore factory default settings |
||||
|
||||
The factory default values are restored. The default environment |
||||
variables are restored (ipaddr, serverip...) and the board |
||||
specific values (ethaddr, eth1addr and serial#) are restored |
||||
to the environment from the I2C EEPROM. Also a bootline parameter |
||||
is added to the Linux bootline to signal the Linux kernel upon |
||||
the next startup, that the factory defaults should be restored. |
||||
|
||||
The command to check this sw-reset status and act accordingly is |
||||
|
||||
=> chkreset |
||||
|
||||
This command is added to the default "bootcmd", so that it is called |
||||
automatically upon startup. |
||||
|
||||
Also, the 2 LED's are used to indicate the current status of this |
||||
command (time passed since pushing the button). When the POST test |
||||
will be run, the green LED will be switched off, and when the |
||||
factory restore will be initiated, the reg LED will be switched off. |
||||
|
||||
|
||||
Loggin of POST results: |
||||
----------------------- |
||||
|
||||
The results of the POST tests are logged in a logbuffer located at the end |
||||
of the onboard memory. It can be accessed with the U-Boot command "log": |
||||
|
||||
=> log show |
||||
<4>POST memory PASSED |
||||
<4>POST cache PASSED |
||||
<4>POST cpu PASSED |
||||
<4>POST uart PASSED |
||||
<4>POST ethernet PASSED |
||||
|
||||
The DENX Linux kernel tree has support for this log buffer included. Exactly |
||||
this buffer is used for logging of all kernel messages too. By enabling the |
||||
compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you |
||||
can access the U-Boot log messages from Linux too. |
||||
|
||||
2007-08-10, Stefan Roese <sr@denx.de> |
||||
@ -0,0 +1,156 @@ |
||||
/*
|
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_DTT_DS1775 |
||||
#include <i2c.h> |
||||
#include <dtt.h> |
||||
|
||||
#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */ |
||||
|
||||
int dtt_read(int sensor, int reg) |
||||
{ |
||||
int dlen; |
||||
uchar data[2]; |
||||
|
||||
/*
|
||||
* Calculate sensor address and command |
||||
*/ |
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */ |
||||
|
||||
/*
|
||||
* Prepare to handle 2 byte result |
||||
*/ |
||||
if ((reg == DTT_READ_TEMP) || |
||||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) |
||||
dlen = 2; |
||||
else |
||||
dlen = 1; |
||||
|
||||
/*
|
||||
* Now try to read the register |
||||
*/ |
||||
if (i2c_read(sensor, reg, 1, data, dlen) != 0) |
||||
return 1; |
||||
|
||||
/*
|
||||
* Handle 2 byte result |
||||
*/ |
||||
if (dlen == 2) |
||||
return ((int)((short)data[1] + (((short)data[0]) << 8))); |
||||
|
||||
return (int) data[0]; |
||||
} |
||||
|
||||
|
||||
int dtt_write(int sensor, int reg, int val) |
||||
{ |
||||
int dlen; |
||||
uchar data[2]; |
||||
|
||||
/*
|
||||
* Calculate sensor address and register |
||||
*/ |
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); |
||||
|
||||
/*
|
||||
* Handle various data sizes |
||||
*/ |
||||
if ((reg == DTT_READ_TEMP) || |
||||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) { |
||||
dlen = 2; |
||||
data[0] = (char)((val >> 8) & 0xff); /* MSB first */ |
||||
data[1] = (char)(val & 0xff); |
||||
} else { |
||||
dlen = 1; |
||||
data[0] = (char)(val & 0xff); |
||||
} |
||||
|
||||
/*
|
||||
* Write value to device |
||||
*/ |
||||
if (i2c_write(sensor, reg, 1, data, dlen) != 0) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
static int _dtt_init(int sensor) |
||||
{ |
||||
int val; |
||||
|
||||
/*
|
||||
* Setup High Temp |
||||
*/ |
||||
val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; |
||||
if (dtt_write(sensor, DTT_TEMP_OS, val) != 0) |
||||
return 1; |
||||
udelay(50000); /* Max 50ms */ |
||||
|
||||
/*
|
||||
* Setup Low Temp - hysteresis |
||||
*/ |
||||
val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; |
||||
if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) |
||||
return 1; |
||||
udelay(50000); /* Max 50ms */ |
||||
|
||||
/*
|
||||
* Setup configuraton register |
||||
* |
||||
* Fault Tolerance limits 4, Thermometer resolution bits is 9, |
||||
* Polarity = Active Low,continuous conversion mode, Thermostat |
||||
* mode is interrupt mode |
||||
*/ |
||||
val = 0xa; |
||||
if (dtt_write(sensor, DTT_CONFIG, val) != 0) |
||||
return 1; |
||||
udelay(50000); /* Max 50ms */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int dtt_init (void) |
||||
{ |
||||
int i; |
||||
unsigned char sensors[] = CONFIG_DTT_SENSORS; |
||||
|
||||
for (i = 0; i < sizeof(sensors); i++) { |
||||
if (_dtt_init(sensors[i]) != 0) |
||||
printf("DTT%d: FAILED\n", i+1); |
||||
else |
||||
printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
int dtt_get_temp(int sensor) |
||||
{ |
||||
return (dtt_read(sensor, DTT_READ_TEMP) / 256); |
||||
} |
||||
|
||||
|
||||
#endif /* CONFIG_DTT_DS1775 */ |
||||
@ -0,0 +1,348 @@ |
||||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* hcu4.h - configuration for HCU4 board (similar to hcu5.h) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HCU4 1 /* Board is HCU4 */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */ |
||||
#define CONFIG_405GP 1 |
||||
#define CONFIG_4xx 1 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
|
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
|
||||
/* ... with on-chip memory here (4KBytes) */ |
||||
#define CFG_OCM_DATA_ADDR 0xF4000000 |
||||
#define CFG_OCM_DATA_SIZE 0x00001000 |
||||
/* Do not set up locked dcache as init ram. */ |
||||
#undef CFG_INIT_DCACHE_CS |
||||
|
||||
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE |
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
/*
|
||||
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
||||
* If CFG_405_UART_ERRATA_59, then UART divisor is 31. |
||||
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. |
||||
* The Linux BASE_BAUD define should match this configuration. |
||||
* baseBaud = cpuClock/(uartDivisor*16) |
||||
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, |
||||
* set Linux BASE_BAUD to 403200. |
||||
*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#undef CONFIG_SERIAL_MULTI /* needed to be able to define |
||||
CONFIG_SERIAL_SOFTWARE_FIFO */ |
||||
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
|
||||
/* Size (bytes) of interrupt driven serial port buffer.
|
||||
* Set to 0 to use polling instead of interrupts. |
||||
* Setting to 0 will also disable RTS/CTS handshaking. |
||||
*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
|
||||
/* Set console baudrate to 9600 */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_IS_IN_EEPROM |
||||
#undef CFG_ENV_IS_NOWHERE |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
/* Put the environment after the SDRAM configuration */ |
||||
#define PROM_SIZE 2048 |
||||
#define CFG_ENV_OFFSET 512 |
||||
#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* Put the environment in Flash */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the |
||||
* the first internal I2C controller of the PPC440EPx |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SPD_BUS_NUM 0 |
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* This is the 7bit address of the device, not including P. */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#undef CFG_I2C_MULTI_EEPROMS |
||||
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
/* Setup some board specific values for the default environment variables */ |
||||
#define CONFIG_HOSTNAME hcu4 |
||||
#define CONFIG_IPADDR 172.25.1.42 |
||||
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
#define CONFIG_SERVERIP 172.25.1.3 |
||||
|
||||
#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"loadaddr=0x01000000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/hcu4/uImage\0" \
|
||||
"load=tftp 100000 hcu4/u-boot.bin\0" \
|
||||
"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
|
||||
"cp.b 100000 FFFa0000 60000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"vx=tftp ${loadaddr} hcu4_vx_rom;" \
|
||||
"setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
|
||||
" h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
|
||||
"bootvx ${loadaddr}\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run vx" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
|
||||
#define CONFIG_HAS_ETH0 |
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_BSP |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IMMAP |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SDRAM |
||||
|
||||
/* SPD EEPROM (sdram speed config) disabled */ |
||||
#define CONFIG_SPD_EEPROM 1 |
||||
#define SPD_EEPROM_ADDRESS 0x50 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */ |
||||
#define CFG_EBC_PB0AP 0x02005400 |
||||
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
#define CFG_EBC_PB1AP 0x03041200 |
||||
#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ |
||||
|
||||
#define CFG_EBC_PB2AP 0x02054500 |
||||
#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ |
||||
|
||||
#define CFG_EBC_PB3AP 0x01840300 |
||||
#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ |
||||
|
||||
#define CFG_EBC_PB4AP 0x01800300 |
||||
#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ |
||||
|
||||
#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* Init Memory Controller:
|
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
||||
|
||||
|
||||
/* Configuration Port location */ |
||||
#define CONFIG_PORT_ADDR 0xF0000500 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,393 @@ |
||||
/*
|
||||
* (C) Copyright 2007 Netstal Maschinen AG |
||||
* Niklaus Giger (Niklaus.Giger@netstal.com) |
||||
* |
||||
* (C) Copyright 2006-2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* (C) Copyright 2006 |
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* hcu5.h - configuration for HCU5 board (derived from sequoia.h) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HCU5 1 /* Board is HCU5 */ |
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
||||
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
|
||||
#define CFG_BOOT_BASE_ADDR 0xfff00000 |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_OCM_BASE 0xe0010000 /* ocm */ |
||||
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ |
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 |
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 |
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 |
||||
|
||||
/* Don't change either of these */ |
||||
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
||||
|
||||
#define CFG_USB2D0_BASE 0xe0000100 |
||||
#define CFG_USB_DEVICE 0xe0000000 |
||||
#define CFG_USB_HOST 0xe0000400 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer |
||||
*----------------------------------------------------------------------*/ |
||||
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
||||
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ |
||||
|
||||
#define CFG_INIT_RAM_END (4 << 10) |
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#undef CONFIG_SERIAL_MULTI /* needed to be able to define |
||||
CONFIG_SERIAL_SOFTWARE_FIFO, but |
||||
CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ |
||||
/* Size (bytes) of interrupt driven serial port buffer.
|
||||
* Set to 0 to use polling instead of interrupts. |
||||
* Setting to 0 will also disable RTS/CTS handshaking. |
||||
*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#undef CONFIG_UART1_CONSOLE |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
|
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_IS_IN_EEPROM |
||||
#undef CFG_ENV_IS_NOWHERE |
||||
|
||||
#ifdef CFG_ENV_IS_IN_EEPROM |
||||
/* Put the environment after the SDRAM and bootstrap configuration */ |
||||
#define PROM_SIZE 2048 |
||||
#define CFG_BOOSTRAP_OPTION_OFFSET 512 |
||||
#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) |
||||
#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* Put the environment in Flash */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ |
||||
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ |
||||
#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ |
||||
#define CONFIG_DDR_ECC 1 /* enable ECC */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the |
||||
* the second internal I2C controller of the PPC440EPx |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SPD_BUS_NUM 1 |
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* This is the 7bit address of the device, not including P. */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#undef CFG_I2C_MULTI_EEPROMS |
||||
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
/* Setup some board specific values for the default environment variables */ |
||||
#define CONFIG_HOSTNAME hcu5 |
||||
#define CONFIG_IPADDR 172.25.1.42 |
||||
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
#define CONFIG_SERVERIP 172.25.1.3 |
||||
|
||||
#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"loadaddr=0x01000000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"bootfile=hcu5/uImage\0" \
|
||||
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
|
||||
"load=tftp 100000 hcu5/u-boot.bin\0" \
|
||||
"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
|
||||
"cp.b 100000 FFFa0000 60000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
|
||||
"setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
|
||||
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
|
||||
"bootvx ${loadaddr}\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run vx" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_M88E1111_PHY 1 |
||||
#define CONFIG_IBM_EMAC4_V4 1 |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
||||
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
|
||||
#define CONFIG_HAS_ETH0 |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
||||
#define CONFIG_PHY1_ADDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
/* Comment this out to enable USB 1.1 device */ |
||||
#define USB_2_0_DEVICE |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_BSP |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IMMAP |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_USB |
||||
|
||||
#define CONFIG_SUPPORT_VFAT |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_TARGET_INIT |
||||
#define CFG_PCI_MASTER_INIT |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_FLASH CFG_FLASH_BASE |
||||
#define CFG_CS_1 0xC8000000 /* CAN */ |
||||
#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ |
||||
#define CFG_CPLD CFG_CS_2 |
||||
#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
* Memory Bank 0 (BOOT-FLASH) initialization |
||||
*/ |
||||
#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ |
||||
#define CFG_EBC_PB0AP 0x02005400 |
||||
#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ |
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ |
||||
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* Memory Bank 1 CAN-Chips initialization */ |
||||
#define CFG_EBC_PB1AP 0x02054500 |
||||
#define CFG_EBC_PB1CR 0xC8018000 |
||||
|
||||
/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ |
||||
#define CFG_EBC_PB2AP 0x01840300 |
||||
#define CFG_EBC_PB2CR 0xCC0BA000 |
||||
|
||||
/* Memory Bank 3 IMC-Bus fast mode initialization */ |
||||
#define CFG_EBC_PB3AP 0x01800300 |
||||
#define CFG_EBC_PB3CR 0xCE0BA000 |
||||
|
||||
/* Memory Bank 4 (not used) initialization */ |
||||
#undef CFG_EBC_PB4AP |
||||
#undef CFG_EBC_PB4CR |
||||
|
||||
/* Memory Bank 5 (not used) initialization */ |
||||
#undef CFG_EBC_PB5AP |
||||
#undef CFG_EBC_PB5CR |
||||
|
||||
#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) |
||||
#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,476 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2005-2007 |
||||
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
||||
#define CONFIG_4xx 1 /* member of PPC4xx family */ |
||||
#define CONFIG_TAIHU 1 /* on a taihu board */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_NO_SERIAL_EEPROM |
||||
|
||||
/*----------------------------------------------------------------------------*/ |
||||
#ifdef CONFIG_NO_SERIAL_EEPROM |
||||
|
||||
/*
|
||||
!------------------------------------------------------------------------------- |
||||
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, |
||||
! assuming a 33MHz input clock to the 405EP from the C9531. |
||||
!------------------------------------------------------------------------------- |
||||
*/ |
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3) |
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ |
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1) |
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ |
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 |
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 |
||||
#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 |
||||
#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 |
||||
|
||||
#endif |
||||
/*----------------------------------------------------------------------------*/ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bootfile=/tftpboot/taihu/uImage\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"kernel_addr=FC000000\0" \
|
||||
"ramdisk_addr=FC180000\0" \
|
||||
"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
|
||||
"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
|
||||
"cp.b 200000 FFFC0000 40000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0x14 /* PHY address */ |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
||||
#define CONFIG_PHY_RESET 1 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_SPI |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ |
||||
#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ |
||||
#define CFG_SDRAM_BANKS 2 |
||||
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
||||
*/ |
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ |
||||
|
||||
/* SDRAM timings used in datasheet */ |
||||
#define CFG_SDRAM_CL 3 /* CAS latency */ |
||||
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ |
||||
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ |
||||
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
||||
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
/*
|
||||
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
||||
* If CFG_405_UART_ERRATA_59, then UART divisor is 31. |
||||
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. |
||||
* The Linux BASE_BAUD define should match this configuration. |
||||
* baseBaud = cpuClock/(uartDivisor*16) |
||||
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, |
||||
* set Linux BASE_BAUD to 403200. |
||||
*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_UART1_CONSOLE 1 |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
|
||||
#define CONFIG_SOFT_SPI |
||||
#define SPI_SCL spi_scl |
||||
#define SPI_SDA spi_sda |
||||
#define SPI_READ spi_read() |
||||
#define SPI_DELAY udelay(2) |
||||
#ifndef __ASSEMBLY__ |
||||
void spi_scl(int); |
||||
void spi_sda(int); |
||||
unsigned char spi_read(void); |
||||
#endif |
||||
|
||||
/* standard dtt sensor configuration */ |
||||
#define CONFIG_DTT_DS1775 1 |
||||
#define CONFIG_DTT_SENSORS { 0 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
#define CONFIG_EEPRO100 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFFE00000 |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_ADDR0 0x555 |
||||
#define CFG_FLASH_ADDR1 0x2aa |
||||
#define CFG_FLASH_WORD_SIZE unsigned short |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif /* CFG_ENV_IS_IN_FLASH */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
||||
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM |
||||
#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
||||
#define CFG_ENV_ADDR \ |
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC405 GPIO Configuration |
||||
*/ |
||||
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ |
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
|
||||
} \
|
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash/SRAM) initialization */ |
||||
#define CFG_EBC_PB0AP 0x03815600 |
||||
#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */ |
||||
#define CFG_EBC_PB1AP 0x05815600 |
||||
#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 2 (USB device) initialization */ |
||||
#define CFG_EBC_PB2AP 0x03016600 |
||||
#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 3 (LCM and D-flip-flop) initialization */ |
||||
#define CFG_EBC_PB3AP 0x158FF600 |
||||
#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 4 (not install) initialization */ |
||||
#define CFG_EBC_PB4AP 0x158FF600 |
||||
#define CFG_EBC_PB4CR 0x5021A000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific) |
||||
* |
||||
* GPIO0[0] - External Bus Controller BLAST output |
||||
* GPIO0[1-9] - Instruction trace outputs |
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||
* GPIO0[28-29] - UART1 data signal input/output |
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
||||
*/ |
||||
#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ |
||||
#define CFG_GPIO0_OSRL 0x00000110 |
||||
#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ |
||||
#define CFG_GPIO0_ISR1L 0x15545440 |
||||
#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ |
||||
#define CFG_GPIO0_TSRL 0x00000000 |
||||
#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ |
||||
#define CFG_GPIO0_ODR 0x00000000 /* open drain */ |
||||
|
||||
#define GPIO0 0 /* GPIO controller 0 */ |
||||
|
||||
/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ |
||||
|
||||
#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) |
||||
#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) |
||||
#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) |
||||
#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) |
||||
#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) |
||||
|
||||
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ |
||||
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ |
||||
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ |
||||
#define GPIO_IS2(x) (x+GPIOx_IS1L) |
||||
#define GPIO_IS3(x) (x+GPIOx_IS1L) |
||||
|
||||
#define CPLD_REG0_ADDR 0x50100000 |
||||
#define CPLD_REG1_ADDR 0x50100001 |
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,382 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* zeus.h - configuration for Zeus board |
||||
***********************************************************************/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_ZEUS 1 /* Board is Zeus */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_405EP 1 /* Specifc 405EP support*/ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_111 |
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_111 |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0x01 /* PHY address */ |
||||
#define CONFIG_HAS_ETH1 1 |
||||
#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
||||
#define CONFIG_PHY_RESET 1 |
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_LOG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CFG_POST_MEMORY | \ |
||||
CFG_POST_CPU | \
|
||||
CFG_POST_CACHE | \
|
||||
CFG_POST_UART | \
|
||||
CFG_POST_ETHER) |
||||
|
||||
#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ |
||||
|
||||
/* Define here the base-addresses of the UARTs to test in POST */ |
||||
#define CFG_POST_UART_TABLE {UART0_BASE} |
||||
|
||||
#define CONFIG_LOGBUFFER |
||||
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ |
||||
|
||||
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
||||
*/ |
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ |
||||
|
||||
/* SDRAM timings used in datasheet */ |
||||
#define CFG_SDRAM_CL 3 /* CAS latency */ |
||||
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ |
||||
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ |
||||
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
||||
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
||||
#define CFG_BASE_BAUD 691200 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SERIAL_MULTI |
||||
|
||||
/* The following table includes the supported baudrates */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
#define CONFIG_LOOPW 1 /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* these are for the ST M24C02 2kbit serial i2c eeprom */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
/*
|
||||
* The layout of the I2C EEPROM, used for bootstrap setup and for board- |
||||
* specific values, like ethaddr... that can be restored via the sw-reset |
||||
* button |
||||
*/ |
||||
#define FACTORY_RESET_I2C_EEPROM 0x50 |
||||
#define FACTORY_RESET_ENV_OFFS 0x80 |
||||
#define FACTORY_RESET_ENV_SIZE 0x80 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */ |
||||
#define CFG_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
/* reserve some memory for POST and BOOT limit info */ |
||||
#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) |
||||
|
||||
/* extra data in OCM */ |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) |
||||
#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8) |
||||
#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash 16M) initialization */ |
||||
#define CFG_EBC_PB0AP 0x05815600 |
||||
#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific) |
||||
* |
||||
* GPIO0[0] - External Bus Controller BLAST output |
||||
* GPIO0[1-9] - Instruction trace outputs |
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs |
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs |
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs |
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs |
||||
* GPIO0[28-29] - UART1 data signal input/output |
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs |
||||
*/ |
||||
#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */ |
||||
#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ |
||||
#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ |
||||
#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ |
||||
#define CFG_GPIO0_TSRH 0x00000000 |
||||
#define CFG_GPIO0_TSRL 0x00000000 |
||||
#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ |
||||
#define CFG_GPIO0_ODR 0x00000000 |
||||
|
||||
#define CFG_GPIO_SW_RESET 1 |
||||
#define CFG_GPIO_ZEUS_PE 12 |
||||
#define CFG_GPIO_LED_RED 22 |
||||
#define CFG_GPIO_LED_GREEN 23 |
||||
|
||||
/* Time in milli-seconds */ |
||||
#define CFG_TIME_POST 5000 |
||||
#define CFG_TIME_FACTORY_RESET 10000 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/* ENVIRONMENT VARS */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" |
||||
#define CONFIG_IPADDR 192.168.1.10 |
||||
#define CONFIG_SERVERIP 192.168.1.100 |
||||
#define CONFIG_GATEWAYIP 192.168.1.100 |
||||
#define CONFIG_ETHADDR 50:00:00:00:06:00 |
||||
#define CONFIG_ETH1ADDR 50:00:00:00:06:01 |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"logversion=2\0" \
|
||||
"hostname=zeus\0" \
|
||||
"netdev=eth0\0" \
|
||||
"ethact=ppc_4xx_eth0\0" \
|
||||
"netmask=255.255.255.0\0" \
|
||||
"ramdisk_size=50000\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw" \
|
||||
" nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw" \
|
||||
" ramdisk=${ramdisk_size}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0," \
|
||||
"${baudrate}\0" \
|
||||
"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"run nfsargs addip addtty;bootm\0" \
|
||||
"net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
|
||||
"tftp ${ramdisk_mem_addr} ${file_fs};" \
|
||||
"run ramargs addip addtty;" \
|
||||
"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
|
||||
"rootpath=/target_fs/zeus\0" \
|
||||
"kernel_fl_addr=ff000000\0" \
|
||||
"kernel_mem_addr=200000\0" \
|
||||
"ramdisk_fl_addr=ff300000\0" \
|
||||
"ramdisk_mem_addr=4000000\0" \
|
||||
"uboot_fl_addr=fffc0000\0" \
|
||||
"uboot_mem_addr=100000\0" \
|
||||
"file_uboot=/zeus/u-boot.bin\0" \
|
||||
"tftp_uboot=tftp 100000 ${file_uboot}\0" \
|
||||
"update_uboot=protect off fffc0000 ffffffff;" \
|
||||
"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
|
||||
"protect on fffc0000 ffffffff\0" \
|
||||
"upd_uboot=run tftp_uboot;run update_uboot\0" \
|
||||
"file_kernel=/zeus/uImage_ba\0" \
|
||||
"tftp_kernel=tftp 100000 ${file_kernel}\0" \
|
||||
"update_kernel=protect off ff000000 ff17ffff;" \
|
||||
"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
|
||||
"upd_kernel=run tftp_kernel;run update_kernel\0" \
|
||||
"file_fs=/zeus/rootfs_ba.img\0" \
|
||||
"tftp_fs=tftp 100000 ${file_fs}\0" \
|
||||
"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
|
||||
"cp.b 100000 ff300000 580000\0" \
|
||||
"upd_fs=run tftp_fs;run update_fs\0" \
|
||||
"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
|
||||
"" |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,29 @@ |
||||
#
|
||||
# (C) Copyright 2002-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
|
||||
LIB = libpostlwmon5.a
|
||||
|
||||
COBJS = ecc.o
|
||||
|
||||
include $(TOPDIR)/post/rules.mk |
||||
@ -0,0 +1,267 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Developed for DENX Software Engineering GmbH. |
||||
* |
||||
* Author: Pavel Kolesnikov <concord@emcraft.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* define DEBUG for debugging output (obviously ;-)) */ |
||||
#if 0 |
||||
#define DEBUG |
||||
#endif |
||||
|
||||
#include <common.h> |
||||
#include <watchdog.h> |
||||
|
||||
#ifdef CONFIG_POST |
||||
|
||||
#include <post.h> |
||||
|
||||
#if CONFIG_POST & CFG_POST_ECC |
||||
|
||||
/*
|
||||
* MEMORY ECC test |
||||
* |
||||
* This test performs the checks ECC facility of memory. |
||||
*/ |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/io.h> |
||||
#include <ppc440.h> |
||||
|
||||
#include "../../../board/lwmon5/sdram.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
const static unsigned char syndrome_codes[] = { |
||||
0xF4, 0XF1, 0XEC ,0XEA, 0XE9, 0XE6, 0XE5, 0XE3, |
||||
0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB, |
||||
0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2, |
||||
0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A, |
||||
0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62, |
||||
0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A, |
||||
0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23, |
||||
0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B, |
||||
0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 |
||||
}; |
||||
|
||||
#define ECC_START_ADDR 0x10 |
||||
#define ECC_STOP_ADDR 0x2000 |
||||
#define ECC_PATTERN 0x0101010101010101ull |
||||
#define ECC_PATTERN_CORR 0x0101010101010100ull |
||||
#define ECC_PATTERN_UNCORR 0x010101010101010Full |
||||
|
||||
static int test_ecc_error(void) |
||||
{ |
||||
unsigned long value; |
||||
unsigned long hdata, ldata, haddr, laddr; |
||||
unsigned int bit; |
||||
|
||||
int ret = 0; |
||||
|
||||
mfsdram(DDR0_23, value); |
||||
|
||||
for (bit = 0; bit < sizeof(syndrome_codes); bit++) |
||||
if (syndrome_codes[bit] == ((value >> 16) & 0xff)) |
||||
break; |
||||
|
||||
mfsdram(DDR0_00, value); |
||||
|
||||
if (value & DDR0_00_INT_STATUS_BIT0) { |
||||
debug("Bit0. A single access outside the defined PHYSICAL" |
||||
" memory space detected\n"); |
||||
mfsdram(DDR0_32, laddr); |
||||
mfsdram(DDR0_33, haddr); |
||||
debug(" addr = 0x%08x%08x\n", haddr, laddr); |
||||
ret = 1; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT1) { |
||||
debug("Bit1. Multiple accesses outside the defined PHYSICAL" |
||||
" memory space detected\n"); |
||||
ret = 2; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT2) { |
||||
debug("Bit2. Single correctable ECC event detected\n"); |
||||
mfsdram(DDR0_38, laddr); |
||||
mfsdram(DDR0_39, haddr); |
||||
mfsdram(DDR0_40, ldata); |
||||
mfsdram(DDR0_41, hdata); |
||||
debug(" 0x%08x - 0x%08x%08x, bit - %d\n", |
||||
laddr, hdata, ldata, bit); |
||||
ret = 3; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT3) { |
||||
debug("Bit3. Multiple correctable ECC events detected\n"); |
||||
mfsdram(DDR0_38, laddr); |
||||
mfsdram(DDR0_39, haddr); |
||||
mfsdram(DDR0_40, ldata); |
||||
mfsdram(DDR0_41, hdata); |
||||
debug(" 0x%08x - 0x%08x%08x, bit - %d\n", |
||||
laddr, hdata, ldata, bit); |
||||
ret = 4; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT4) { |
||||
debug("Bit4. Single uncorrectable ECC event detected\n"); |
||||
mfsdram(DDR0_34, laddr); |
||||
mfsdram(DDR0_35, haddr); |
||||
mfsdram(DDR0_36, ldata); |
||||
mfsdram(DDR0_37, hdata); |
||||
debug(" 0x%08x - 0x%08x%08x, bit - %d\n", |
||||
laddr, hdata, ldata, bit); |
||||
ret = 5; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT5) { |
||||
debug("Bit5. Multiple uncorrectable ECC events detected\n"); |
||||
mfsdram(DDR0_34, laddr); |
||||
mfsdram(DDR0_35, haddr); |
||||
mfsdram(DDR0_36, ldata); |
||||
mfsdram(DDR0_37, hdata); |
||||
debug(" 0x%08x - 0x%08x%08x, bit - %d\n", |
||||
laddr, hdata, ldata, bit); |
||||
ret = 6; |
||||
} |
||||
if (value & DDR0_00_INT_STATUS_BIT6) { |
||||
debug("Bit6. DRAM initialization complete\n"); |
||||
ret = 7; |
||||
} |
||||
|
||||
/* error status cleared */ |
||||
mfsdram(DDR0_00, value); |
||||
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int test_ecc(unsigned long ecc_addr) |
||||
{ |
||||
volatile unsigned long long *ecc_mem; |
||||
unsigned long value; |
||||
unsigned long ecc_data; |
||||
volatile unsigned long *lecc_mem; |
||||
int pret, ret = 0; |
||||
|
||||
sync(); |
||||
eieio(); |
||||
WATCHDOG_RESET(); |
||||
|
||||
ecc_mem = (unsigned long long *)ecc_addr; |
||||
lecc_mem = (ulong *)ecc_addr; |
||||
*ecc_mem = ECC_PATTERN; |
||||
pret = test_ecc_error(); |
||||
if (pret != 0) |
||||
ret = 1; |
||||
|
||||
/* disconnect ecc */ |
||||
mfsdram(DDR0_22, value); |
||||
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) |
||||
| DDR0_22_CTRL_RAW_ECC_DISABLE); |
||||
|
||||
/* injecting error */ |
||||
*ecc_mem = ECC_PATTERN_CORR; |
||||
|
||||
/* enable ecc */ |
||||
mfsdram(DDR0_22, value); |
||||
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) |
||||
| DDR0_22_CTRL_RAW_ECC_ENABLE); |
||||
|
||||
ecc_data = *lecc_mem; |
||||
pret = test_ecc_error(); |
||||
/* if read data ok, 1 correctable error must be fixed */ |
||||
if (pret != 3) |
||||
ret = 1; |
||||
|
||||
/* test for uncorrectable error */ |
||||
/* disconnect from ecc storage */ |
||||
mfsdram(DDR0_22, value); |
||||
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) |
||||
| DDR0_22_CTRL_RAW_NO_ECC_RAM); |
||||
|
||||
/* injecting multiply bit error */ |
||||
|
||||
*ecc_mem = ECC_PATTERN_UNCORR; |
||||
|
||||
/* enable ecc */ |
||||
mfsdram(DDR0_22, value); |
||||
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) |
||||
| DDR0_22_CTRL_RAW_ECC_ENABLE); |
||||
|
||||
ecc_data = *lecc_mem; |
||||
/* what the data should be read? */ |
||||
|
||||
pret = test_ecc_error(); |
||||
/* info about uncorrectable error must appear */ |
||||
if (pret != 5) |
||||
ret = 1; |
||||
|
||||
sync(); |
||||
eieio(); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int ecc_post_test (int flags) |
||||
{ |
||||
int ret = 0; |
||||
unsigned long value; |
||||
unsigned long iaddr; |
||||
|
||||
#if CONFIG_DDR_ECC |
||||
sync(); |
||||
eieio(); |
||||
|
||||
/* mask all int */ |
||||
mfsdram(DDR0_01, value); |
||||
mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK) |
||||
| DDR0_01_INT_MASK_ALL_OFF); |
||||
|
||||
/* clear error status */ |
||||
mfsdram(DDR0_00, value); |
||||
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); |
||||
|
||||
/* enable full support of ECC */ |
||||
mfsdram(DDR0_22, value); |
||||
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) |
||||
| DDR0_22_CTRL_RAW_ECC_ENABLE); |
||||
|
||||
for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) { |
||||
ret = test_ecc(iaddr); |
||||
if (ret) |
||||
break; |
||||
} |
||||
|
||||
/* clear error status */ |
||||
mfsdram(DDR0_00, value); |
||||
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); |
||||
|
||||
/*
|
||||
* Clear possible errors resulting from ECC testing. |
||||
* If not done, then we could get an interrupt later on when |
||||
* exceptions are enabled. |
||||
*/ |
||||
set_mcsr(get_mcsr()); |
||||
#endif |
||||
|
||||
return ret; |
||||
|
||||
} |
||||
|
||||
#endif /* CONFIG_POST & CFG_POST_ECC */ |
||||
#endif /* CONFIG_POST */ |
||||
Loading…
Reference in new issue